Skip to content

Conversation

codygunton
Copy link
Contributor

@codygunton codygunton commented Sep 11, 2025

Companion of risc0/risc0#3421
According to the spec for jalr

The target address is obtained by adding the sign-extended 12-bit I-immediate to the register rs1, then setting the least-significant bit of the result to zero.

This masking is done in the emulator but not in the circuit. This PR implements the masking at the circuit level as well.

Copy link
Contributor

@jbruestle jbruestle left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants