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Fix jalr circuit #284

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Merged
merged 5 commits into from
Sep 23, 2025
+28 −23
Merged

Fix jalr circuit #284

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c9e6bb2
straightforwardly fix jalr
codygunton Sep 9, 2025
8bfea3f
fix from jeremy: range constraint half
codygunton Sep 10, 2025
012d6a3
update golden hashes
codygunton Sep 10, 2025
a0d8bdb
remove dedundant constraint
codygunton Sep 10, 2025
dc522a0
update golden hashes
codygunton Sep 10, 2025
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44 changes: 22 additions & 22 deletions zirgen/circuit/predicates/golden_hashes.txt
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27c35c723bd90e014c01c1d92deff2276b6b71367bac28e6b6404afaed700e11 lift_rv32im_v2_povw_19.zkr
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313519930b2efbe66101b3f24c295533be5247ac55377c4970bec1bca1e483af lift_rv32im_v2_povw_24.zkr
f99657cf182e53df3810e0c88b6e2aa10a17af9c086b93dbb941bf4ea17ebde7 test_recursion_circuit.zkr
730afd6be910247584675f02e0a578951118c141e37cfd0605afa3e112ef2361 join.zkr
25a75a2e9c29a30ed690363f119eb569bb40840e33de582beffae542ca066e51 join_povw.zkr
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7 changes: 6 additions & 1 deletion zirgen/circuit/rv32im/v2/dsl/inst_misc.zir
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Original file line number Diff line number Diff line change
Expand Up @@ -200,9 +200,14 @@ component OpJAL(input: MiscInput) {

component OpJALR(input: MiscInput) {
VerifyOpcodeF3(input.decoded, 0x67, 0x0);
unmasked := AddU32(input.rs1, input.decoded.immI);
lsb := NondetBitReg(unmasked.low & 1);
masked := unmasked.low - lsb;
half := NondetU16Reg(masked / 2);
masked = 2 * half;
MiscOutput(1,
AddU32(input.pc_u32, ConstU32<4>()),
AddU32(input.rs1, input.decoded.immI))
DenormedValU32(masked, unmasked.high))
}

component OpLUI(input: MiscInput) {
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