A64fx sst model

CMakeLists.txt

@@ -1,7 +1,7 @@
 cmake_minimum_required(VERSION 3.13)
 include(FetchContent)
 set(FETCHCONTENT_QUIET OFF)
-
+set(CMAKE_VERBOSE_MAKEFILE ON)
 # FetchContent_MakeAvailable was introduced in 3.14
 # there also isn't a version that accepts extra args at the end for add_subdirectory
 # hence we write one ourselves
@@ -122,6 +122,8 @@ option(SIMENG_ENABLE_TESTS "Whether to enable testing for SimEng" OFF)
 option(SIMENG_USE_EXTERNAL_LLVM "Use an external LLVM rather than building it as a submodule" OFF)
 option(SIMENG_SANITIZE "Enable compiler sanitizers" OFF)
 option(SIMENG_OPTIMIZE "Enable Extra Compiler Optimizatoins" OFF)
+option(SIMENG_ENABLE_SST "Compile SimEng SST Wrapper" OFF)
+option(SIMENG_ENABLE_SST_TESTS "Enable testing for SST" OFF)
 
 if (SIMENG_OPTIMIZE)
   # Turn on link time optimization for all targets.
@@ -219,3 +221,24 @@ endif()
 # include sources
 add_subdirectory(src)
 add_subdirectory(docs)
+
+if (SIMENG_ENABLE_SST)
+  if (SST_INSTALL_DIR)
+    add_subdirectory(sst)
+    if (SIMENG_ENABLE_SST_TESTS)
+      enable_testing()
+      list(APPEND CMAKE_CTEST_ARGUMENTS "--verbose")
+      add_custom_target(test-sst-simeng
+      COMMAND ${CMAKE_CTEST_COMMAND}
+      DEPENDS sstsimengtest
+      )
+    endif()
+  else()
+    message(WARNING "SST build was selected but SST install directory was not specified.
+    Please specify -DSST_INSTALL_DIR=<path> for the SST build to proceed.")  
+  endif()
+endif()
+
+# Install SimEng model configs in the build directory
+set(SIMENG_CONFIG_INSTALL_DIR "${CMAKE_BINARY_DIR}/simeng-configs")
+install(DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/configs/ DESTINATION ${SIMENG_CONFIG_INSTALL_DIR})

configs/sst-cores/a64fx-sst.yaml

@@ -0,0 +1,269 @@
+---
+# The following resources where utilised to create the config file and naming schemes:
+# https://github.com/fujitsu/A64FX
+
+Core:
+  Simulation-Mode: outoforder
+  # Clock Frequency is in GHz.
+  Clock-Frequency: 1.8
+  # Timer-Frequency is in MHz.
+  Timer-Frequency: 100
+  Micro-Operations: True
+  Vector-Length: 512
+Fetch:
+  Fetch-Block-Size: 32
+  Loop-Buffer-Size: 48
+  Loop-Detection-Threshold: 4
+Process-Image:
+  Heap-Size: 1073741824
+  Stack-Size: 1048576
+Register-Set:
+  GeneralPurpose-Count: 96
+  FloatingPoint/SVE-Count: 128
+  Predicate-Count: 48
+  Conditional-Count: 128
+Pipeline-Widths:
+  Commit: 4
+  FrontEnd: 4
+  LSQ-Completion: 2
+Queue-Sizes:
+  ROB: 128
+  Load: 40
+  Store: 24
+Branch-Predictor:
+  BTB-Tag-Bits: 11
+  Saturating-Count-Bits: 2
+  Global-History-Length: 11
+  RAS-entries: 8
+  Fallback-Static-Predictor: "Always-Taken"
+L1-Data-Memory:
+  Interface-Type: External
+L1-Instruction-Memory:
+  Interface-Type: Flat
+LSQ-L1-Interface:
+  Access-Latency: 5
+  Exclusive: True
+  Load-Bandwidth: 128
+  Store-Bandwidth: 64
+  Permitted-Requests-Per-Cycle: 2
+  Permitted-Loads-Per-Cycle: 2
+  Permitted-Stores-Per-Cycle: 1
+Ports:
+  0:
+    Portname: FLA
+    Instruction-Support:
+    - FP
+    - SVE
+  1:
+    Portname: PR
+    Instruction-Support:
+    - PREDICATE
+  2:
+    Portname: EXA
+    Instruction-Support:
+    - INT_SIMPLE
+    - INT_MUL
+    - STORE_DATA
+  3:
+    Portname: FLB
+    Instruction-Support:
+    - FP_SIMPLE
+    - FP_MUL
+    - SVE_SIMPLE
+    - SVE_MUL
+  4:
+    Portname: EXB
+    Instruction-Support:
+    - INT_SIMPLE
+    - INT_DIV_OR_SQRT
+  5:
+    Portname: EAGA
+    Instruction-Support:
+    - LOAD
+    - STORE_ADDRESS
+    - INT_SIMPLE_ARTH_NOSHIFT
+    - INT_SIMPLE_LOGICAL_NOSHIFT
+    - INT_SIMPLE_CMP
+  6:
+    Portname: EAGB
+    Instruction-Support:
+    - LOAD
+    - STORE_ADDRESS
+    - INT_SIMPLE_ARTH_NOSHIFT
+    - INT_SIMPLE_LOGICAL_NOSHIFT
+    - INT_SIMPLE_CMP
+  7:
+    Portname: BR
+    Instruction-Support:
+    - BRANCH
+Reservation-Stations:
+  0:
+    Size: 20
+    Dispatch-Rate: 2
+    Ports:
+    - FLA
+    - PR
+    - EXA
+  1:
+    Size: 20
+    Dispatch-Rate: 2
+    Ports:
+    - FLB
+    - EXB
+  2:
+    Size: 10
+    Dispatch-Rate: 2
+    Ports:
+    - EAGA
+  3:
+    Size: 10
+    Dispatch-Rate: 2
+    Ports:
+    - EAGB
+  4:
+    Size: 19
+    Dispatch-Rate: 2
+    Ports:
+    - BR
+Execution-Units:
+  0:
+    Pipelined: True
+    Blocking-Groups:
+    - INT_DIV_OR_SQRT
+    - FP_DIV_OR_SQRT
+    - SVE_DIV_OR_SQRT
+  1:
+    Pipelined: True
+    Blocking-Groups: 
+    - INT_DIV_OR_SQRT
+    - FP_DIV_OR_SQRT
+    - SVE_DIV_OR_SQRT
+  2:
+    Pipelined: True
+    Blocking-Groups: 
+    - INT_DIV_OR_SQRT
+    - FP_DIV_OR_SQRT
+    - SVE_DIV_OR_SQRT
+  3:
+    Pipelined: True
+    Blocking-Groups: 
+    - INT_DIV_OR_SQRT
+    - FP_DIV_OR_SQRT
+    - SVE_DIV_OR_SQRT
+  4:
+    Pipelined: True
+    Blocking-Groups: 
+    - INT_DIV_OR_SQRT
+    - FP_DIV_OR_SQRT
+    - SVE_DIV_OR_SQRT
+  5:
+    Pipelined: True
+    Blocking-Groups: 
+    - INT_DIV_OR_SQRT
+    - FP_DIV_OR_SQRT
+    - SVE_DIV_OR_SQRT
+  6:
+    Pipelined: True
+    Blocking-Groups: 
+    - INT_DIV_OR_SQRT
+    - FP_DIV_OR_SQRT
+    - SVE_DIV_OR_SQRT
+  7:
+    Pipelined: True
+    Blocking-Groups: 
+    - INT_DIV_OR_SQRT
+    - FP_DIV_OR_SQRT
+    - SVE_DIV_OR_SQRT
+Latencies:
+  0:
+    Instruction-Groups: 
+    - INT
+    Execution-Latency: 2
+    Execution-Throughput: 2
+  1:
+    Instruction-Groups: 
+    - INT_SIMPLE_ARTH_NOSHIFT
+    - INT_SIMPLE_LOGICAL_NOSHIFT
+    - INT_SIMPLE_CVT
+    Execution-Latency: 1
+    Execution-Throughput: 1
+  2:
+    Instruction-Groups: 
+    - INT_MUL
+    Execution-Latency: 5
+    Execution-Throughput: 1
+  3:
+    Instruction-Groups: 
+    - INT_DIV_OR_SQRT
+    Execution-Latency: 41
+    Execution-Throughput: 41
+  4:
+    Instruction-Groups: 
+    - SCALAR_SIMPLE
+    - VECTOR_SIMPLE_LOGICAL
+    - SVE_SIMPLE_LOGICAL
+    - VECTOR_SIMPLE_CMP
+    - SVE_SIMPLE_CMP
+    Execution-Latency: 4
+    Execution-Throughput: 1
+  5:
+    Instruction-Groups: 
+    - FP_DIV_OR_SQRT
+    Execution-Latency: 29
+    Execution-Throughput: 29
+  6:
+    Instruction-Groups: 
+    - VECTOR_SIMPLE
+    - SVE_SIMPLE
+    - SCALAR_SIMPLE_CVT
+    - FP_MUL
+    - SVE_MUL
+    Execution-Latency: 9
+    Execution-Throughput: 1
+  7:
+    Instruction-Groups: 
+    - SVE_DIV_OR_SQRT
+    Execution-Latency: 98
+    Execution-Throughput: 98
+  8:
+    Instruction-Groups: 
+    - PREDICATE
+    Execution-Latency: 3
+    Execution-Throughput: 1
+  9:
+    Instruction-Groups: 
+    - LOAD_SCALAR
+    - LOAD_VECTOR
+    - STORE_ADDRESS_SCALAR
+    - STORE_ADDRESS_VECTOR
+    Execution-Latency: 3
+    Execution-Throughput: 1
+  10:
+    Instruction-Groups: 
+    - LOAD_SVE
+    - STORE_ADDRESS_SVE
+    Execution-Latency: 6
+    Execution-Throughput: 1
+# CPU-Info mainly used to generate a replica of the special (or system) file directory 
+# structure
+CPU-Info:
+  # Set Generate-Special-Dir to True to generate the special files directory, or to False to not.
+  # (Not generating the special files directory may require the user to copy over files manually)
+  Generate-Special-Dir: True
+  # Core-Count MUST be 1 as multi-core is not supported at this time. (A64FX true value is 48)
+  Core-Count: 1
+  # Socket-Count MUST be 1 as multi-socket simulations are not supported at this time. (A64FX true value is 1)
+  Socket-Count: 1
+  # SMT MUST be 1 as Simultanious-Multi-Threading is not supported at this time. (A64FX true value is 1)
+  SMT: 1
+  # Below are the values needed to generate /proc/cpuinfo
+  BogoMIPS: 200.00
+  Features: fp asimd evtstrm sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm fcma dcpop sve
+  CPU-Implementer: "0x46"
+  CPU-Architecture: 8
+  CPU-Variant: "0x1"
+  CPU-Part: "0x001"
+  CPU-Revision: 0
+  # Package-Count is used to generate 
+  # /sys/devices/system/cpu/cpu{0..Core-Count}/topology/{physical_package_id, core_id}
+  Package-Count: 1