A64fx sst model #11
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A64fx sst model #11
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…ency, rather than update the VCT register to total cycles completed.
…m register (PMCCNTR_EL0 for Aarch64).
A fix for handling missing system registers in the aarch64 systemRegisterMap_ map. A missing entry will return a -1 and a decoded instruction accessing an unmapped system register will raise a new UnmappedSysReg fatal exception.
…ow for a wider param space (UoB-HPC#229)
Fixes output error present for miniBUDE when compiled with GCC-10.3.0 targeting armv8.4-a+sve, caused by an incorrect implementation of the FNEG sve instruction. Additionally, other SVE instructions were updated to accomodate for optional patterns.
…e Linux machines.
A new generic branch predictor containing parameterisable BTB and RAS structures, global indexing, and better identification of branch instructions. Additionally, a parameterisable loop buffer has been implemented in the fetch unit and a loop detection scheme in the ROB unit.
* Moved counter timer logic from main into Architecture, allowing the implementation to be architecture agnostic. * Added test for CNTVCT register. * Updated sveGetPattern auxiliary function to work for any instruction string. * Ensured all necessary SVE instructions included pattern recognition. * Changed specialFiles generation directory to be the build location. * Fixed AArch64_LD1RQ_D_IMM's invalid increments of its index variable. * Improved conditional branch not taken target and remove loop closing direction due to emergent bug. * Resolved LSQ bugs for comparisons against the total req limit and forwarding operands from flushed loads. * Updated comment in sveGetPattern Aux function.
This pull request updates SimEng to use the Armv9.2-update branch of the UoB-HPC Capstone Fork. Changes to the CMake files have been changed to reflect build changes in the upstream Capstone:next branch. A pre-upstreamed update to Capstone has been merged into the Armv9.2-update, which adds support for the AArch64 Armv9.2-a ISA (including SVE2 and SME instructions). As such, minor fixes have been made to accommodate changes to instruction enums, aliasing logic, and other changes.
This PR has reduced the number of unused copies of the memory image and thus reduced the memory requirements of a SimEng simulation. The process memory image is instantiated once through malloc/remalloc calls and shared between simulation objects through shared pointers.
This PR introduces a new CoreInstance class. The class supports the creation of a SimEng core model, storing all the relevant simulation objects within shared pointers. A key factor in this change being introduced was to improve the ease SimEng's interactions with other frameworks e.g. SST.
This PR adds prefixes to all SimEng outputs to help distinguish between simulated workload outputs and the outputs from the framework.
… cmake. (UoB-HPC#231) This PR implements the `SST` wrapper and `simeng::MemoryInterface` needed for successful integration with SST. It also adds support for conditional compilation through `CMake`.
…ency, rather than update the VCT register to total cycles completed.
…m register (PMCCNTR_EL0 for Aarch64).
A fix for handling missing system registers in the aarch64 systemRegisterMap_ map. A missing entry will return a -1 and a decoded instruction accessing an unmapped system register will raise a new UnmappedSysReg fatal exception.
…ow for a wider param space (UoB-HPC#229)
Fixes output error present for miniBUDE when compiled with GCC-10.3.0 targeting armv8.4-a+sve, caused by an incorrect implementation of the FNEG sve instruction. Additionally, other SVE instructions were updated to accomodate for optional patterns.
…e Linux machines.
A new generic branch predictor containing parameterisable BTB and RAS structures, global indexing, and better identification of branch instructions. Additionally, a parameterisable loop buffer has been implemented in the fetch unit and a loop detection scheme in the ROB unit.
This pull request updates SimEng to use the Armv9.2-update branch of the UoB-HPC Capstone Fork. Changes to the CMake files have been changed to reflect build changes in the upstream Capstone:next branch. A pre-upstreamed update to Capstone has been merged into the Armv9.2-update, which adds support for the AArch64 Armv9.2-a ISA (including SVE2 and SME instructions). As such, minor fixes have been made to accommodate changes to instruction enums, aliasing logic, and other changes.
This PR has reduced the number of unused copies of the memory image and thus reduced the memory requirements of a SimEng simulation. The process memory image is instantiated once through malloc/remalloc calls and shared between simulation objects through shared pointers.
This PR introduces a new CoreInstance class. The class supports the creation of a SimEng core model, storing all the relevant simulation objects within shared pointers. A key factor in this change being introduced was to improve the ease SimEng's interactions with other frameworks e.g. SST.
This PR adds prefixes to all SimEng outputs to help distinguish between simulated workload outputs and the outputs from the framework.
This PR moves the dispatch rate restriction from dispatch unit wide to the individual reservation stations. This improves the parameterization of the unit as a whole.
Includes a custom testing framework for SST, changes to CoreInstance to support execution of LLVM assembled instructions on SSTSimEng, Addition of Assembler class in SST, multiple SST tests (a64fx based), SST validation binaries and L1L2 SST config.
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