SinglePass: add support for riscv64 target

[marxin]

The PR adds the rudimentary support for RISC-V 64-bit target into the SinglePass compiler. Even though, the code still needs some polishing and various TODOs must be addressed, the compiler can pass all (104) the spec tests.

TODOs:

• unwinding support
• FP status register - save/restore
• a general location_cmp + jmp_on_X needs polishing as RISC-V target does not provide a FLAGS register (Singlepass: refactor condition jumps to single fn (jmp_on_condition) #5750).
• spec/address.wast is flaky (sometimes trap is not properly triggered)
• basic testing - all compiler tests (including the WASI tests) are green now
• include RISCV-V in CI by running the tests in qemu

Minor improvements:

• CLZ, CTZ and POPCOUNT have sub-optimal performance - could be implemented as builtins in the run-time (fn call overhead)
• still some unimplemented entry points for the Machine trait - wipe unused entry points in the Trait
• more intensive testing needed (including real hardware + valgrind)

[marxin]

All right, I switched the implementation of the Unreachable for the Singlepass in the PR to use the direct call to wasmer_vm_raise_trap.

@wakabat Just wanted to let you know that I've decided to skip the change from this initial PR, but it's going to come shortly after we merge this PR as it's a change that influences other targets as well.

Addressed in #5821.

[marxin]

@syrusakbary The PR is basically ready to be merged. However, it depends on a smaller tweaks to the CI when it comes to testing of riscv64gc target: #5817 #5815 #5809

[marxin]

The CI job Run WAST tests on linux-riscv64 is green when running in CI under QEMU. Yay!