Adding commercial flow for nangate45

[franout]

Added fixes and features to support the use of Nangate45 in the VLSI commercial flow.
Corrected typos in the technology file (stackup name) and added the grid_unit for metallizations.
Added a utility function to retrieve reset ports, which is useful for Design for Testability (DFT) insertion.

Related PRs / Issues
None

Type of change:

• Bug fix
• New feature
• Other enhancement

Impact:

• Change to core Hammer
• Change to a Hammer plugin (please see PR #36 in hammer-synopsys-plugin)
• Other

Contributor Checklist:

• Did you set master as the base branch?
• Did you state the type-of-change/impact?
• Did you delete any extraneous prints/debugging code?
• (If applicable) Did you add documentation for the feature?
• (If applicable) Did you update the poetry.lock file if you updated the requirements in pyproject.toml?
• (If applicable) Did you add a unit test demonstrating the PR?
• (If applicable) Did you run this through the e2e integration tests?
• (If applicable) Did you update the submodules in e2e/ if this feature depends on updated plugins?

[franout]

For the e2e tests, I do not have full acceess to the technology used in the chipyard framework (sky130 and asap7) for correctly run all the tests.

I do not know it makes sense to add a test for the get_reset_ports function (addeed in this PR).

[nayiri-k]

For the e2e tests, I do not have full acceess to the technology used in the chipyard framework (sky130 and asap7) for correctly run all the tests.

I'm working on creating an e2e test for the nangate45 setup, what is the best way to install nangate45? I'm only seeing it here.

[franout]

sorry to reach you back late, i was in a conference.

It looks fine, the only issue is the missing behavioural model for post synthesis simulation.

I am used to download the lib from here for research purposes.

I have implemented the tech.json file for the library distributed by Si2 in our fork of the hammer project.

[franout]

In my research group we are mainly involved in hardware testing and reliability...
Would you be interested if we implement the test pattern generation flow ( #894 ) and/or functional fault simulation flows (Z01X, VC Z01X from synopsys, or xcelium-based from cadence)?

[nayiri-k]

In my research group we are mainly involved in hardware testing and reliability... Would you be interested if we implement the test pattern generation flow ( #894 ) and/or functional fault simulation flows (Z01X, VC Z01X from synopsys, or xcelium-based from cadence)?

Yes absolutely! We don't directly work in this space but a test pattern generation flow sounds incredibly useful to have.

[franout]

@nayiri-k there may be a bug with the sram generated for the nangate45 tech (when running make sim-rtl in vlsi).
We are fixing it