Verilog

Experimental Verilog Support

Background

The primary purpose of this project is to provide bare-metal, Verilog-free capability. However, on occasions, it may be important to be able to embed fpgasm code into an existing Verilog project, or to be able to distribute your modules to users not equipped to handle fpgasm. Therefore, since the beginning of the project, I thought it would be important to someday be able to go to Verilog.

The main problem is that fpgasm allows you to configure primitives directly, by setting the appropriate "cfg" strings. Verilog does not go that low - you have to instantiate primitives like LUT4 or XORC that do not map directly to anything at all - not the "cfg"s, not xdlrc primitives. In fact it is quite a challenge to come up with a "cfg" to verilog converter. If anyone has a great idea of how to do that easily (or at least automatically based on .xdlrc files with minimum human interaction), please let me know.

The first step (already implemented) is a bit of a kluge. When defining a fpgasm module that contains primitives, you can add a parameter called "Verilog" and set its default value to a piece of Verilog code. Invoking fpgasm in verilog mode (target file has a .v extension) results in the fpgasm module hierarchy replicated in Verilog; any modules containing a "Verilog" parameter will simply expand to the default value.

Normally fpgasm top modules must not have any pins defined. For Verilog the top module should contain input and output pins that you will use to interface with the rest of your Verilog logic. It's a pretty good idea to separate our Veriloggable project into a separate file; you can convert it to Verilog or 'include' it into an fpgasm testbench for developtment. Similarly, the output Verilog file may be simply included into your Verilog project. Use common sense and enjoy.

While not very flexible, it gives you an immediate capability of outputting to Verilog, assuming you go through the trouble of creating the low-level Verilog definitions for your low-level modules. It's something anyway.

Verilog output is generally not a priority to me, so unless there is a strong demand (or a financial incentive), I will probably not be focusing on it in the near future.

Please contact me at fpgasm(AT)apple2.x10.mx - replace (AT) with an @, of course Home