PipelinedCPU

This project implements a bit-level CPU in Verilog, including both non-pipelined and 5-stage pipelined designs. The architecture is modular and structured into the following components:

🧩 Components

• Register File
  Handles general-purpose register reads and writes at the bit level.

• ALU
  Performs bit-level arithmetic and logic operations:

  • Addition
  • Subtraction
  • AND, OR, XOR

• CPU Architectures

  • 🟢 Non-Pipelined CPU
  • 🚀 5-Stage Pipelined CPU with:
    • Instruction fetch (IF), decode (ID), execute (EX), memory (MEM), and write-back (WB) stages
    • Hazard detection
    • Data forwarding
    • Stall control

✅ Testing

All modules are verified with:

• Unit tests for individual modules
• Integration tests for full system validation

▶️ Simulation Instructions (ModelSim)

1. Edit runlab.do
   Update the script to include the highest-level module you want to simulate

2. Open ModelSim
   Launch the ModelSim GUI in your project directory.

3. Run the simulation script
   In the ModelSim console, run:

   do runlab.do