This is a request for Sail to support marking a subset of PMPs as read-only zero. Designs must implement 0, 16, or 64 PMPs, but since they are WARL it is allowed to implement e.g. 64 but then have the last half of them ROZ giving you effectively 32 PMPs. Spike supports this.

I think initially just having a single integer to say how many PMPs are not ROZ (same as Spike's option) would be fine.

Original issue below.

Could it be that the "sail" function does not support "--pmp-count=32"? Here is the test command：
riscv_sim_RV64 --pmp-count=32
PMP count: 32
invalid PMP count: must be 0, 16 or 64

File1 Path:/riscof_work/pmp64/src/pmp64-CFG-reg.S/dut/DUT-Fpga.signature
File2 Path:/riscof_work/pmp64/src/pmp64-CFG-reg.S/ref/Reference-sail_c_simulator.signature
Match Line# File1 File2
9f9f9f9f deadbeef
9f9f9f9f deadbeef
9f9f9f9f deadbeef
9f9f9f9f deadbeef
000001ff 00000000
00000000 00000000
000001ff 00000000
00000000 00000000

3.7.1. Physical Memory Protection CSRs
PMP entries are described by an 8-bit configuration register and one MXLEN-bit address register. Some PMP settings additionally use the address register associated with the preceding PMP entry. Up to 64 PMP entries are supported. Implementations may implement zero, 16, or 64 PMP entries; the lowest-numbered PMP entries must be implemented first. All PMP CSR fields are WARL and may be read-only zero. PMP CSRs are only accessible to M-mode