feat: integrate LiteX SoC

.gitignore

@@ -10,3 +10,9 @@ metals.sbt
 
 .envrc
 .direnv/
+
+lite*/
+litex_setup.py
+pythondata*/
+valentyusb/
+migen/

Makefile

@@ -1,5 +1,7 @@
 BUILDDIR ?= build
+CPUDIR ?= cpu
 TARGET ?= ulx3s
+PORT ?= /dev/ttyUSB0
 
 all: synth
 
@@ -12,7 +14,7 @@ $(BUILDDIR)/Raster.sv: $(shell find src/main/scala -type f)
 $(BUILDDIR)/%:
 	@mkdir -p $@
 
-.PHONY: sim
+.PHONY: sim cpu
 sim: $(BUILDDIR)/Raster.sv $(BUILDDIR)/sim
 	@make -C sim run BUILDDIR=$(CURDIR)/$(BUILDDIR)/sim
 
@@ -25,5 +27,13 @@ prog: $(BUILDDIR)/Raster.sv $(BUILDDIR)/$(TARGET)
 flash: $(BUILDDIR)/Raster.sv $(BUILDDIR)/$(TARGET)
 	@make -C synth/$(TARGET) flash BUILDDIR=$(CURDIR)/$(BUILDDIR)/$(TARGET)
 
+cpu: FORCE
+	@make -C $(CPUDIR)
+
+cpu-test: $(CPUDIR)/bare-program
+	@PORT=$(PORT) make -C $(CPUDIR)/bare-program
+
 clean:
 	@rm -rf $(BUILDDIR)
+
+FORCE:

cpu/CPU.mk

@@ -0,0 +1,13 @@
+TARGET = radiona_ulx3s
+DEVICE = LFE5U-85F
+SDRAM = W9825G6KH6
+BUS ?= axi-lite
+CPU ?= vexriscv
+VARIANT ?= minimal+debug
+
+all: FORCE
+	@python3 -m litex_boards.targets.$(TARGET) \
+        --device $(DEVICE) --sdram-module $(SDRAM) \
+        --bus-standard $(BUS) --cpu-type $(CPU) \
+        --cpu-variant $(VARIANT) --build --load
+FORCE:

cpu/Makefile

@@ -0,0 +1,5 @@
+all: FORCE
+	@bash setup.sh
+	@make -C litex
+
+FORCE:

cpu/bare-program/.cargo/config.toml

@@ -0,0 +1,10 @@
+[target.riscv32i-unknown-none-elf]
+rustflags = [
+  "-C", "link-arg=-Tmemory.x",
+  "-C", "link-arg=-Tlink.x",
+  "-C", "linker-plugin-lto",
+]
+
+
+[build]
+target = "riscv32i-unknown-none-elf"

cpu/bare-program/.gitignore

@@ -0,0 +1,2 @@
+/target
+*.bin