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Enable RISC-V platform support #2

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4 changes: 4 additions & 0 deletions CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -75,6 +75,10 @@ elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "amd64.*|x86_64.*|AMD64.*")
set(CLConform_TARGET_ARCH x86_64)
elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "i686.*|i386.*|x86.*")
set(CLConform_TARGET_ARCH x86)
elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "riscv64")
set(CLConform_TARGET_ARCH RISCV64)
elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "riscv")
set(CLConform_TARGET_ARCH RISCV)
endif()

if(NOT DEFINED CLConform_TARGET_ARCH)
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6 changes: 6 additions & 0 deletions test_common/harness/fpcontrol.h
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Expand Up @@ -69,6 +69,8 @@ inline void ForceFTZ(FPU_mode_type *mode)
__asm__ volatile("msr fpcr, %0" ::"r"(fpscr | (1U << 24)));
#elif defined(__mips__)
fpa_bissr(FPA_CSR_FS);
#elif defined(__riscv)
#warning RISC-V platform does NOT support FTZ...
#else
#error ForceFTZ needs an implentation
#endif
Expand Down Expand Up @@ -97,6 +99,8 @@ inline void DisableFTZ(FPU_mode_type *mode)
__asm__ volatile("msr fpcr, %0" ::"r"(fpscr & ~(1U << 24)));
#elif defined(__mips__)
fpa_bicsr(FPA_CSR_FS);
#elif defined(__riscv)
#warning RISC-V platform does NOT support FTZ...
#else
#error DisableFTZ needs an implentation
#endif
Expand All @@ -117,6 +121,8 @@ inline void RestoreFPState(FPU_mode_type *mode)
__asm__ volatile("msr fpcr, %0" ::"r"(*mode));
#elif defined(__mips__)
// Mips runs by default with DAZ=1 FTZ=1
#elif defined(__riscv)
#warning RISC-V platform does NOT support FTZ...
#else
#error RestoreFPState needs an implementation
#endif
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5 changes: 5 additions & 0 deletions test_common/harness/rounding_mode.cpp
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Expand Up @@ -224,6 +224,9 @@ void *FlushToZero(void)
#elif defined(__mips__)
fpa_bissr(FPA_CSR_FS);
return NULL;
#elif defined(__riscv)
#warning RISC-V does NOT support FTZ...
return NULL;
#else
#error Unknown arch
#endif
Expand Down Expand Up @@ -254,6 +257,8 @@ void UnFlushToZero(void *p)
_FPU_SETCW(flags);
#elif defined(__mips__)
fpa_bicsr(FPA_CSR_FS);
#elif defined(__riscv)
#warning RISC-V does NOT support FTZ...
#else
#error Unknown arch
#endif
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2 changes: 2 additions & 0 deletions test_common/harness/testHarness.cpp
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Expand Up @@ -1374,6 +1374,8 @@ void PrintArch(void)
vlog("ARCH:\tWindows\n");
#elif defined(__mips__)
vlog("ARCH:\tmips\n");
#elif defined(__riscv)
vlog("ARCH:\riscv/riscv64\n");
#else
#error unknown arch
#endif
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