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This PR adds functionality into SimEng to support the AArch64 SME extension. 6 new SME instructions have been implemented, along with the SVCR Streaming-SVE-Mode context switching functionality. Additionally, the default LLVM version has been updated to 14.0.5 in order to support the SME regression tests. The AArch64 Instruction class now has a copy constructor, optimising the use of cached instructions. Updated Jenkin's pipeline scripts to work with LLVM 14 Changes the Capstone usage to fix an existing memory leak, as mentioned in Issue UoB-HPC#261.
Adds Integration with SST and a custom framework for testing SST
This pull request adds support for rv64iam. That is, 64 bit RISC-V base, atomic and multiply extensions working in all three simulation modes. Expanding on previous work, the general code base has been adjusted to be more ISA agnostic. Specific config option parsing has been moved to the ISA specific classes and the exception handler has become more generic. Some more work may be needed on this as exception types are currently ISA specific; this causes the need for repeated functions which is undesirable. Almost all of the base, atomic and multiply extension instructions have been implemented along with their pseudoinstructions. ### Architecture updates - rv64i - RISC-V base extension - a - RISC-V atomic extension - m - RISC-V multiply/divide extension ### Changes to config options - Addition of ```ISA``` option with valid arguments <```aarch64```, ```rv64```> ### To note - FENCE is implemented as a NOP which is considered allowable by the spec - EBREAK is unimplemented but only needed for debugging - Atomics don't operate truly atomically which is currently functional for single threaded programs but not accurate - MULH and MULHSU aren't implemented as they will need a library such as GMP. Tests are implemented and expected to fail This functionality is sufficient to run many benchmarks including STREAM, Dhrystone and an implementation of the Smith-Waterman algorithm.
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