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[FMV][AArch64] Remove feature sha1 from FMV. #108383

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Merged
merged 7 commits into from
Sep 27, 2024
Merged

[FMV][AArch64] Remove feature sha1 from FMV. #108383

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50820f4
[FMV][AArch64] Remove feature sha1 from FMV.
labrinea Sep 12, 2024
3fb81b4
Merge branch 'main' into fmv-remove-sha1
labrinea Sep 19, 2024
6c0485d
Changes from last revision:
labrinea Sep 19, 2024
d5e1b18
Merge branch 'main' into fmv-remove-sha1
labrinea Sep 20, 2024
c706082
Merge branch 'main' into fmv-remove-sha1
labrinea Sep 27, 2024
b1d4397
Merge branch 'main' into fmv-remove-sha1
labrinea Sep 27, 2024
927b913
Merge branch 'main' into fmv-remove-sha1
labrinea Sep 27, 2024
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3 changes: 0 additions & 3 deletions clang/test/CodeGen/aarch64-fmv-dependencies.c
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Original file line number Diff line number Diff line change
Expand Up @@ -111,9 +111,6 @@ __attribute__((target_version("rpres"))) int fmv(void) { return 0; }
// CHECK: define dso_local i32 @fmv._Msb() #[[sb:[0-9]+]] {
__attribute__((target_version("sb"))) int fmv(void) { return 0; }

// CHECK: define dso_local i32 @fmv._Msha1() #[[ATTR0:[0-9]+]] {
__attribute__((target_version("sha1"))) int fmv(void) { return 0; }

// CHECK: define dso_local i32 @fmv._Msha2() #[[sha2:[0-9]+]] {
__attribute__((target_version("sha2"))) int fmv(void) { return 0; }

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12 changes: 6 additions & 6 deletions clang/test/CodeGen/attr-target-version.c
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Expand Up @@ -24,7 +24,7 @@ int foo() {
return fmv()+fmv_one()+fmv_two();
}

inline int __attribute__((target_version("sha1+pmull+f64mm"))) fmv_inline(void) { return 1; }
inline int __attribute__((target_version("sha2+pmull+f64mm"))) fmv_inline(void) { return 1; }
inline int __attribute__((target_version("fp16+fcma+rdma+sme+ fp16 "))) fmv_inline(void) { return 2; }
inline int __attribute__((target_version("sha3+i8mm+f32mm"))) fmv_inline(void) { return 12; }
inline int __attribute__((target_version("dit+sve-ebf16"))) fmv_inline(void) { return 8; }
Expand Down Expand Up @@ -659,7 +659,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
//
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mf64mmMpmullMsha1
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mf64mmMpmullMsha2
// CHECK-SAME: () #[[ATTR23:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
Expand Down Expand Up @@ -805,12 +805,12 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
// CHECK-NEXT: ret ptr @fmv_inline._Msve2Msve2-bitpermMsve2-pmull128
// CHECK: resolver_else4:
// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 34359773184
// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 34359773184
// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 34359775232
// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 34359775232
// CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]]
// CHECK-NEXT: br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]]
// CHECK: resolver_return5:
// CHECK-NEXT: ret ptr @fmv_inline._Mf64mmMpmullMsha1
// CHECK-NEXT: ret ptr @fmv_inline._Mf64mmMpmullMsha2
// CHECK: resolver_else6:
// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 17246986240
Expand Down Expand Up @@ -1135,7 +1135,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
// CHECK: attributes #[[ATTR20]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+jsconv,+neon" }
// CHECK: attributes #[[ATTR21:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ls64" }
// CHECK: attributes #[[ATTR22]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sb" }
// CHECK: attributes #[[ATTR23]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+aes,+f64mm,+fp-armv8,+fullfp16,+neon,+sve" }
// CHECK: attributes #[[ATTR23]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+aes,+f64mm,+fp-armv8,+fullfp16,+neon,+sha2,+sve" }
// CHECK: attributes #[[ATTR24]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+complxnum,+fp-armv8,+fullfp16,+neon,+rdm,+sme" }
// CHECK: attributes #[[ATTR25]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f32mm,+fp-armv8,+fullfp16,+i8mm,+neon,+sha2,+sha3,+sve" }
// CHECK: attributes #[[ATTR26]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+dit,+fp-armv8,+fullfp16,+neon,+sve" }
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6 changes: 3 additions & 3 deletions clang/test/Sema/attr-target-clones-aarch64.c
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Expand Up @@ -24,17 +24,17 @@ int __attribute__((target_clones("rng", "fp16fml+fp", "default"))) redecl4(void)
// expected-error@+3 {{'target_clones' attribute does not match previous declaration}}
// expected-note@-2 {{previous declaration is here}}
// expected-warning@+1 {{version list contains entries that don't impact code generation}}
int __attribute__((target_clones("dgh+memtag+rpres", "ebf16+dpb+sha1", "default"))) redecl4(void) { return 1; }
int __attribute__((target_clones("dgh+memtag+rpres", "ebf16+dpb", "default"))) redecl4(void) { return 1; }

int __attribute__((target_version("flagm2"))) redef2(void) { return 1; }
// expected-error@+2 {{multiversioned function redeclarations require identical target attributes}}
// expected-note@-2 {{previous declaration is here}}
int __attribute__((target_clones("flagm2", "default"))) redef2(void) { return 1; }

int __attribute__((target_clones("f32mm", "f64mm", "sha1+fp"))) redef3(void) { return 1; }
int __attribute__((target_clones("f32mm", "f64mm", "sha2+fp"))) redef3(void) { return 1; }
// expected-error@+2 {{'target_clones' attribute does not match previous declaration}}
// expected-note@-2 {{previous declaration is here}}
int __attribute__((target_clones("f32mm", "sha1+fp", "f64mm"))) redef3(void) { return 1; }
int __attribute__((target_clones("f32mm", "sha2+fp", "f64mm"))) redef3(void) { return 1; }

int __attribute__((target_clones("rdm+lse+rdm", "lse+rdm"))) dup1(void) { return 1; }
// expected-warning@+1 {{version list contains duplicate entries}}
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4 changes: 2 additions & 2 deletions clang/test/Sema/attr-target-version.c
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Expand Up @@ -36,7 +36,7 @@ void __attribute__((target_version("bti+flagm2"))) one(void) {}
//expected-error@+1 {{multiversioned function redeclarations require identical target attributes}}
void __attribute__((target_version("flagm2+bti"))) one(void) {}

void __attribute__((target_version("ssbs+sha1"))) two(void) {}
void __attribute__((target_version("ssbs+sha2"))) two(void) {}
void __attribute__((target_version("ssbs+fp16fml"))) two(void) {}

//expected-error@+1 {{'main' cannot be a multiversioned function}}
Expand Down Expand Up @@ -89,7 +89,7 @@ int bar() {
return def();
}
// expected-error@+1 {{function declaration cannot become a multiversioned function after first usage}}
int __attribute__((target_version("sha1"))) def(void) { return 1; }
int __attribute__((target_version("sha2"))) def(void) { return 1; }

int __attribute__((target_version("sve"))) prot();
// expected-error@-1 {{multiversioned function must have a prototype}}
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2 changes: 1 addition & 1 deletion compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc
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Expand Up @@ -33,7 +33,7 @@ enum CPUFeatures {
FEAT_FP,
FEAT_SIMD,
FEAT_CRC,
FEAT_SHA1,
RESERVED_FEAT_SHA1, // previously used and now ABI legacy
FEAT_SHA2,
FEAT_SHA3,
FEAT_AES,
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2 changes: 0 additions & 2 deletions compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc
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Expand Up @@ -35,8 +35,6 @@ static void __init_cpu_features_constructor(unsigned long hwcap,
setCPUFeature(FEAT_RDM);
if (hwcap & HWCAP_AES)
setCPUFeature(FEAT_AES);
if (hwcap & HWCAP_SHA1)
setCPUFeature(FEAT_SHA1);
if (hwcap & HWCAP_SHA2)
setCPUFeature(FEAT_SHA2);
if (hwcap & HWCAP_JSCVT)
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2 changes: 1 addition & 1 deletion llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc
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Expand Up @@ -33,7 +33,7 @@ enum CPUFeatures {
FEAT_FP,
FEAT_SIMD,
FEAT_CRC,
FEAT_SHA1,
RESERVED_FEAT_SHA1, // previously used and now ABI legacy
FEAT_SHA2,
FEAT_SHA3,
FEAT_AES,
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1 change: 0 additions & 1 deletion llvm/lib/Target/AArch64/AArch64FMV.td
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Expand Up @@ -73,7 +73,6 @@ def : FMVExtension<"rdm", "FEAT_RDM", "+rdm,+fp-armv8,+neon", 108>;
def : FMVExtension<"rng", "FEAT_RNG", "+rand", 10>;
def : FMVExtension<"rpres", "FEAT_RPRES", "", 300>;
def : FMVExtension<"sb", "FEAT_SB", "+sb", 470>;
def : FMVExtension<"sha1", "FEAT_SHA1", "+fp-armv8,+neon", 120>;
def : FMVExtension<"sha2", "FEAT_SHA2", "+sha2,+fp-armv8,+neon", 130>;
def : FMVExtension<"sha3", "FEAT_SHA3", "+sha3,+sha2,+fp-armv8,+neon", 140>;
def : FMVExtension<"simd", "FEAT_SIMD", "+fp-armv8,+neon", 100>;
Expand Down
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