Adding CLIC (Core-Local Interrupt Controller) support to VexRiscv SMP CPU for LiteX SoC #2
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This PR is implementation of CLIC support for the VexRiscv SMP CPU core for LiteX SOC. CLIC provides advanced interrupt handling capabilities with up to 4096 interrupts and 8-bit priority levels.
It is based on below Pull-Requests:
Adding CLIC (Core-Local Interrupt Controller) support to VexRiscv SMP CPU for LiteX SoC linux-on-litex-vexriscv#438
Adding CLIC (Core-Local Interrupt Controller) support to VexRiscv SMP CPU for LiteX SoC pythondata-cpu-vexriscv_smp#10
Add RISC-V CLIC and CLINT interrupt controller support enjoy-digital/litex#2260