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1. divide-by-3-clock-divider divide-by-3-clock-divider Public

   SystemVerilog divide-by-3 clock divider with 50% duty cycle using dual counter architecture

   SystemVerilog

2. 8bit-full-adder 8bit-full-adder Public

   Implementation of 8-bit Full Adder using 1-bit Full Adders in Verilog

   Verilog

3. oop-aquarium oop-aquarium Public

   Interactive object-oriented aquarium simulator featuring fish and crabs with customizable behavior.

   Python

4. convolutional-codes convolutional-codes Public

   Simulates convolutional codes and Viterbi decoding with visualization support

   Python 1

5. Assembly-ADC-DAC Assembly-ADC-DAC Public

   MSP430 Assembly implementation of ADC sampling, voltage analysis, and PWM generation for Introduction to Computers Lab 6

   Assembly

6. hangman-game hangman-game Public

   Hangman game based on 'Pygame' module.

   Python