This project is being developed in the context of the Course Final Project as part of the Electronics, Telecommunications and Computer Engineering BSc at ISEL - Lisbon School of Engineering during the Summer Semester of 2024/25. The objective is to design and analyze a two-stage CMOS operational amplifier (OpAmp) using the gm/Id methodology, focusing on optimizing power efficiency while meeting performance specifications.
Operational amplifiers are a fundamental building block in analog circuit design, widely used in signal processing, sensor interfaces, and communication systems. The gm/Id methodology is a systematic approach that enables designers to size transistors efficiently, balancing gain, bandwidth, and power consumption.
The process techonology used for this project is: AMS 0.35ΞΌm CMOS C35
- President: to decide
- Examiner: to decide
- Supervisor: Vitor Costa
- Design a two-stage CMOS OpAmp with specific gain, bandwidth, and phase margin requirements.
- Apply the gm/Id methodology to optimize transistor sizing and power efficiency.
- Simulate the design using SPICE (LTspice, Cadence, or HSPICE) and compare results with theoretical calculations.
- Analyze key performance parameters, including DC bias, AC response, transient behavior, and noise characteristics.
- Circuit Simulation: Cadence Virtuoso, LTspice, or HSPICE
- Data Analysis & Scripting: MATLAB
- Report & Documentation: GitHub and Office
This project is based on various textbooks and research papers on CMOS OpAmp design.
For a complete list of references, visit the Bibliography section.
π Books β See full list
π Research Papers β General Papers | IEEE Papers
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