This is pt 2.
We highly encourage you to ask questions as they come up in the team Discord. It's likely that other people have the same problem(s). Plus, it's a first chance for us to work together. You can also go to the tiny tapeout website, which has lots of FAQs under FAQ.
This is by no means mandatory. If you really wanted to, you can see what bugs I added through the commit history. That isn't the point, rather it is a chance for you to get acquainted with some of the tools we will be using.
⭐ Please DO NOT make your edits directly to this repository, or try to commit them / make a PR. Rather, fork it and play around with your repo as much as you want.
Ignore the other branches, just worry about main. 😃
Feel free to reach out to me (Gerry) if there are any issues / confusion / suggestions for improvement with the repo, or anyone from the UW ASIC team.
v1.0 - Just starting out!
Gerry Chen ([email protected], [email protected])
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If Actions are not enabled for this repo, follow the same step(s) you followed in pt 1 to enable.
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Observe the failing workflow runs (most recent ones, or make a random commit yourself and use those runs).
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Check the top verilog file, control_block.v, alu.v for errors. Many are Verilog syntax errors. Some are more involved than that.
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You may also want to check out info.yaml. Is everything correct?
5 (super optional). I want my info.md under docs to be more interesting, not as boring as it is now (Sorry Damir!). Add some pictures maybe (whatever you want).
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go under /test. Look over tb.v. This is the verilog testbench (instantiation of the top module) that cocotb uses to test.
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Check test.py. There are comments in the script that describe how cocotb works. Write a super simple assert - there aren't really any syntax errors. Read through to get an idea of how cocotb works.
Done! (for now) - hope this got you excited instead of wanting to quit. Feel free to let me know any changes that should be made / improvements.