Commits to upstream: 2025-07-23 #7
Open
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
…PR117423) Testcase of PR 117423 shows a flaw in the fancy way we do "total scalarization" in SRA now. We use the types encountered in the function body and not in type declaration (allowing us to totally scalarize when only one union field is ever used, since we effectively "skip" the union then) and can accommodate pre-existing accesses that happen to fall into padding. In this case, we skipped the union (bypassing the totally_scalarizable_type_p check) and the access falling into the "padding" is an aggregate and so not a candidate for SRA but actually containing data. Arguably total scalarization should just bail out when it encounters this situation (but I decided not to depend on this mainly because we'd need to detect all cases when we eventually cannot scalarize, such as when a scalar access has children accesses) but the actual bug is that the detection if all data in an aggregate is indeed covered by replacements just assumes that is always the case if total scalarization triggers which however may not be the case in cases like this - and perhaps more. This patch fixes the bug by just assuming that all padding is taken care of when total scalarization triggered, not that every access was actually scalarized. gcc/ChangeLog: 2025-07-17 Martin Jambor <[email protected]> PR tree-optimization/117423 * tree-sra.cc (analyze_access_subtree): Fix computation of grp_covered flag. gcc/testsuite/ChangeLog: 2025-07-17 Martin Jambor <[email protected]> PR tree-optimization/117423 * gcc.dg/tree-ssa/pr117423.c: New test.
There's a new compiler warning breaking the build. This fixes it. The variable appears to be genuinely vestigial. libgomp/ChangeLog: PR target/121156 * config/gcn/bar.c (gomp_team_barrier_wait_end): Remove unused "generation" variable. (gomp_team_barrier_wait_cancel_end): Likewise.
…[PR121154] Previously for localized output, if _M_debug option was set, the _M_check_ok completed succesfully and _M_locale_fmt was called for months/weekdays that are !ok(). This patch lifts debug checks from each conversion function into _M_check_ok, that in case of !ok() values return a string_view containing the kind of calendar data, to be included after "is not a valid" string. The localized output (_M_locale_fmt) is not used if string is non-empty. Emitting of this message is now handled in _M_format_to, further reducing each specifier function. To handle weekday (%a,%A) and month (%b,%B), _M_check_ok now accepts a mutable reference to conversion specifier, and updates it to corresponding numeric value (%w, %m). Extra care needs to be taken to handle a month(0) that needs to be printed as single digit in debug format. Finally, the _M_time_point is replaced with _M_needs_ok_check member, that indicates if input contains any user-suplied values that are checked for being ok() and these values are referenced in chrono-specs. PR libstdc++/121154 libstdc++-v3/ChangeLog: * include/bits/chrono_io.h (_ChronoSpec::_M_time_point): Remove. (_ChronoSpec::_M_needs_ok_check): Define (__formatter_chrono::_M_parse): Set _M_needs_ok_check. (__formatter_chrono::_M_check_ok): Check values also for debug mode, and return __string_view. (__formatter_chrono::_M_format_to): Handle results of _M_check_ok. (__formatter_chrono::_M_wi, __formatter_chrono::_M_a_A) (__formatter_chrono::_M_b_B, __formatter_chrono::_M_C_y_Y) (__formatter_chrono::_M_d_e, __formatter_chrono::_M_F): Removed handling of _M_debug. (__formatter_chrono::__M_m): Print zero unpadded in _M_debug mode. (__formatter_duration::_S_spec_for): Remove _M_time_point refernce. (__formatter_duration::_M_parse): Override _M_needs_ok_check. * testsuite/std/time/month/io.cc: Test for localized !ok() values. * testsuite/std/time/weekday/io.cc: Test for localized !ok() values.
PR libstdc++/119137 libstdc++-v3/ChangeLog: * include/std/inplace_vector (inplace_vector::operator=): Qualify call to std::addressof.
Like the avg3_floor pattern, the avg3_ceil has the similar issue that lack of the RVV DImode support. Thus, this patch would like to support the DImode by the standard name, with the iterator V_VLSI_D. The below test suites are passed for this patch series. * The rv64gcv fully regression test. gcc/ChangeLog: * config/riscv/autovec.md (avg<mode>3_ceil): Add new pattern of avg3_ceil for RVV DImode gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/avg_data.h: Adjust the test data. * gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c: New test. * gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i64-from-i128.c: New test. Signed-off-by: Pan Li <[email protected]>
libstdc++-v3/ChangeLog: * doc/xml/manual/build_hacking.xml: Document that windows_zones-map.h is a generated file. * doc/html/manual/appendix_porting.html: Regenerate.
…ting Paolo has not been active for some time. libstdc++-v3/ChangeLog: * doc/xml/manual/appendix_contributing.xml: Remove Paolo from list of maintainers to contact about contributing. * doc/html/manual/appendix_contributing.html: Regenerate.
…ets [PR121153] I missed this when I added the two testcase vect-reduc-cond-[12].c. These testcases require support of vectorization of `a ? b : c` which some targets (e.g. sparc) does not support. Pushed as obvious after a quick test. PR testsuite/121153 gcc/testsuite/ChangeLog: * gcc.dg/vect/vect-reduc-cond-1.c: Require vect_condition. * gcc.dg/vect/vect-reduc-cond-2.c: Likewise. Signed-off-by: Andrew Pinski <[email protected]>
…121145] PR fortran/121145 gcc/fortran/ChangeLog: * trans-expr.cc (gfc_conv_procedure_call): Do not create pointer check for proc-pointer actual passed to optional dummy. gcc/testsuite/ChangeLog: * gfortran.dg/pointer_check_15.f90: New test.
This patch fixes the 2nd parameter name mismatch in ARRAYOFCHAR.mod. gcc/m2/ChangeLog: PR modula2/121164 * gm2-libs/ARRAYOFCHAR.mod (Write): Rename 2nd parameter name a to str. Signed-off-by: Gaius Mulley <[email protected]>
Currently this new concept will get defined for -std=c++17 -fconcepts but as it uses std::input_iterator, which is new in C++20, that won't work. Guard it with __cpp_lib_concepts as well as __cpp_concepts. libstdc++-v3/ChangeLog: * include/bits/stl_iterator_base_types.h (__any_input_iterator): Only define when __cpp_lib_concepts is defined.
gcc/ * config/avr/avr-passes.cc (avr_optimize_casesi): Fuse get_insns() with end_sequence().
…ir_p ()
> A number of folks have had their fingers in this code and it's going to take
> a few submissions to do everything we want to do.
>
> This patch is primarily concerned with avoiding signaling that fusion can
> occur in cases where it obviously should not be signaling fusion.
Hi Jeff,
With this change, we're liable to ICE whenever prev_set or curr_set are
NULL_RTX. For a fix, how about something like the below?
Thanks,
Artemiy
Introduced in r16-1984-g83d19b5d842dad, initializers for
{prev,curr}_dest_regno can cause an ICE if the respective insn isn't a
single set. Rectify this by inserting a NULL_RTX check before using
{prev,curr}_set.
Regtested on riscv32.
gcc/
* config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Protect
from a NULL PREV_SET or CURR_SET.
…umulate [PR119100] This pattern enables the combine pass (or late-combine, depending on the case) to merge a float_extend'ed vec_duplicate into a (possibly negated) minus-mult RTL instruction. Before this patch, we have six instructions, e.g.: vsetivli zero,4,e32,m1,ta,ma fcvt.s.h fa5,fa5 vfmv.v.f v4,fa5 vfwcvt.f.f.v v1,v3 vsetvli zero,zero,e32,m1,ta,ma vfnmadd.vv v1,v4,v2 After, we get only one: vfwnmacc.vf v1,fa5,v2 PR target/119100 gcc/ChangeLog: * config/riscv/autovec-opt.md (*vfwnmacc_vf_<mode>): New pattern. (*vfwnmsac_vf_<mode>): New pattern. * config/riscv/riscv.cc (get_vector_binary_rtx_cost): Add support for a vec_duplicate in a neg. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfwnmacc and vfwnmsac. * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f32.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f32.c: New test.
The ctable base address for SBCO/LBCO load/store patterns was incorrectly stored as unsigned integer. That prevented matching addresses with bit 31 set, because const_int RTL expression is expected to be sign-extended. Fix by using sign-extended 32-bit values for ctable base addresses. PR target/121124 gcc/ChangeLog: * config/pru/pru-pragma.cc (pru_pragma_ctable_entry): Handle the ctable base address as signed 32-bit value, and sign-extend to HOST_WIDE_INT. * config/pru/pru-protos.h (struct pru_ctable_entry): Store the ctable base address as signed. (pru_get_ctable_exact_base_index): Pass base address as signed. (pru_get_ctable_base_index): Ditto. (pru_get_ctable_base_offset): Ditto. * config/pru/pru.cc (pru_get_ctable_exact_base_index): Ditto. (pru_get_ctable_base_index): Ditto. (pru_get_ctable_base_offset): Ditto. (pru_print_operand_address): Ditto. gcc/testsuite/ChangeLog: * gcc.target/pru/pragma-ctable_entry-2.c: New test.
According to the semantics of the avg_floor and avg_ceil as below: floor: op0 = (narrow) (((wide) op1 + (wide) op2) >> 1); ceil: op0 = (narrow) (((wide) op1 + (wide) op2 + 1) >> 1); Aka we have (const_int 1) as the op2 of the ashiftrt but seems missed. Thus, add it back to align the definition. The below test suites are passed for this patch. * The rv64gcv fully regression test. gcc/ChangeLog: * config/riscv/autovec.md: Add (const_int 1) as the op2 of ashiftrt. Signed-off-by: Pan Li <[email protected]>
The previous test case doesn't leverage the right test helper macro, it should be DEF_AVG_0_WRAP instead of DEF_AVG_0. We prefer the test function name is test_avg_floor_int64_t_int32_t_0 instead of test_avg_floor_WT_NT_0 for DEF_AVG_0(WT, NT). The below test suites are passed for this patch. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i32.c: Leverage DEF_AVG_0_WRAP to generate the correct func name. * gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/avg_floor-1-i32-from-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c: Ditto. * gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c: Ditto. Signed-off-by: Pan Li <[email protected]>
The problem here is that the testcase is part of another testcase but dg-final does not work across source files so it needs its own dg-* headers to that match up with afdo-crossmodule-1.c. Pushed as preapproved in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120859#c4 . PR testsuite/120859 gcc/testsuite/ChangeLog: * gcc.dg/tree-prof/afdo-crossmodule-1b.c: Add some dg-* commands like what is in afdo-crossmodule-1.c Signed-off-by: Andrew Pinski <[email protected]>
r16-442 implemented both std::extents and std::dextents (and perhaps other stuff), but exported only std::extents. I went through https://eel.is/c++draft/mdspan.syn and I think std::dextents is the only one implemented but not exported. The following patch exports it, and additionally appends some further entities to the FIXME list, those all seems to be unimplemented yet. 2025-07-20 Jakub Jelinek <[email protected]> PR libstdc++/121174 * src/c++23/std.cc.in (std::dextents): Export. Add to FIXME comments other not yet implemented nor exported <mdspan> entities.
…atexit' [PR119853, PR119854] Fix-up for commit aafe942 "GCN, nvptx offloading: Host/device compatibility: Itanium C++ ABI, DSO Object Destruction API [PR119853, PR119854]": we need to adjust for 'targetm.cxx.use_aeabi_atexit': gcc/config/arm/arm.cc:#define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit gcc/config/arm/arm.cc:/* The EABI says __aeabi_atexit should be used to register static gcc/config/arm/arm.cc- destructors. */ gcc/config/arm/arm.cc- gcc/config/arm/arm.cc-static bool gcc/config/arm/arm.cc:arm_cxx_use_aeabi_atexit (void) gcc/config/arm/arm.cc-{ gcc/config/arm/arm.cc- return TARGET_AAPCS_BASED; gcc/config/arm/arm.cc-} ..., which 'gcc/cp/decl.cc:get_atexit_node' then acts on: call '__aeabi_atexit' instead of '__cxa_atexit', and swap two arguments. PR target/119853 PR target/119854 libgomp/ * testsuite/libgomp.c++/target-cdtor-1.C: Adjust for 'targetm.cxx.use_aeabi_atexit'. * testsuite/libgomp.c++/target-cdtor-2.C: Likewise.
This patch adds testcase for form8 and form9, as shown below:
T __attribute__((noinline)) \
sat_u_add_##T##_fmt_8(T x, T y) \
{ \
return x <= (T)(x + y) ? (x + y) : -1; \
}
T __attribute__((noinline)) \
sat_u_add_##T##_fmt_9(T x, T y) \
{ \
return x > (T)(x + y) ? -1 : (x + y); \
}
Passed the rv64gc regression test.
Signed-off-by: Ciyan Pan <[email protected]>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat/sat_arith.h: Unsigned testcase form8 form9.
* gcc.target/riscv/sat/sat_u_add-8-u16.c: New test.
* gcc.target/riscv/sat/sat_u_add-8-u32.c: New test.
* gcc.target/riscv/sat/sat_u_add-8-u64.c: New test.
* gcc.target/riscv/sat/sat_u_add-8-u8.c: New test.
* gcc.target/riscv/sat/sat_u_add-9-u16.c: New test.
* gcc.target/riscv/sat/sat_u_add-9-u32.c: New test.
* gcc.target/riscv/sat/sat_u_add-9-u64.c: New test.
* gcc.target/riscv/sat/sat_u_add-9-u8.c: New test.
* gcc.target/riscv/sat/sat_u_add-run-8-u16.c: New test.
* gcc.target/riscv/sat/sat_u_add-run-8-u32.c: New test.
* gcc.target/riscv/sat/sat_u_add-run-8-u64.c: New test.
* gcc.target/riscv/sat/sat_u_add-run-8-u8.c: New test.
* gcc.target/riscv/sat/sat_u_add-run-9-u16.c: New test.
* gcc.target/riscv/sat/sat_u_add-run-9-u32.c: New test.
* gcc.target/riscv/sat/sat_u_add-run-9-u64.c: New test.
* gcc.target/riscv/sat/sat_u_add-run-9-u8.c: New test.
Save subexpressions of array descriptor references to variables, so that all the expressions using the descriptor as base object benefit from a simplified reference using the variables. This limits the size of the expressions generated in the original tree dump, easing analysis of the code involving those expressions. This is especially helpful with chains of array references where each array in the chain uses a descriptor. After optimizations, the effect of the change shouldn't be visible in the vast majority of cases. In rare cases it seems to permit a couple more jump threadings. gcc/fortran/ChangeLog: * trans-array.cc (gfc_conv_ss_descriptor): Move the descriptor expression initialisation... (set_factored_descriptor_value): ... to this new function. Before initialisation, walk the reference expression passed as argument and save some of its subexpressions to a variable. (substitute_t): New struct. (maybe_substitute_expr): New function. (substitute_subexpr_in_expr): New function.
…106] PR fortran/119106 gcc/fortran/ChangeLog: * expr.cc (simplify_constructor): Do not simplify constants. (gfc_simplify_expr): Continue to simplify expression when an iterator is present. gcc/testsuite/ChangeLog: * gfortran.dg/array_constructor_58.f90: New test.
The following removes the minimum VF compute from dataref analysis which does not take into account SLP at all, leaving the testcase vectorized with V2SImode instead of V4SImode on x86. With SLP the only minimum VF we can compute this early is 1. * tree-vectorizer.h (vect_analyze_data_refs): Remove min_vf output. * tree-vect-data-refs.cc (vect_analyze_data_refs): Likewise. * tree-vect-loop.cc (vect_analyze_loop_2): Remove early out based on bogus min_vf. * tree-vect-slp.cc (vect_slp_analyze_bb_1): Adjust. * gcc.dg/vect/vect-127.c: New testcase.
Implement hard register constraints of the form {regname} where regname
must be a valid register name for the target. Such constraints may be
used in asm statements as a replacement for register asm and in machine
descriptions. A more verbose description is given in extend.texi.
It is expected and desired that optimizations coalesce multiple pseudos
into one whenever possible. However, in case of hard register
constraints we may have to undo this and introduce copies since
otherwise we would constraint a single pseudo to multiple hard
registers. This is done prior RA during asmcons in
match_asm_constraints_2(). While IRA tries to reduce live ranges, it
also replaces some register-register moves. That in turn might undo
those copies of a pseudo which we just introduced during asmcons. Thus,
check in decrease_live_ranges_number() via
valid_replacement_for_asm_input_p() whether it is valid to perform a
replacement.
The reminder of the patch mostly deals with parsing and decoding hard
register constraints. The actual work is done by LRA in
process_alt_operands() where a register filter, according to the
constraint, is installed.
For the sake of "reviewability" and in order to show the beauty of LRA,
error handling (which gets pretty involved) is spread out into a
subsequent patch.
Limitation
----------
Currently, a fixed register cannot be used as hard register constraint.
For example, loading the stack pointer on x86_64 via
void *
foo (void)
{
void *y;
__asm__ ("" : "={rsp}" (y));
return y;
}
leads to an error.
Asm Adjust Hook
---------------
The following targets implement TARGET_MD_ASM_ADJUST:
- aarch64
- arm
- avr
- cris
- i386
- mn10300
- nds32
- pdp11
- rs6000
- s390
- vax
Most of them only add the CC register to the list of clobbered register.
However, cris, i386, and s390 need some minor adjustment.
gcc/ChangeLog:
* config/cris/cris.cc (cris_md_asm_adjust): Deal with hard
register constraint.
* config/i386/i386.cc (map_egpr_constraints): Ditto.
* config/s390/s390.cc (f_constraint_p): Ditto.
* doc/extend.texi: Document hard register constraints.
* doc/md.texi: Ditto.
* function.cc (match_asm_constraints_2): Have a unique pseudo
for each operand with a hard register constraint.
(pass_match_asm_constraints::execute): Calling into new helper
match_asm_constraints_2().
* genoutput.cc (mdep_constraint_len): Return the length of a
hard register constraint.
* genpreds.cc (write_insn_constraint_len): Support hard register
constraints for insn_constraint_len().
* ira.cc (valid_replacement_for_asm_input_p_1): New helper.
(valid_replacement_for_asm_input_p): New helper.
(decrease_live_ranges_number): Similar to
match_asm_constraints_2() ensure that each operand has a unique
pseudo if constrained by a hard register.
* lra-constraints.cc (process_alt_operands): Install hard
register filter according to constraint.
* recog.cc (asm_operand_ok): Accept register type for hard
register constrained asm operands.
(constrain_operands): Validate hard register constraints.
* stmt.cc (decode_hard_reg_constraint): Parse a hard register
constraint into the corresponding register number or bail out.
(parse_output_constraint): Parse hard register constraint and
set *ALLOWS_REG.
(parse_input_constraint): Ditto.
* stmt.h (decode_hard_reg_constraint): Declaration of new
function.
gcc/testsuite/ChangeLog:
* gcc.dg/asm-hard-reg-1.c: New test.
* gcc.dg/asm-hard-reg-2.c: New test.
* gcc.dg/asm-hard-reg-3.c: New test.
* gcc.dg/asm-hard-reg-4.c: New test.
* gcc.dg/asm-hard-reg-5.c: New test.
* gcc.dg/asm-hard-reg-6.c: New test.
* gcc.dg/asm-hard-reg-7.c: New test.
* gcc.dg/asm-hard-reg-8.c: New test.
* gcc.target/aarch64/asm-hard-reg-1.c: New test.
* gcc.target/i386/asm-hard-reg-1.c: New test.
* gcc.target/i386/asm-hard-reg-2.c: New test.
* gcc.target/s390/asm-hard-reg-1.c: New test.
* gcc.target/s390/asm-hard-reg-2.c: New test.
* gcc.target/s390/asm-hard-reg-3.c: New test.
* gcc.target/s390/asm-hard-reg-4.c: New test.
* gcc.target/s390/asm-hard-reg-5.c: New test.
* gcc.target/s390/asm-hard-reg-6.c: New test.
* gcc.target/s390/asm-hard-reg-longdouble.h: New test.
This implements error handling for hard register constraints including
potential conflicts with register asm operands.
In contrast to register asm operands, hard register constraints allow
more than just one register per operand. Even more than just one
register per alternative. For example, a valid constraint for an
operand is "{r0}{r1}m,{r2}". However, this also means that we have to
make sure that each register is used at most once in each alternative
over all outputs and likewise over all inputs. For asm statements this
is done by this patch during gimplification. For hard register
constraints used in machine description, error handling is still a todo
and I haven't investigated this so far and consider this rather a low
priority.
gcc/ada/ChangeLog:
* gcc-interface/trans.cc (gnat_to_gnu): Pass null pointer to
parse_{input,output}_constraint().
gcc/analyzer/ChangeLog:
* region-model-asm.cc (region_model::on_asm_stmt): Pass null
pointer to parse_{input,output}_constraint().
gcc/c/ChangeLog:
* c-typeck.cc (build_asm_expr): Pass null pointer to
parse_{input,output}_constraint().
gcc/ChangeLog:
* cfgexpand.cc (n_occurrences): Move this ...
(check_operand_nalternatives): and this ...
(expand_asm_stmt): and the call to gimplify.cc.
* config/s390/s390.cc (s390_md_asm_adjust): Pass null pointer to
parse_{input,output}_constraint().
* gimple-walk.cc (walk_gimple_asm): Pass null pointer to
parse_{input,output}_constraint().
(walk_stmt_load_store_addr_ops): Ditto.
* gimplify-me.cc (gimple_regimplify_operands): Ditto.
* gimplify.cc (num_occurrences): Moved from cfgexpand.cc.
(num_alternatives): Ditto.
(gimplify_asm_expr): Deal with hard register constraints.
* stmt.cc (eliminable_regno_p): New helper.
(hardreg_ok_p): Perform a similar check as done in
make_decl_rtl().
(parse_output_constraint): Add parameter for gimplify_reg_info
and validate hard register constrained operands.
(parse_input_constraint): Ditto.
* stmt.h (class gimplify_reg_info): Forward declaration.
(parse_output_constraint): Add parameter.
(parse_input_constraint): Ditto.
* tree-ssa-operands.cc
(operands_scanner::get_asm_stmt_operands): Pass null pointer
to parse_{input,output}_constraint().
* tree-ssa-structalias.cc (find_func_aliases): Pass null pointer
to parse_{input,output}_constraint().
* varasm.cc (assemble_asm): Pass null pointer to
parse_{input,output}_constraint().
* gimplify_reg_info.h: New file.
gcc/cp/ChangeLog:
* semantics.cc (finish_asm_stmt): Pass null pointer to
parse_{input,output}_constraint().
gcc/d/ChangeLog:
* toir.cc: Pass null pointer to
parse_{input,output}_constraint().
gcc/testsuite/ChangeLog:
* gcc.dg/pr87600-2.c: Split test into two files since errors for
functions test{0,1} are thrown during expand, and for
test{2,3} during gimplification.
* lib/scanasm.exp: On s390, skip lines beginning with #.
* gcc.dg/asm-hard-reg-error-1.c: New test.
* gcc.dg/asm-hard-reg-error-2.c: New test.
* gcc.dg/asm-hard-reg-error-3.c: New test.
* gcc.dg/asm-hard-reg-error-4.c: New test.
* gcc.dg/asm-hard-reg-error-5.c: New test.
* gcc.dg/pr87600-3.c: New test.
* gcc.target/aarch64/asm-hard-reg-2.c: New test.
* gcc.target/s390/asm-hard-reg-7.c: New test.
Since genoutput has no information about hard register names we cannot statically verify those names in constraints of the machine description. Therefore, we have to do it at runtime. Although verification shouldn't be too expensive, restrict it to checking builds. This should be sufficient since hard register constraints in machine descriptions probably change rarely, and each commit should be tested with checking anyway, or at the very least before a release is taken. gcc/ChangeLog: * genoutput.cc (main): Emit function verify_reg_names_in_constraints() for run-time validation. (mdep_constraint_len): Deal with hard register constraints. * output.h (verify_reg_names_in_constraints): New function declaration. * toplev.cc (backend_init): If checking is enabled, call into verify_reg_names_in_constraints().
This commit implements basic type checking support for SlicePattern, based on rustc's check_pat_slice function. gcc/rust/ChangeLog: * typecheck/rust-hir-type-check-pattern.cc (TypeCheckPattern::visit(SlicePattern)): Implement initial type checking for SlicePattern. Signed-off-by: Yap Zhi Heng <[email protected]>
This change is made to ensure that LiteralPatterns in SlicePattern are type-checked against the scrutinee array/slice's element type properly. gcc/rust/ChangeLog: * typecheck/rust-hir-type-check-pattern.cc(TypeCheckPattern::visit(LiteralPattern)): Check LiteralPattern's type against its parent. Signed-off-by: Yap Zhi Heng <[email protected]>
Fix narrowing:
-../../gcc/rust/checks/errors/borrowck/rust-borrow-checker-diagnostics.cc:145:46:
warning: narrowing conversion of ‘loan’ from ‘Rust::Polonius::Loan’ {aka
‘long unsigned int’} to ‘uint32_t’ {aka ‘unsigned int’} [-Wnarrowing]
gcc/rust/ChangeLog:
* checks/errors/borrowck/rust-bir-place.h (LoanId::value): Make
it size_t to match Loan's base type.
Signed-off-by: Marc Poulhiès <[email protected]>
This was a nasty issue to debug, the issue was very eager type bounds checking. So for example: pub trait PartialOrd<Rhs: ?Sized = Self>: PartialEq<Rhs> The super trait of PartialEq<Rhs> is a generic substitution and we reuse our bounds code here for normal generic bounds and generics an invalid bounds check was occuring when PartialEq<Rhs> was getting substituted becase this is a trait doing proper bounds checking is not valid here because this is telling us about the bounds in this case. Fixes Rust-GCC#3836 gcc/rust/ChangeLog: * typecheck/rust-hir-trait-resolve.cc (TraitResolver::resolve_trait): track is super trait * typecheck/rust-hir-type-bounds.h: refactor bounds scan * typecheck/rust-hir-type-check-base.h: track from super trait * typecheck/rust-hir-type-check-expr.cc (TypeCheckExpr::visit): likewise * typecheck/rust-tyty-bounds.cc (TypeBoundsProbe::is_bound_satisfied_for_type): refactor (TypeBoundsProbe::scan): likewise (TypeBoundPredicate::apply_generic_arguments): likewise * typecheck/rust-tyty-subst.cc: optional bounds checking on parm subst * typecheck/rust-tyty-subst.h: likewise * typecheck/rust-tyty.h: likewise gcc/testsuite/ChangeLog: * rust/compile/derive_partial_ord1.rs: this is now fully supported * rust/execute/torture/basic_partial_ord1.rs: add missing i32 impl * rust/execute/torture/basic_partial_ord2.rs: likewise * rust/compile/issue-3836.rs: New test. * rust/execute/torture/issue-3836.rs: New test. * rust/execute/torture/partial-ord-6.rs: New test. Signed-off-by: Philip Herron <[email protected]>
gcc/rust/ChangeLog: * resolve/rust-late-name-resolver-2.0.cc (Late::visit): Check for a label before visiting it.
…rcions
This case:
let i = 1;
let j = i as i64;
'i' is meant to default to i32 but the inference was making both of these
i64 because the code was prefering coercion logic which can end up with a
default unify which causes the ?integer to unify with i64 making them both
i64.
But all we need to do is allow the simple cast rules to run first then
fallback to coercions but special consideration has to be made to ensure
that if there are dyn objects needed then this needs a unsize coercion, but
also we need to ensure the underlying types are a valid simple cast too
otherwise these also need to fallback to the coercion code.
Fixes Rust-GCC#2680
gcc/rust/ChangeLog:
* typecheck/rust-casts.cc (TypeCastRules::resolve): optional emit_error flag
(TypeCastRules::check): try the simple cast rules then fallback to coercions
(TypeCastRules::check_ptr_ptr_cast): ensure the underlying's
(TypeCastRules::emit_cast_error): make this a static helper
* typecheck/rust-casts.h: new emit_error prototype
gcc/testsuite/ChangeLog:
* rust/compile/issue-2680.rs: New test.
Signed-off-by: Philip Herron <[email protected]>
We just had a typo returning ok true when it should have been false. Fixes Rust-GCC#3876 gcc/rust/ChangeLog: * typecheck/rust-hir-type-check-struct.cc (TypeCheckStructExpr::visit): fix typo gcc/testsuite/ChangeLog: * rust/compile/issue-3876.rs: New test. Signed-off-by: Philip Herron <[email protected]>
Fixes Rust-GCC#3599 gcc/testsuite/ChangeLog: * rust/compile/issue-3599.rs: New test. Signed-off-by: Philip Herron <[email protected]>
Fixes Rust-GCC#3144 gcc/testsuite/ChangeLog: * rust/compile/issue-3144.rs: New test. Signed-off-by: Philip Herron <[email protected]>
Fixes Rust-GCC#1048 gcc/testsuite/ChangeLog: * rust/compile/issue-1048.rs: New test. Signed-off-by: Philip Herron <[email protected]>
gcc/rust/ChangeLog: * util/rust-attribute-values.h: Add declarations for them. * util/rust-attributes.cc: Add definitions.
We have more complex test cases already but this will close out this issue. Fixes Rust-GCC#2005 gcc/testsuite/ChangeLog: * rust/execute/torture/issue-2005.rs: New test. Signed-off-by: Philip Herron <[email protected]>
gcc/rust/ChangeLog: * typecheck/rust-hir-type-check-pattern.cc(TypeCheckPattern::visit(SlicePattern)): Implement size checking for SlicePattern when type checking against array parent Signed-off-by: Yap Zhi Heng <[email protected]>
…ype scrutinee
Example GIMPLE output from compiling testsuite/rust/compile/match-pattern-array.rs:
...
a[0] = 0;
a[1] = 1;
RUSTTMP.3 = a;
_1 = RUSTTMP.3[0];
_2 = _1 == 0;
_3 = RUSTTMP.3[1];
_4 = _3 == 1;
_5 = _2 & _4;
if (_5 != 0) goto <D.122>; else goto <D.123>;
<D.122>:
{
{
}
}
goto <D.117>;
}
<D.123>:
...
gcc/rust/ChangeLog:
* rust-backend.h: New size_constant_expression function.
* rust-gcc.cc: Implementation of size_constant_expression function to generate tree node
for array access.
* backend/rust-compile-pattern.h: Remove empty visits for SlicePattern.
* backend/rust-compile-pattern.cc: Implement SlicePattern check expression & binding
compilation against ArrayType scrutinee.
Signed-off-by: Yap Zhi Heng <[email protected]>
gcc/rust/ChangeLog: * backend/rust-compile-expr.cc (CompileExpr::visit): Add a catch for const/static. gcc/testsuite/ChangeLog: * rust/compile/loop_constant_context.rs: New test. * rust/compile/issue-3618.rs: Signed-off-by: lishin <[email protected]>
Fixes Rust-GCC#3524 gcc/testsuite/ChangeLog: * rust/compile/issue-3524.rs: New test. Signed-off-by: Philip Herron <[email protected]>
gcc/rust/ChangeLog: * parse/rust-parse-impl.h (Parser::parse_simple_path): Be more careful about skipping SCOPE_RESOLUTION tokens. (Parser::parse_simple_path_segment): Allow parsing from a starting offset. (Parser::parse_use_tree): Handle a non-skipped SCOPE_RESOLUTION token. * parse/rust-parse.h (Parser::parse_simple_path_segment): Add parameter for parsing from a starting offset. gcc/testsuite/ChangeLog: * rust/compile/parse_simple_path_fail_1.rs: New test. * rust/compile/parse_simple_path_fail_2.rs: New test. Signed-off-by: Owen Avery <[email protected]>
Rust seems to allow duplicate HIR::Item 'main' functions but it needs to be a root item to be the true main entry point. This means we can use the canonical path to determine if this is a root one where its CrateName::main or CrateName::Module::main. Fixes Rust-GCC#3978 gcc/rust/ChangeLog: * backend/rust-compile-base.cc: check the canonical path gcc/testsuite/ChangeLog: * rust/compile/issue-3978.rs: New test. Signed-off-by: Philip Herron <[email protected]>
In the test case:
fn test (len: usize) -> u64 {
let mut i = 0;
let mut out = 0;
if i + 3 < len {
out = 123;
}
out
}
The issue is to determine the correct type of 'i', out is simple because it hits a
coercion site in the resturn position for u64. But 'i + 3', 'i' is an integer infer
variable and the same for the literal '3'. So when it comes to resolving the type for
the Add expression we hit the resolve the operator overload code and because of this:
macro_rules! add_impl {
($($t:ty)*) => ($(
impl Add for $t {
type Output = $t;
#[inline]
#[rustc_inherit_overflow_checks]
fn add(self, other: $t) -> $t { self + other }
}
)*)
}
add_impl! { usize u8 u16 u32 u64 u128 isize i8 i16 i32 i64 i128 f32 f64 }
This means the resolution for 'i + 3' is ambigious because it could be any of these Add
implementations. But because we unify against the '< len' where len is defined as usize
later in the resolution we determine 'i' is actually a usize. Which means if we defer the
resolution of this operator overload in the ambigious case we can simply resolve it at the
end.
Fixes Rust-GCC#3916
gcc/rust/ChangeLog:
* hir/tree/rust-hir-expr.cc (OperatorExprMeta::OperatorExprMeta): track the rhs
* hir/tree/rust-hir-expr.h: likewise
* hir/tree/rust-hir-path.h: get rid of old comments
* typecheck/rust-hir-trait-reference.cc (TraitReference::get_trait_substs): return
references instead of copy
* typecheck/rust-hir-trait-reference.h: update header
* typecheck/rust-hir-type-check-expr.cc (TypeCheckExpr::ResolveOpOverload): write ambigious
operator overloads to a table and try to resolve it at the end
* typecheck/rust-hir-type-check-expr.h: new static helper
* typecheck/rust-hir-type-check.h (struct DeferredOpOverload): new model to defer resolution
* typecheck/rust-typecheck-context.cc (TypeCheckContext::lookup_operator_overload): new
(TypeCheckContext::compute_ambigious_op_overload): likewise
(TypeCheckContext::compute_inference_variables): likewise
gcc/testsuite/ChangeLog:
* rust/compile/issue-3916.rs: New test.
Signed-off-by: Philip Herron <[email protected]>
Not adding the test case here we emit more errors than rustc for the error type node so its just noisy and dejagnu is being a pain. Fixes Rust-GCC#3933 gcc/rust/ChangeLog: * backend/rust-compile-resolve-path.cc (ResolvePathRef::resolve): return error_mark_node Signed-off-by: Philip Herron <[email protected]>
This should make it easier for us to handle attribute meta items of the form <SimplePath> '=' <Expression> where the expression isn't a literal. Some low hanging fruit remains here, but I think I should keep this patch small as I had some trouble debugging it as-is (see: Rust::Token::as_string vs Rust::Token::get_str vs Rust::AST::Token::as_string). gcc/rust/ChangeLog: * ast/rust-ast.cc: Include "rust-macro-invoc-lexer.h". (AttributeParser::~AttributeParser): Move function definition here. (AttributeParser::AttributeParser): Likewise and adjust member initialization. (AttributeParser::parse_meta_item_inner): Handle changes to peek_token. (AttributeParser::parse_literal): Likewise. (AttributeParser::parse_simple_path_segment): Likewise. (AttributeParser::parse_meta_item_seq): Handle changes to AttributeParser fields. (AttributeParser::peek_token): Move function definition here and wrap MacroInvocLexer. (AttributeParser::skip_token): Likewise. * ast/rust-macro.h (class MacroInvocLexer): Forward declare. (class Parser): Likewise. (AttributeParser::token_stream): Remove field. (AttributeParser::stream_pos): Likewise. (AttributeParser::lexer): New field. (AttributeParser::parser): Likewise. (AttributeParser::AttributeParser): Move definition to "rust-ast.cc". (AttributeParser::~AttributeParser): Likewise. (AttributeParser::peek_token): Likewise. (AttributeParser::skip_token): Likewise. Signed-off-by: Owen Avery <[email protected]>
When we have generic paths like T::foobar during codegen sometimes we need to enforce an extra lookup for this generic parameter type to the mono morphized underlying type. Fixes Rust-GCC#3915 Fixes Rust-GCC#1247 gcc/rust/ChangeLog: * backend/rust-compile-resolve-path.cc (HIRCompileBase::query_compile): do another lookup gcc/testsuite/ChangeLog: * rust/compile/issue-3915.rs: New test. * rust/execute/torture/sip-hasher.rs: New test. Signed-off-by: Philip Herron <[email protected]>
gcc/rust/ChangeLog: * expand/rust-expand-visitor.cc (ExpandVisitor::expand_inner_items): Adjust call to expand_macro_children. (ExpandVisitor::expand_inner_stmts): Likewise. (ExpandVisitor::visit): Likewise. * expand/rust-expand-visitor.h (ExpandVisitor::expand_macro_children): Take a pointer to member function instead of a std::function. Signed-off-by: Owen Avery <[email protected]>
TopLevel would ignore just-loaded modules but Early and ExpandVisitor wouldn't. The latter would produce errors when it hit attributes which should have been indirectly CfgStrip'd away. gcc/rust/ChangeLog: * expand/rust-cfg-strip.cc (CfgStrip::visit): Load unloaded modules. * resolve/rust-toplevel-name-resolver-2.0.cc (TopLevel::visit): Assume modules have been loaded by CfgStrip. Signed-off-by: Owen Avery <[email protected]>
This is important for importing enum variants as items. gcc/rust/ChangeLog: * util/rust-hir-map.cc (Mappings::insert_ast_module): Rename to... (Mappings::insert_glob_container): ...this. (Mappings::lookup_ast_module): Rename to... (Mappings::lookup_glob_container): ...this. * util/rust-hir-map.h: Change declarations.
gcc/rust/ChangeLog: * resolve/rust-early-name-resolver-2.0.cc (Early::resolve_glob_import): Adapt for enums. (Early::finalize_glob_import): Likewise. * resolve/rust-early-name-resolver-2.0.h: Likewise. * resolve/rust-finalize-imports-2.0.cc (GlobbingVisitor::go): Likewise. (GlobbingVisitor::visit_module_container): New function. (GlobbingVisitor::visit_enum_container): New function. * resolve/rust-finalize-imports-2.0.h: Declare them. * resolve/rust-toplevel-name-resolver-2.0.cc (TopLevel::visit): Insert enums as potential containers. gcc/testsuite/ChangeLog: * rust/compile/glob_import_enum.rs: New test.
gcc/rust/ChangeLog: * ast/rust-expr.h: Add handling for deferred consts. * ast/rust-ast-visitor.cc (DefaultASTVisitor::visit): Likewise. * ast/rust-ast.cc (AnonConst::as_string): Likewise. (ArrayType::as_string): Likewise. * ast/rust-type.h (class ArrayType): Use AnonConst for sizes. * parse/rust-parse-impl.h (Parser::parse_anon_const): New function. (Parser::parse_slice_or_array_type): Call it. * parse/rust-parse.h: Declare it.
gcc/rust/ChangeLog: * hir/rust-ast-lower-expr.cc (ASTLoweringExpr::visit): Handle defered consts. * hir/tree/rust-hir-expr.cc (AnonConst::AnonConst): Likewise. (AnonConst::operator=): Likewise. * hir/tree/rust-hir-expr.h: Likewise. * hir/tree/rust-hir-visitor.cc (DefaultHIRVisitor::walk): Likewise. * typecheck/rust-hir-type-check-expr.cc (TypeCheckExpr::visit): Likewise. gcc/testsuite/ChangeLog: * rust/compile/deferred_const_inference.rs: New test.
gcc/rust/ChangeLog: * ast/rust-expr.h: Fix formatting.
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Hey there! I'm gerris 🦀