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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 [email protected]

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

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  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

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  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

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  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

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  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

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  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

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  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

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Repositories

Showing 10 of 111 repositories
  • caliptra-mcu-sw Public

    Caliptra MCU Software

    chipsalliance/caliptra-mcu-sw’s past year of commit activity
    Rust 13 Apache-2.0 3 15 1 Updated Apr 22, 2025
  • caliptra-ss Public

    HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

    chipsalliance/caliptra-ss’s past year of commit activity
    SystemVerilog 14 Apache-2.0 10 55 15 Updated Apr 22, 2025
  • Caliptra Public

    Caliptra IP and firmware for integrated Root of Trust block

    chipsalliance/Caliptra’s past year of commit activity
    281 Apache-2.0 40 43 11 Updated Apr 22, 2025
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 110 Apache-2.0 53 133 61 Updated Apr 22, 2025
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 4,244 Apache-2.0 623 330 (1 issue needs help) 158 Updated Apr 22, 2025
  • caliptra-dpe Public

    High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs

    chipsalliance/caliptra-dpe’s past year of commit activity
    Rust 17 Apache-2.0 24 11 8 Updated Apr 21, 2025
  • sv-tests Public

    Test suite designed to check compliance with the SystemVerilog standard.

    chipsalliance/sv-tests’s past year of commit activity
    SystemVerilog 313 ISC 79 48 (5 issues need help) 23 Updated Apr 21, 2025
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 264 Apache-2.0 34 20 41 Updated Apr 21, 2025
  • chisel-nix Public

    Nix template for the chisel-based industrial designing flows.

    chipsalliance/chisel-nix’s past year of commit activity
    Nix 41 5 0 1 Updated Apr 21, 2025
  • i3c-core Public
    chipsalliance/i3c-core’s past year of commit activity
    SystemVerilog 23 Apache-2.0 5 4 1 Updated Apr 21, 2025
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