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(MaquinaEstado)VGA_Tile_32x32_restored
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db
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incremental_db
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ComponenteDeControle.vhd
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DECODE.vhd
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DecoderFunct.vhd
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DecoderOpcode.vhd
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MEM_ACCESS.vhd
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MIPSExpo.qar
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MIPSExpo.qarlog
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MIPSExpo.qpf
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MIPSExpo.qsf
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MIPSExpo.restore.rpt
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MIPSExpo.vhd
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MIPSentregaFinal.vhd
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RAMMIPS.vhd
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README.md
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ROMMIPS.vhd
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ROMMIPS.vhd.bak
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ULAMIPS.vhd
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UnidadeDeControle.vhd
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WRITE_BACK.vhd
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assignment_defaults.qdf
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bancoReg.vhd
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buffer_3_state_mask.vhd
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c5_pin_model_dump.txt
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charMapROM_32x32_2K-RelogioDesComp.mif
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conversorHex7Seg.vhd
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estendeSinalGenerico.vhd
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somador1Bit.vhd
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somadorGenerico.vhd
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MIPS-based project presented at Insper Expo 2022

Presented by: Bernardo Cunha Capoferri

MIPS architechture programmers:

Bernardo Cunha Capoferri, Francisco Pinheiro Janela and Guilherme Dantas Rameh

Assembly Programmer:

Bernardo Cunha Capoferri

This is repository contains the VHDL code for a MIPS architecture with working pipeline, forwarding and stall, it was run on a DE0-CV board with a Cyclone V FPGA architecture. It is running a simple sprite animation loop coded in assembly language made possible by a VGA driver which was provided by the professor Paulo Carlos Santos teacher of the subject "Design de computadores" at Insper Instituto de Ensino e Pesquisa.

Video of the animation: https://youtube.com/shorts/Hg_RS33tgDw

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