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Sample projects

  • sample-00: Test turning on/off a LED in the DE0 Nano development kit

Project File Structure

project-name/ : Top level directory of the Quartus Prime project

  • bdf/ : Block diagram or schematic files (.bdf)
  • hdl/ : Verilog HDL files (.v)
    • generated/ : Verilog files generated by Quartus Prime from a block diagram or schematic file
  • simulation/ : Simulation waveform files for the Simulation Waveform Editor of Quartus Prime (.vwf)
  • symbols/ : Generated symbol files (.bsf)
  • tests/ : Verilog HDL testing or testbench files (.v)
  • waves/ : Waveforms for ModelSim Altera (.do)
  • project-name.bdf : Top level block diagram or schematic
  • project-name.qpf : Quartus Prime project file
  • project-name.qps : Quartus Prime settings file

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FPGA practice to get ready for TP5

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