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build(deps): bump third_party/cores/veer-el2 from 89b18ac to b5e2e9d #1014

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build(deps): bump third_party/cores/veer-el2 from 89b18ac to b5e2e9d #1014

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2 changes: 1 addition & 1 deletion third_party/cores/veer-el2
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Submodule veer-el2 updated 95 files
+0 −16 .github/assets/riscv_dv/README.md
+0 −3,941 .github/assets/riscv_dv/pyflow/test_riscv_arithmetic_basic_test/asm_test/riscv_arithmetic_basic_test_0.S
+0 −8,668 .github/assets/riscv_dv/pyflow/test_riscv_arithmetic_basic_test/asm_test/riscv_arithmetic_basic_test_1.S
+0 −5,555 .github/assets/riscv_dv/pyflow/test_riscv_arithmetic_basic_test/asm_test/riscv_arithmetic_basic_test_2.S
+0 −12,389 .github/assets/riscv_dv/uvm/test_riscv_arithmetic_basic_test/asm_test/riscv_arithmetic_basic_test_0.S
+0 −11,753 .github/assets/riscv_dv/uvm/test_riscv_arithmetic_basic_test/asm_test/riscv_arithmetic_basic_test_1.S
+0 −11,748 .github/assets/riscv_dv/uvm/test_riscv_arithmetic_basic_test/asm_test/riscv_arithmetic_basic_test_2.S
+0 −20,700 .github/assets/riscv_dv/uvm/test_riscv_ebreak_debug_mode_test/asm_test/riscv_ebreak_debug_mode_test_0.S
+0 −19,585 .github/assets/riscv_dv/uvm/test_riscv_ebreak_debug_mode_test/asm_test/riscv_ebreak_debug_mode_test_1.S
+0 −19,721 .github/assets/riscv_dv/uvm/test_riscv_ebreak_debug_mode_test/asm_test/riscv_ebreak_debug_mode_test_2.S
+0 −20,700 .github/assets/riscv_dv/uvm/test_riscv_ebreak_test/asm_test/riscv_ebreak_test_0.S
+0 −19,585 .github/assets/riscv_dv/uvm/test_riscv_ebreak_test/asm_test/riscv_ebreak_test_1.S
+0 −19,721 .github/assets/riscv_dv/uvm/test_riscv_ebreak_test/asm_test/riscv_ebreak_test_2.S
+0 −20,701 .github/assets/riscv_dv/uvm/test_riscv_full_interrupt_test/asm_test/riscv_full_interrupt_test_0.S
+0 −19,585 .github/assets/riscv_dv/uvm/test_riscv_full_interrupt_test/asm_test/riscv_full_interrupt_test_1.S
+0 −19,720 .github/assets/riscv_dv/uvm/test_riscv_full_interrupt_test/asm_test/riscv_full_interrupt_test_2.S
+0 −20,748 .github/assets/riscv_dv/uvm/test_riscv_hint_instr_test/asm_test/riscv_hint_instr_test_0.S
+0 −19,632 .github/assets/riscv_dv/uvm/test_riscv_hint_instr_test/asm_test/riscv_hint_instr_test_1.S
+0 −19,767 .github/assets/riscv_dv/uvm/test_riscv_hint_instr_test/asm_test/riscv_hint_instr_test_2.S
+0 −20,748 .github/assets/riscv_dv/uvm/test_riscv_illegal_instr_test/asm_test/riscv_illegal_instr_test_0.S
+0 −19,632 .github/assets/riscv_dv/uvm/test_riscv_illegal_instr_test/asm_test/riscv_illegal_instr_test_1.S
+0 −19,767 .github/assets/riscv_dv/uvm/test_riscv_illegal_instr_test/asm_test/riscv_illegal_instr_test_2.S
+0 −10,576 .github/assets/riscv_dv/uvm/test_riscv_jump_stress_test/asm_test/riscv_jump_stress_test_0.S
+0 −9,847 .github/assets/riscv_dv/uvm/test_riscv_jump_stress_test/asm_test/riscv_jump_stress_test_1.S
+0 −9,881 .github/assets/riscv_dv/uvm/test_riscv_jump_stress_test/asm_test/riscv_jump_stress_test_2.S
+0 −17,556 .github/assets/riscv_dv/uvm/test_riscv_loop_test/asm_test/riscv_loop_test_0.S
+0 −16,850 .github/assets/riscv_dv/uvm/test_riscv_loop_test/asm_test/riscv_loop_test_1.S
+0 −16,658 .github/assets/riscv_dv/uvm/test_riscv_loop_test/asm_test/riscv_loop_test_2.S
+0 −22,706 .github/assets/riscv_dv/uvm/test_riscv_mmu_stress_test/asm_test/riscv_mmu_stress_test_0.S
+0 −22,094 .github/assets/riscv_dv/uvm/test_riscv_mmu_stress_test/asm_test/riscv_mmu_stress_test_1.S
+0 −22,140 .github/assets/riscv_dv/uvm/test_riscv_mmu_stress_test/asm_test/riscv_mmu_stress_test_2.S
+0 −20,699 .github/assets/riscv_dv/uvm/test_riscv_no_fence_test/asm_test/riscv_no_fence_test_0.S
+0 −19,583 .github/assets/riscv_dv/uvm/test_riscv_no_fence_test/asm_test/riscv_no_fence_test_1.S
+0 −19,720 .github/assets/riscv_dv/uvm/test_riscv_no_fence_test/asm_test/riscv_no_fence_test_2.S
+0 −20,425 .github/assets/riscv_dv/uvm/test_riscv_non_compressed_instr_test/asm_test/riscv_non_compressed_instr_test_0.S
+0 −19,670 .github/assets/riscv_dv/uvm/test_riscv_non_compressed_instr_test/asm_test/riscv_non_compressed_instr_test_1.S
+0 −19,630 .github/assets/riscv_dv/uvm/test_riscv_non_compressed_instr_test/asm_test/riscv_non_compressed_instr_test_2.S
+0 −24,902 ...cv_dv/uvm/test_riscv_pmp_disable_all_regions_test_veer/asm_test/riscv_pmp_disable_all_regions_test_veer_0.S
+0 −35,527 .github/assets/riscv_dv/uvm/test_riscv_pmp_full_random_test_veer/asm_test/riscv_pmp_full_random_test_veer_0.S
+0 −38,049 ...b/assets/riscv_dv/uvm/test_riscv_pmp_out_of_bounds_test_veer/asm_test/riscv_pmp_out_of_bounds_test_veer_0.S
+0 −24,619 .github/assets/riscv_dv/uvm/test_riscv_pmp_region_exec_test_veer/asm_test/riscv_pmp_region_exec_test_veer_0.S
+0 −20,701 .github/assets/riscv_dv/uvm/test_riscv_pmp_test/asm_test/riscv_pmp_test_0.S
+0 −19,585 .github/assets/riscv_dv/uvm/test_riscv_pmp_test/asm_test/riscv_pmp_test_1.S
+0 −19,720 .github/assets/riscv_dv/uvm/test_riscv_pmp_test/asm_test/riscv_pmp_test_2.S
+0 −20,701 .github/assets/riscv_dv/uvm/test_riscv_rand_instr_test/asm_test/riscv_rand_instr_test_0.S
+0 −19,705 .github/assets/riscv_dv/uvm/test_riscv_rand_instr_test/asm_test/riscv_rand_instr_test_1.S
+0 −19,791 .github/assets/riscv_dv/uvm/test_riscv_rand_instr_test/asm_test/riscv_rand_instr_test_2.S
+0 −16,792 .github/assets/riscv_dv/uvm/test_riscv_rand_jump_test/asm_test/riscv_rand_jump_test_0.S
+0 −16,308 .github/assets/riscv_dv/uvm/test_riscv_rand_jump_test/asm_test/riscv_rand_jump_test_1.S
+0 −16,058 .github/assets/riscv_dv/uvm/test_riscv_rand_jump_test/asm_test/riscv_rand_jump_test_2.S
+0 −17,745 .github/assets/riscv_dv/uvm/test_riscv_unaligned_load_store_test/asm_test/riscv_unaligned_load_store_test_0.S
+0 −17,163 .github/assets/riscv_dv/uvm/test_riscv_unaligned_load_store_test/asm_test/riscv_unaligned_load_store_test_1.S
+0 −17,117 .github/assets/riscv_dv/uvm/test_riscv_unaligned_load_store_test/asm_test/riscv_unaligned_load_store_test_2.S
+0 −14,438 .github/assets/riscv_dv/uvm/test_riscv_user_mode_rand_test/asm_test/riscv_user_mode_rand_test_0.S
+0 −13,849 .github/assets/riscv_dv/uvm/test_riscv_user_mode_rand_test/asm_test/riscv_user_mode_rand_test_1.S
+0 −13,913 .github/assets/riscv_dv/uvm/test_riscv_user_mode_rand_test/asm_test/riscv_user_mode_rand_test_2.S
+7 −0 .github/scripts/convert_dat.sh
+1 −1 .github/scripts/info_process_setup.sh
+4 −6 .github/scripts/prepare_coverage_data.sh
+27 −19 .github/scripts/riscv_dv_matrix_include.py
+1 −0 .github/scripts/secrets_version
+0 −45 .github/scripts/split_info.py
+9 −3 .github/workflows/custom-lint.yml
+0 −37 .github/workflows/gh-pages-pr-deploy.yml
+2 −1 .github/workflows/gh-pages-pr-remove.yml
+23 −21 .github/workflows/publish-webpage.yml
+16 −4 .github/workflows/report-coverage.yml
+12 −10 .github/workflows/test-openocd.yml
+10 −7 .github/workflows/test-regression-cache-waypack.yml
+6 −3 .github/workflows/test-regression-dcls.yml
+12 −9 .github/workflows/test-regression-exceptions.yml
+1 −1 .github/workflows/test-renode.yml
+4 −5 .github/workflows/test-riscof.yml
+82 −51 .github/workflows/test-riscv-dv.yml
+16 −5 .github/workflows/test-uarch.yml
+1 −1 .github/workflows/test-uvm.yml
+15 −12 .github/workflows/test-verification.yml
+5 −0 MAINTAINERS.md
+17 −8 design/dec/el2_dec_pmp_ctl.sv
+1 −2 design/el2_mem.sv
+2 −0 design/ifu/el2_ifu_bp_ctl.sv
+30 −17 design/ifu/el2_ifu_ic_mem.sv
+2 −1 design/lib/el2_mem_if.sv
+2 −3 testbench/axi4_mux/axi_crossbar_wrap_2x1.v
+12 −2 tools/prefix_macros.sh
+8 −13 tools/riscv-dv/Makefile
+2 −2 verification/block/dmi/test_dmi_tap_fsm.py
+18 −0 verification/block/ifu_mem_ctl/Makefile
+4 −0 verification/block/ifu_mem_ctl/cm.cfg
+149 −0 verification/block/ifu_mem_ctl/common.py
+185 −0 verification/block/ifu_mem_ctl/el2_ifu_mem_ctl_wrapper.sv
+165 −0 verification/block/ifu_mem_ctl/test_err.py
+114 −0 verification/block/ifu_mem_ctl/test_err_stop.py
+201 −0 verification/block/ifu_mem_ctl/test_miss.py
+14 −7 verification/block/noxfile.py
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