I3C core FPGA test design

Copyright (c) 2025 Antmicro

This design targets US+ device and instantiates the I3C core in a way it is connected to ARM AXI bus allowing interactions with the core from Linux running on the MPSoC I3C core is mapped at the 0x80000000 address in ARM memory space. I3C pins are routed to ZCU106 J3 connector:

• SDA to pin 8 of the connector
• SCL to pin 6 of the connector

Both are configured to LVCMOS18 IOSTANDARD with PULLUP enabled.

Fetching the sources

Clone this repository and fetch the submodules, with:

git submodule update --init --recursive

Building the design

Use Vivado 2023.2, run the following command to generate and build the project:

vivado -mode batch -source fpga_i3c_axi.tcl -tclargs BUILD=TRUE

The command should be run in the top directory of the repository

Running the design on ZCU106

• Boot a linux system on the board

• Load the bitstream to the FPGA

  echo "i3c_axi_fpga.bit" > /sys/class/fpga_manager/fpga0/firmware
  

• Set system clock frequency for the I3C core (eg. 200MHz):

  echo 200000000 > /sys/bus/platform/drivers/xilinx_fclk/fclk0/set_rate
  

• Build and run the I3C userspace configuration app to configure the I3C core registers

  ./i3c_userspace
  

The core is now ready to respond to I3C requests.