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ad9208_dual_ebz: Replace adcfifo with data_offload #1598

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5e40ffc
ad9208_dual_ebz: Replace adcfifo with data_offload
podgori Nov 28, 2024
7f045ac
docs: ad9208_dual_ebz: Switch to Data Offload
podgori Jun 5, 2025
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2 changes: 1 addition & 1 deletion docs/projects/ad9208_dual_ebz/ad9208_dual_ebz_block_diagram.svg
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11 changes: 6 additions & 5 deletions docs/projects/ad9208_dual_ebz/index.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -80,8 +80,8 @@ Both links are set for full bandwidth mode and operate with the following parame
Both transport layer components present on their output 256 bits at once
on every clock cycle, representing 8 samples per converter. The two receive
chains are merged together and transferred to the DDR with a single DMA. An
ADC buffer is used to store 65k samples per converter in the fabric before
transferring it with the DMA.
ADC buffer (:git-hdl:`data_offload <library/data_offload>`) is used to store
65k samples per converter in the fabric before transferring it with the DMA.

Block diagram
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Expand Down Expand Up @@ -138,6 +138,7 @@ axi_ad9208_1_xcvr 0x44B6_0000 0x84B6_0000 0xA4B6_00000
rx_ad9208_1_tpl_core 0x44B1_0000 0x84B1_0000 0xA4B1_00000
axi_ad9208_1_jesd 0x44B9_0000 0x84B9_0000 0xA4B9_00000
axi_ad9208_dma 0x7C42_0000 0x9C42_0000 0xBC42_00000
ad9208_data_offload 0x7C43_0000 0x9C43_0000 0xBC43_00000
==================== =============== =========== ============

SPI connections
Expand Down Expand Up @@ -316,9 +317,9 @@ HDL related
* - UTIL_CPACK2
- :git-hdl:`library/util_pack/util_cpack2`
- :ref:`util_cpack2`
* - UTIL_ADCFIFO
- :git-hdl:`library/util_adcfifo`
- ---
* - DATA_OFFLOAD
- :git-hdl:`library/data_offload`
- :ref:`data_offload`
* - UTIL_ADXCVR for AMD
- :git-hdl:`library/xilinx/util_adxcvr`
- :ref:`util_adxcvr`
Expand Down
46 changes: 34 additions & 12 deletions projects/ad9208_dual_ebz/common/ad9208_dual_ebz_bd.tcl
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Expand Up @@ -12,8 +12,9 @@ set RX_SAMPLE_WIDTH 16 ; # N/NP
set RX_SAMPLES_PER_CHANNEL 8 ; # L * 32 / (M * N)

source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl

set adc_fifo_name axi_ad9208_fifo
set adc_offload_name ad9208_data_offload
set adc_data_width 512
set adc_dma_data_width 512

Expand Down Expand Up @@ -76,7 +77,23 @@ ad_ip_instance util_cpack2 util_ad9208_cpack [list \
SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \
]

ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_dma_data_width $adc_fifo_address_width
ad_data_offload_create $adc_offload_name \
0 \
$adc_offload_type \
$adc_offload_size \
$adc_data_width \
$adc_dma_data_width

ad_ip_parameter $adc_offload_name/i_data_offload CONFIG.SYNC_EXT_ADD_INTERNAL_CDC 0
ad_connect $adc_offload_name/sync_ext GND

ad_ip_instance util_vector_logic rx_do_rstout_logic
ad_ip_parameter rx_do_rstout_logic config.c_operation {not}
ad_ip_parameter rx_do_rstout_logic config.c_size {1}

ad_ip_instance util_vector_logic cpack_reset_logic
ad_ip_parameter cpack_reset_logic config.c_operation {or}
ad_ip_parameter cpack_reset_logic config.c_size {1}

ad_ip_instance axi_dmac axi_ad9208_dma
ad_ip_parameter axi_ad9208_dma CONFIG.DMA_TYPE_SRC 1
Expand Down Expand Up @@ -145,15 +162,18 @@ ad_connect glbl_clk_0 rx_ad9208_0_tpl_core/link_clk
ad_connect glbl_clk_0 rx_ad9208_1_tpl_core/link_clk

ad_connect glbl_clk_0 util_ad9208_cpack/clk
ad_connect glbl_clk_0 axi_ad9208_fifo/adc_clk
ad_connect glbl_clk_0 $adc_offload_name/s_axis_aclk

# dma clock domain
ad_connect $sys_cpu_clk axi_ad9208_fifo/dma_clk
ad_connect $sys_cpu_clk $adc_offload_name/m_axis_aclk
ad_connect $sys_cpu_clk axi_ad9208_dma/s_axis_aclk

# connect resets
ad_connect glbl_clk_0_rstgen/peripheral_reset axi_ad9208_fifo/adc_rst
ad_connect glbl_clk_0_rstgen/peripheral_reset util_ad9208_cpack/reset
ad_connect glbl_clk_0_rstgen/peripheral_aresetn $adc_offload_name/s_axis_aresetn
ad_connect glbl_clk_0_rstgen/peripheral_reset cpack_reset_logic/op1
ad_connect rx_do_rstout_logic/res cpack_reset_logic/op2
ad_connect cpack_reset_logic/res util_ad9208_cpack/reset
ad_connect $sys_cpu_resetn $adc_offload_name/m_axis_aresetn
ad_connect $sys_cpu_resetn axi_ad9208_dma/m_dest_axi_aresetn

# connect dataflow
Expand All @@ -176,13 +196,14 @@ for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
ad_connect rx_ad9208_0_tpl_core/adc_dovf util_ad9208_cpack/fifo_wr_overflow
ad_connect rx_ad9208_1_tpl_core/adc_dovf util_ad9208_cpack/fifo_wr_overflow

ad_connect util_ad9208_cpack/packed_fifo_wr_data axi_ad9208_fifo/adc_wdata
ad_connect util_ad9208_cpack/packed_fifo_wr_en axi_ad9208_fifo/adc_wr
ad_connect util_ad9208_cpack/packed_fifo_wr_data $adc_offload_name/s_axis_tdata
ad_connect util_ad9208_cpack/packed_fifo_wr_en $adc_offload_name/s_axis_tvalid
ad_connect $adc_offload_name/s_axis_tlast GND
ad_connect $adc_offload_name/s_axis_tkeep VCC
ad_connect $adc_offload_name/s_axis_tready rx_do_rstout_logic/op1

ad_connect axi_ad9208_fifo/dma_wr axi_ad9208_dma/s_axis_valid
ad_connect axi_ad9208_fifo/dma_wdata axi_ad9208_dma/s_axis_data
ad_connect axi_ad9208_fifo/dma_wready axi_ad9208_dma/s_axis_ready
ad_connect axi_ad9208_fifo/dma_xfer_req axi_ad9208_dma/s_axis_xfer_req
ad_connect $adc_offload_name/m_axis axi_ad9208_dma/s_axis
ad_connect $adc_offload_name/init_req axi_ad9208_dma/s_axis_xfer_req

# interconnect (cpu)

Expand All @@ -193,6 +214,7 @@ ad_cpu_interconnect 0x44b10000 rx_ad9208_1_tpl_core
ad_cpu_interconnect 0x44a90000 axi_ad9208_0_jesd
ad_cpu_interconnect 0x44b90000 axi_ad9208_1_jesd
ad_cpu_interconnect 0x7c420000 axi_ad9208_dma
ad_cpu_interconnect 0x7c430000 $adc_offload_name

# interconnect (gt/adc)

Expand Down
7 changes: 5 additions & 2 deletions projects/ad9208_dual_ebz/vcu118/Makefile
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Expand Up @@ -9,19 +9,22 @@ PROJECT_NAME := ad9208_dual_ebz_vcu118
M_DEPS += ../common/ad9208_dual_ebz_bd.tcl
M_DEPS += ../../scripts/adi_pd.tcl
M_DEPS += ../../daq3/common/daq3_spi.v
M_DEPS += ../../common/xilinx/adcfifo_bd.tcl
M_DEPS += ../../common/vcu118/vcu118_system_constr.xdc
M_DEPS += ../../common/vcu118/vcu118_system_bd.tcl
M_DEPS += ../../common/xilinx/data_offload_bd.tcl
M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
M_DEPS += ../../../library/common/ad_iobuf.v

LIB_DEPS += axi_dmac
LIB_DEPS += axi_sysid
LIB_DEPS += data_offload
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
LIB_DEPS += jesd204/axi_jesd204_rx
LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += sysid_rom
LIB_DEPS += util_adcfifo
LIB_DEPS += util_do_ram
LIB_DEPS += util_hbm
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr
Expand Down
6 changes: 3 additions & 3 deletions projects/ad9208_dual_ebz/vcu118/system_bd.tcl
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Expand Up @@ -3,11 +3,11 @@
### SPDX short identifier: ADIBSD
###############################################################################

## FIFO depth is 4Mb - 250k samples (65k samples per converter)
set adc_fifo_address_width 13
## Offload attributes
set adc_offload_type 0 ; ## BRAM
set adc_offload_size [expr 512*1024] ; ## 512 kB

source $ad_hdl_dir/projects/common/vcu118/vcu118_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
source ../common/ad9208_dual_ebz_bd.tcl
source $ad_hdl_dir/projects/scripts/adi_pd.tcl

Expand Down
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