Rewrite early ready condition

Signed-off-by: Alex Forencich <[email protected]>

Author: alexforencich

rtl/arp_eth_tx.v

@@ -296,8 +296,8 @@ assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
 assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
 assign m_eth_payload_axis_tuser = m_eth_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int));
+// enable ready input next cycle if temp register is empty and output register will be available
+assign m_eth_payload_axis_tready_int_early = !temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || m_eth_payload_axis_tready);
 
 always @* begin
     // transfer sink ready state to source

rtl/axis_eth_fcs_check.v

@@ -280,8 +280,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if temp register is empty and output register will be available
+assign m_axis_tready_int_early = !temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || m_axis_tready);
 
 always @* begin
     // transfer sink ready state to source

rtl/axis_eth_fcs_check_64.v

@@ -414,8 +414,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if temp register is empty and output register will be available
+assign m_axis_tready_int_early = !temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || m_axis_tready);
 
 always @* begin
     // transfer sink ready state to source

rtl/axis_eth_fcs_insert.v

@@ -307,8 +307,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if temp register is empty and output register will be available
+assign m_axis_tready_int_early = !temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || m_axis_tready);
 
 always @* begin
     // transfer sink ready state to source

rtl/axis_eth_fcs_insert_64.v

@@ -653,8 +653,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if temp register is empty and output register will be available
+assign m_axis_tready_int_early = !temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || m_axis_tready);
 
 always @* begin
     // transfer sink ready state to source

rtl/eth_arb_mux.v

@@ -241,8 +241,8 @@ assign m_eth_payload_axis_tid    = ID_ENABLE   ? m_eth_payload_axis_tid_reg   :
 assign m_eth_payload_axis_tdest  = DEST_ENABLE ? m_eth_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_eth_payload_axis_tuser  = USER_ENABLE ? m_eth_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int));
+// enable ready input next cycle if temp register is empty and output register will be available
+assign m_eth_payload_axis_tready_int_early = !temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || m_eth_payload_axis_tready);
 
 always @* begin
     // transfer sink ready state to source

rtl/eth_axis_rx.v

@@ -333,8 +333,8 @@ assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
 assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
 assign m_eth_payload_axis_tuser = m_eth_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int));
+// enable ready input next cycle if temp register is empty and output register will be available
+assign m_eth_payload_axis_tready_int_early = !temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || m_eth_payload_axis_tready);
 
 always @* begin
     // transfer sink ready state to source

rtl/eth_axis_tx.v

@@ -337,8 +337,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if temp register is empty and output register will be available
+assign m_axis_tready_int_early = !temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || m_axis_tready);
 
 always @* begin
     // transfer sink ready state to source

rtl/eth_demux.v

@@ -235,8 +235,8 @@ assign m_eth_payload_axis_tid    = ID_ENABLE   ? {M_COUNT{m_eth_payload_axis_tid
 assign m_eth_payload_axis_tdest  = DEST_ENABLE ? {M_COUNT{m_eth_payload_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}};
 assign m_eth_payload_axis_tuser  = USER_ENABLE ? {M_COUNT{m_eth_payload_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_eth_payload_axis_tready_int_early = (m_eth_payload_axis_tready & m_eth_payload_axis_tvalid) || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid || !m_eth_payload_axis_tvalid_int));
+// enable ready input next cycle if temp register is empty and output register will be available
+assign m_eth_payload_axis_tready_int_early = !temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || (m_eth_payload_axis_tready & m_eth_payload_axis_tvalid));
 
 always @* begin
     // transfer sink ready state to source

rtl/eth_mux.v

@@ -229,8 +229,8 @@ assign m_eth_payload_axis_tid    = ID_ENABLE   ? m_eth_payload_axis_tid_reg   :
 assign m_eth_payload_axis_tdest  = DEST_ENABLE ? m_eth_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_eth_payload_axis_tuser  = USER_ENABLE ? m_eth_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int));
+// enable ready input next cycle if temp register is empty and output register will be available
+assign m_eth_payload_axis_tready_int_early = !temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || m_eth_payload_axis_tready);
 
 always @* begin
     // transfer sink ready state to source

rtl/ip_arb_mux.v

@@ -332,8 +332,8 @@ assign m_ip_payload_axis_tid    = ID_ENABLE   ? m_ip_payload_axis_tid_reg   : {I
 assign m_ip_payload_axis_tdest  = DEST_ENABLE ? m_ip_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_ip_payload_axis_tuser  = USER_ENABLE ? m_ip_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || !m_ip_payload_axis_tvalid_int));
+// enable ready input next cycle if temp register is empty and output register will be available
+assign m_ip_payload_axis_tready_int_early = !temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || m_ip_payload_axis_tready);
 
 always @* begin
     // transfer sink ready state to source

rtl/ip_demux.v

@@ -326,8 +326,8 @@ assign m_ip_payload_axis_tid    = ID_ENABLE   ? {M_COUNT{m_ip_payload_axis_tid_r
 assign m_ip_payload_axis_tdest  = DEST_ENABLE ? {M_COUNT{m_ip_payload_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}};
 assign m_ip_payload_axis_tuser  = USER_ENABLE ? {M_COUNT{m_ip_payload_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_ip_payload_axis_tready_int_early = (m_ip_payload_axis_tready & m_ip_payload_axis_tvalid) || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid || !m_ip_payload_axis_tvalid_int));
+// enable ready input next cycle if temp register is empty and output register will be available
+assign m_ip_payload_axis_tready_int_early = !temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || (m_ip_payload_axis_tready & m_ip_payload_axis_tvalid));
 
 always @* begin
     // transfer sink ready state to source

rtl/ip_eth_rx.v

@@ -516,8 +516,8 @@ assign m_ip_payload_axis_tvalid = m_ip_payload_axis_tvalid_reg;
 assign m_ip_payload_axis_tlast = m_ip_payload_axis_tlast_reg;
 assign m_ip_payload_axis_tuser = m_ip_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || !m_ip_payload_axis_tvalid_int));
+// enable ready input next cycle if temp register is empty and output register will be available
+assign m_ip_payload_axis_tready_int_early = !temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || m_ip_payload_axis_tready);
 
 always @* begin
     // transfer sink ready state to source

rtl/ip_eth_rx_64.v

@@ -622,8 +622,8 @@ assign m_ip_payload_axis_tvalid = m_ip_payload_axis_tvalid_reg;
 assign m_ip_payload_axis_tlast = m_ip_payload_axis_tlast_reg;
 assign m_ip_payload_axis_tuser = m_ip_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || !m_ip_payload_axis_tvalid_int));
+// enable ready input next cycle if temp register is empty and output register will be available
+assign m_ip_payload_axis_tready_int_early = !temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || m_ip_payload_axis_tready);
 
 always @* begin
     // transfer sink ready state to source

rtl/ip_eth_tx.v

@@ -436,8 +436,8 @@ assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
 assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
 assign m_eth_payload_axis_tuser = m_eth_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int));
+// enable ready input next cycle if temp register is empty and output register will be available
+assign m_eth_payload_axis_tready_int_early = !temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || m_eth_payload_axis_tready);
 
 always @* begin
     // transfer sink ready state to source

rtl/ip_eth_tx_64.v

@@ -584,8 +584,8 @@ assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
 assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
 assign m_eth_payload_axis_tuser = m_eth_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready | (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg | !m_eth_payload_axis_tvalid_int));
+// enable ready input next cycle if temp register is empty and output register will be available
+assign m_eth_payload_axis_tready_int_early = !temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || m_eth_payload_axis_tready);
 
 always @* begin
     // transfer sink ready state to source

rtl/ip_mux.v

@@ -320,8 +320,8 @@ assign m_ip_payload_axis_tid    = ID_ENABLE   ? m_ip_payload_axis_tid_reg   : {I
 assign m_ip_payload_axis_tdest  = DEST_ENABLE ? m_ip_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_ip_payload_axis_tuser  = USER_ENABLE ? m_ip_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || !m_ip_payload_axis_tvalid_int));
+// enable ready input next cycle if temp register is empty and output register will be available
+assign m_eth_payload_axis_tready_int_early = !temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || m_eth_payload_axis_tready);
 
 always @* begin
     // transfer sink ready state to source

rtl/udp_arb_mux.v

@@ -360,8 +360,8 @@ assign m_udp_payload_axis_tid    = ID_ENABLE   ? m_udp_payload_axis_tid_reg   :
 assign m_udp_payload_axis_tdest  = DEST_ENABLE ? m_udp_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_udp_payload_axis_tuser  = USER_ENABLE ? m_udp_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid_reg || !m_udp_payload_axis_tvalid_int));
+// enable ready input next cycle if temp register is empty and output register will be available
+assign m_udp_payload_axis_tready_int_early = !temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid_reg || m_udp_payload_axis_tready);
 
 always @* begin
     // transfer sink ready state to source

rtl/udp_demux.v

@@ -354,8 +354,8 @@ assign m_udp_payload_axis_tid    = ID_ENABLE   ? {M_COUNT{m_udp_payload_axis_tid
 assign m_udp_payload_axis_tdest  = DEST_ENABLE ? {M_COUNT{m_udp_payload_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}};
 assign m_udp_payload_axis_tuser  = USER_ENABLE ? {M_COUNT{m_udp_payload_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_udp_payload_axis_tready_int_early = (m_udp_payload_axis_tready & m_udp_payload_axis_tvalid) || (!temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid || !m_udp_payload_axis_tvalid_int));
+// enable ready input next cycle if temp register is empty and output register will be available
+assign m_udp_payload_axis_tready_int_early = !temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid_reg || (m_udp_payload_axis_tready & m_udp_payload_axis_tvalid));
 
 always @* begin
     // transfer sink ready state to source

rtl/udp_ip_rx.v

@@ -471,8 +471,8 @@ assign m_udp_payload_axis_tvalid = m_udp_payload_axis_tvalid_reg;
 assign m_udp_payload_axis_tlast = m_udp_payload_axis_tlast_reg;
 assign m_udp_payload_axis_tuser = m_udp_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid_reg || !m_udp_payload_axis_tvalid_int));
+// enable ready input next cycle if temp register is empty and output register will be available
+assign m_udp_payload_axis_tready_int_early = !temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid_reg || m_udp_payload_axis_tready);
 
 always @* begin
     // transfer sink ready state to source

rtl/udp_ip_rx_64.v

@@ -496,8 +496,8 @@ assign m_udp_payload_axis_tvalid = m_udp_payload_axis_tvalid_reg;
 assign m_udp_payload_axis_tlast = m_udp_payload_axis_tlast_reg;
 assign m_udp_payload_axis_tuser = m_udp_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid_reg || !m_udp_payload_axis_tvalid_int));
+// enable ready input next cycle if temp register is empty and output register will be available
+assign m_udp_payload_axis_tready_int_early = !temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid_reg || m_udp_payload_axis_tready);
 
 always @* begin
     // transfer sink ready state to source

rtl/udp_ip_tx.v

@@ -432,8 +432,8 @@ assign m_ip_payload_axis_tvalid = m_ip_payload_axis_tvalid_reg;
 assign m_ip_payload_axis_tlast = m_ip_payload_axis_tlast_reg;
 assign m_ip_payload_axis_tuser = m_ip_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || !m_ip_payload_axis_tvalid_int));
+// enable ready input next cycle if temp register is empty and output register will be available
+assign m_ip_payload_axis_tready_int_early = !temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || m_ip_payload_axis_tready);
 
 always @* begin
     // transfer sink ready state to source

rtl/udp_ip_tx_64.v

@@ -485,8 +485,8 @@ assign m_ip_payload_axis_tvalid = m_ip_payload_axis_tvalid_reg;
 assign m_ip_payload_axis_tlast = m_ip_payload_axis_tlast_reg;
 assign m_ip_payload_axis_tuser = m_ip_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || !m_ip_payload_axis_tvalid_int));
+// enable ready input next cycle if temp register is empty and output register will be available
+assign m_ip_payload_axis_tready_int_early = !temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || m_ip_payload_axis_tready);
 
 always @* begin
     // transfer sink ready state to source

rtl/udp_mux.v

@@ -348,8 +348,8 @@ assign m_udp_payload_axis_tid    = ID_ENABLE   ? m_udp_payload_axis_tid_reg   :
 assign m_udp_payload_axis_tdest  = DEST_ENABLE ? m_udp_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_udp_payload_axis_tuser  = USER_ENABLE ? m_udp_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid_reg || !m_udp_payload_axis_tvalid_int));
+// enable ready input next cycle if temp register is empty and output register will be available
+assign m_udp_payload_axis_tready_int_early = !temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid_reg || m_udp_payload_axis_tready);
 
 always @* begin
     // transfer sink ready state to source