Rewrite resets

Signed-off-by: Alex Forencich <[email protected]>

Author: alexforencich

rtl/arp_eth_tx.v

@@ -328,15 +328,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_eth_payload_axis_tvalid_reg <= 1'b0;
-        m_eth_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
-        m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
-        temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
-    end
+    m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
+    m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
+    temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
 
     // datapath
     if (store_eth_payload_int_to_output) begin
@@ -357,6 +351,12 @@ always @(posedge clk) begin
         temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
         temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_eth_payload_axis_tvalid_reg <= 1'b0;
+        m_eth_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule

rtl/axis_eth_fcs_check.v

@@ -312,15 +312,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -338,6 +332,12 @@ always @(posedge clk) begin
         temp_m_axis_tlast_reg <= m_axis_tlast_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule

rtl/axis_eth_fcs_check_64.v

@@ -446,15 +446,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -475,6 +469,12 @@ always @(posedge clk) begin
         temp_m_axis_tlast_reg <= m_axis_tlast_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule

rtl/axis_eth_fcs_insert.v

@@ -339,15 +339,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -365,6 +359,12 @@ always @(posedge clk) begin
         temp_m_axis_tlast_reg <= m_axis_tlast_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule

rtl/axis_eth_fcs_insert_64.v

@@ -685,15 +685,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -714,6 +708,12 @@ always @(posedge clk) begin
         temp_m_axis_tlast_reg <= m_axis_tlast_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule

rtl/eth_arb_mux.v

@@ -273,15 +273,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_eth_payload_axis_tvalid_reg <= 1'b0;
-        m_eth_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
-        m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
-        temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
-    end
+    m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
+    m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
+    temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -308,6 +302,12 @@ always @(posedge clk) begin
         temp_m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
         temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_eth_payload_axis_tvalid_reg <= 1'b0;
+        m_eth_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule

rtl/eth_axis_rx.v

@@ -365,15 +365,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_eth_payload_axis_tvalid_reg <= 1'b0;
-        m_eth_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
-        m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
-        temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
-    end
+    m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
+    m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
+    temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
 
     // datapath
     if (store_eth_payload_int_to_output) begin
@@ -394,6 +388,12 @@ always @(posedge clk) begin
         temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
         temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_eth_payload_axis_tvalid_reg <= 1'b0;
+        m_eth_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule

rtl/eth_axis_tx.v

@@ -369,15 +369,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -398,6 +392,12 @@ always @(posedge clk) begin
         temp_m_axis_tlast_reg <= m_axis_tlast_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule

rtl/eth_demux.v

@@ -267,15 +267,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_eth_payload_axis_tvalid_reg <= {M_COUNT{1'b0}};
-        m_eth_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
-        m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
-        temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
-    end
+    m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
+    m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
+    temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -302,6 +296,12 @@ always @(posedge clk) begin
         temp_m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
         temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_eth_payload_axis_tvalid_reg <= {M_COUNT{1'b0}};
+        m_eth_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule

rtl/eth_mux.v

@@ -261,15 +261,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_eth_payload_axis_tvalid_reg <= 1'b0;
-        m_eth_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
-        m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
-        temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
-    end
+    m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
+    m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
+    temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -296,6 +290,12 @@ always @(posedge clk) begin
         temp_m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
         temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_eth_payload_axis_tvalid_reg <= 1'b0;
+        m_eth_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule

rtl/ip_arb_mux.v

@@ -364,15 +364,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_ip_payload_axis_tvalid_reg <= 1'b0;
-        m_ip_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
-        m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
-        temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
-    end
+    m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
+    m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
+    temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -399,6 +393,12 @@ always @(posedge clk) begin
         temp_m_ip_payload_axis_tdest_reg <= m_ip_payload_axis_tdest_int;
         temp_m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_ip_payload_axis_tvalid_reg <= 1'b0;
+        m_ip_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule

rtl/ip_demux.v

@@ -358,15 +358,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_ip_payload_axis_tvalid_reg <= {M_COUNT{1'b0}};
-        m_ip_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
-        m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
-        temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
-    end
+    m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
+    m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
+    temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -393,6 +387,12 @@ always @(posedge clk) begin
         temp_m_ip_payload_axis_tdest_reg <= m_ip_payload_axis_tdest_int;
         temp_m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_ip_payload_axis_tvalid_reg <= {M_COUNT{1'b0}};
+        m_ip_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule