Welcome to my GitHub profile! I'm a passionate VLSI engineer with interest in designing circuits and systems. My interests lie in both the analog and digital domains of VLSI, where I continually strive to innovate and improve.
- Analog Circuit Design Intern (June - July 2023)
- Mentor: Dr. GS Javed, Analog Design Manager @Intel, Bangalore, India
- Description: Designed basic building blocks of Analog Integrated Circuits including common-source amplifier, source follower amplifier, single-stage operational amplifier, two-stage operational amplifier, and filters using the gm over Id methodology.
- A 5GHz Gain-Bandwidth Op-Amp in 180nm technology (May 2024)
- Conference: 4th IEEE International Conference on VLSI Systems, Architecture, Technology, and Applications (VLSI SATA 2024)
- Publication: Click here to view it on IEEE Xplore
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Design of Phase Locked Loop (PLL) (Aug - June 2025) :
- Description: – This project included the complete design and simulation of 2.4 GHz Phase locked loop (PLL) in 180 nm Technology, targeting applications like Bluetooth and Wi-fi.
- It included designing of PLL Blocks : NMOS based LC VCO, Frequency Divider using TSPC DFF, NAND Gate based phase frequency Detector, and Charge Pump and Loop Filter, and in the end integration of all the blocks.
- We successfully verified the functionality of each blocks and then of the Complete PLL calculating its settling time and locking behaviour.
- Tools Used: LT Spice | Technology Node: CMOS 180 nm
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Design and FPGA Implementation of Neural Network based Digit Recognition System (Jan - May 2024) :
- Description: – Design of software model of Neural Network for Handwritten Digit Recognition system using Python. Hardware realisation of the neural network using Verilog HDL, validating behavioural, Post synthesis & Post Implementation Simulations and then ANN is implemented on FPGA.
- Tools Used: Xilinx Vivado, VS Code | FPGA Board: NEXYS A7 I Languages: Verilog HDL & Python
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Design, simulation and layout of Two-Stage Operational Amplifier (June - July 2023) :
- Description: Utilized Gm/Id methodology to design and simulate a Two-Stage Operational Amplifier in the 180 nm technology for the specifications: Gain >1000, Gain Bandwidth Product (GBW) > 1GHz, and Phase Margin of 50.
- Tools Used: LT Spice, Analog Designer Toolbox (ADT), Electric Binary.
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Design and Analysis of CMOS Inverter using CMOS 180nm Technology (Nov 2022) :
- Description: explored MOSFET models for TSMC180nm, Analyzed strong 0/1 and weak 1/0 logic configurations through simulation. Designed CMOS Inverter, and analysed its voltage transfer characteristics and key design parameters like VOH, VOL, VIH, VIL, and the switching threshold, with its layout using Electric Binary.
- Tools Used: LT Spice, Electric Binary.
