The W55MH32 chip is a cost-effective system-in-package (SiP) solution with a 32-bit Arm ® Cortex ®-M3 Core core and rich interfaces. It also integrates a TCP/IP offload engine (TOE) using WIZnet's patented full-hardware TCP/IP stack technology.
WIZnet's full-hardware TCP/IP stack solution has been proven in numerous applications over the years, supporting TCP, UDP, IPv4, ICMP, ARP, IGMP and PPPoE protocols. TOE embeds 32KB of internal cache for Ethernet data packet processing.
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32-bit Arm® Cortex®-M3 Core, with a maximum operating frequency up to 216MHz.
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1024K bytes FLASH, 96K bytes SRAM
- 3 x 12 bit ADC，2 x 12 bit DAC
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55 x GPIO
- As many as 12 communication interfaces
- Up to 2 I2C interfaces.
- Up to 5 USART interfaces
- Up to 2 SPI interfaces.
- CAN interface (2.0B active)
- USB 2.0 full speed interface
- SDIO interface
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TOE
- 10/100 Mbps Ethernet MAC and PHY
- Full hardware TCP/IP protocol stack, support TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE
- 8 independent hardware sockets
- Integrated 10BaseT/100BaseT Ethernet PHY
- Support automatic negotiation
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Hardware encryption algorithm unit
- TRNG cells are used to generate true random number sequences
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SRAM scrambling
- debug
- Serial single-wire debugging (SWD) and JTAG interfaces
- Embedded Tracking Module (ETM)
website：https://wiznet.io/
github:WIZnet (github.com)
gitee:WIZnet HK (wiznet-hk) - Gitee.com