Add testbench for or instruction
#48
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Pull Request Overview
This PR adds a SystemVerilog testbench for the or instruction as part of task #45. The testbench verifies the correct execution of a bitwise OR operation through all stages of the processor pipeline.
Key Changes
- Creates a comprehensive testbench that validates the
orinstruction execution from fetch to writeback - Tests the instruction decoding, ALU operation, and register file updates
- Includes verification of intermediate states and final results
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One of the tasks in #45