Implement ParitySynth in xDSL without connectivity-awareness

[dwierichs]

Context:
ParitySynth by Vandaele et al. is a method to re-synthesize phase polynomial (sub)circuits, i.e. (sub)circuits consisting of Z-rotations and CNOT gates.
Also see the compilation hub entry on phase polynomials.

Description of the Change:
Implement ParitySynth as an xDSL pass.

Benefits:
New pass added to PennyLane and to new xDSL-based compiler framework in particular.

Possible Drawbacks:
N/A

Related GitHub Issues:

[sc-100926]

[codecov]

Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 99.42%. Comparing base (60f4f10) to head (c038a3c).
⚠️ Report is 1 commits behind head on master.

Additional details and impacted files

@@            Coverage Diff             @@
##           master    #8414      +/-   ##
==========================================
- Coverage   99.42%   99.42%   -0.01%     
==========================================
  Files         584      584              
  Lines       61323    61323              
==========================================
- Hits        60972    60971       -1     
- Misses        351      352       +1     

☔ View full report in Codecov by Sentry.
📢 Have feedback on the report? Share it here.

🚀 New features to boost your workflow:

• ❄️ Test Analytics: Detect flaky tests, report on failures, and find test suite problems.