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Update the Arista platform to use the OpenFDK. #4

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Update the Arista platform to use the OpenFDK. #4

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863deba
Insert an I2C bus between the PCIe bus and the AXI slaves
wingel Jan 13, 2022
a3cd619
Add new xi2c driver and support in libntsfpga
wingel Nov 9, 2021
493a833
Update submodules
wingel Nov 23, 2021
92da076
Make clocks single ended
wingel Nov 22, 2021
c963ae4
Initialize all network paths
wingel Nov 23, 2021
6132163
Python2 compatibility
wingel Nov 23, 2021
bbbda53
Fix spelling error
wingel Dec 6, 2021
c3a0806
Remove ; at end of lines
wingel Dec 6, 2021
602bb7e
Update vcu118 program_fpga.sh script for alternate vivado locations.
wingel Jan 13, 2022
e5dc2b3
Update README.md
wingel Jan 17, 2022
2b974ea
Add Linux_Driver infrastructure for Arista platform
wingel Jan 17, 2022
ffcfd5e
Create ntps_arista based on arista_fdk-2.0.0beta1/examples/tscore
wingel Jan 17, 2022
67d06f8
Set IPv6 addresses when initializing FPGA
wingel Feb 3, 2022
26ecd3b
Merge pull request #1 from Netnod/arista
dcasnowdon Mar 9, 2023
6aeea74
Feature/deveco 770 build ntp server as fdk app (#2)
dcasnowdon Mar 9, 2023
8db03b4
Merged.
dcasnowdon Mar 27, 2023
0932bb7
Change to use Netnod's forks of the various submodules.
dcasnowdon Mar 27, 2023
6777729
Make edits to transition to FDK 2.4. Once this is done we should see …
dcasnowdon Mar 27, 2023
89ec648
Remove device DNA wrapper.
dcasnowdon Mar 27, 2023
49603e0
Make wget quieter.
dcasnowdon Mar 27, 2023
6eddf91
Add a build rule to download and unpack Xilinx sources.
dcasnowdon Mar 27, 2023
c5ece3c
We should be building .swix files, not .rpm.
dcasnowdon Mar 27, 2023
0fbdade
Update rules for downloading Xilinx code.
dcasnowdon Mar 27, 2023
c488d18
Add the tscore wrapper.
dcasnowdon Mar 27, 2023
c5cd9ac
Merge branch 'arista-devel' into feature/FDK-93-update-to-FDK-2.4-round2
dcasnowdon Mar 27, 2023
b182e27
Remove bitstream ID since it's a reserved signal.
dcasnowdon Mar 27, 2023
38a762a
Feature/fdk 93 update to fdk 2.4 (#5)
dcasnowdon Mar 28, 2023
05b97d3
Merge branch 'devel' into arista-devel
May 16, 2023
63d81a8
use the open FDK as a submodule to avoid hving to have a separate dow…
May 16, 2023
10191a1
Update to the latest 2.6 release of the FDK.
dcasnowdon May 25, 2023
af0778b
Update openfdk to the 2.6 release.
dcasnowdon May 25, 2023
2488955
feature/FDK-140 port the FPGA NTPS server to open fdk (#6)
dcasnowdon May 31, 2023
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31 changes: 17 additions & 14 deletions .gitmodules
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Original file line number Diff line number Diff line change
@@ -1,42 +1,45 @@
[submodule "FPGA/cores/aes"]
path = FPGA/cores/aes
url = ../aes.git
url = ../../Netnod/aes.git
[submodule "FPGA/cores/aes-siv"]
path = FPGA/cores/aes-siv
url = ../aes-siv.git
url = ../../Netnod/aes-siv.git
[submodule "FPGA/cores/cmac"]
path = FPGA/cores/cmac
url = ../cmac.git
url = ../../Netnod/cmac.git
[submodule "FPGA/cores/md5"]
path = FPGA/cores/md5
url = ../md5.git
url = ../../Netnod/md5.git
[submodule "FPGA/cores/sha1"]
path = FPGA/cores/sha1
url = ../sha1.git
url = ../../Netnod/sha1.git
[submodule "FPGA/cores/siphash"]
path = FPGA/cores/siphash
url = ../siphash.git
url = ../../Netnod/siphash.git
[submodule "FPGA/cores/api_extension"]
path = FPGA/network_path/api_extension
url = ../api_extension.git
url = ../../Netnod/api_extension.git
[submodule "FPGA/cores/keymem"]
path = FPGA/network_path/keymem
url = ../keymem.git
url = ../../Netnod/keymem.git
[submodule "FPGA/cores/nts"]
path = FPGA/network_path/nts
url = ../nts.git
url = ../../Netnod/nts.git
[submodule "FPGA/cores/nts_noncegen"]
path = FPGA/network_path/nts_noncegen
url = ../nts_noncegen.git
url = ../../Netnod/nts_noncegen.git
[submodule "FPGA/cores/rosc_entropy"]
path = FPGA/cores/rosc_entropy
url = ../rosc_entropy
url = ../../Netnod/rosc_entropy
[submodule "FPGA/cores/verilog-ethernet"]
path = FPGA/cores/verilog-ethernet
url = ../verilog-ethernet
url = ../../Netnod/verilog-ethernet
[submodule "FPGA/cores/verilog-i2c"]
path = FPGA/cores/verilog-i2c
url = ../verilog-i2c
url = ../../Netnod/verilog-i2c
[submodule "FPGA/cores/neorv32"]
path = FPGA/cores/neorv32
url = ../neorv32
url = ../../Netnod/neorv32
[submodule "FPGA/cores/openfdk"]
path = FPGA/cores/openfdk
url = https://github.com/aristanetworks/openfdk.git
2 changes: 1 addition & 1 deletion FPGA/cores/aes-siv
Open in desktop
Submodule aes-siv updated 5 files
+2 −6 src/rtl/aes_siv.v
+2 −6 src/rtl/aes_siv_core.v
+2 −6 src/tb/tb_aes_siv_core.v
+2 −6 src/tb/tb_core_mem.v
+2 −6 src/util/wrapper_aes_siv_core.v
2 changes: 1 addition & 1 deletion FPGA/cores/download-and-unpack.sh
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ DOWNLOADS=../../downloads

if [ ! -f v7_xt_conn_trd/readme.txt ]; then
mkdir -p $DOWNLOADS
wget -nc -P $DOWNLOADS https://www.xilinx.com/support/documentation/boards_and_kits/vc709/2014_3/rdf0285-vc709-connectivity-trd-2014-3.zip
wget -nv -nc -P $DOWNLOADS https://www.xilinx.com/support/documentation/boards_and_kits/vc709/2014_3/rdf0285-vc709-connectivity-trd-2014-3.zip
rm -rf v7_xt_conn_trd
unzip -q $DOWNLOADS/rdf0285-vc709-connectivity-trd-2014-3.zip
fi
1 change: 1 addition & 0 deletions FPGA/cores/openfdk
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Submodule openfdk added at 7406ee
2 changes: 1 addition & 1 deletion FPGA/cores/verilog-i2c
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Submodule verilog-i2c updated 1 files
+7 −27 rtl/i2c_init.v
2 changes: 1 addition & 1 deletion FPGA/network_path/keymem
Open in desktop
Submodule keymem updated 4 files
+2 −6 src/rtl/ntp_auth_keymem.v
+2 −6 src/rtl/nts_keymem.v
+2 −6 src/tb/tb_ntp_auth_keymem.v
+2 −6 src/tb/tb_nts_keymem.v
2 changes: 1 addition & 1 deletion FPGA/network_path/nts
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Submodule nts updated 35 files
+18 −26 src/rtl/memory/bram.v
+18 −26 src/rtl/memory/bram_dp2w.v
+18 −26 src/rtl/memory/bram_dpge.v
+18 −26 src/rtl/memory/memory_ctrl.v
+18 −26 src/rtl/misc/counter64.v
+18 −26 src/rtl/nts_dispatcher.v
+18 −26 src/rtl/nts_dispatcher_mux.v
+18 −26 src/rtl/nts_engine/ctrl_gre.v
+18 −26 src/rtl/nts_engine/icmp.v
+18 −26 src/rtl/nts_engine/ntp_auth.v
+18 −26 src/rtl/nts_engine/nts_api.v
+18 −26 src/rtl/nts_engine/nts_engine.v
+19 −27 src/rtl/nts_engine/nts_parser_ctrl.v
+18 −26 src/rtl/nts_engine/nts_rx_buffer.v
+18 −26 src/rtl/nts_engine/nts_timestamp.v
+18 −26 src/rtl/nts_engine/nts_tx_buffer.v
+18 −26 src/rtl/nts_engine/nts_verify_secure.v
+18 −26 src/rtl/nts_extractor.v
+26 −34 src/rtl/nts_extractor_mux.v
+18 −26 src/rtl/nts_extractor_tx.v
+18 −26 src/rtl/nts_top.v
+18 −26 src/rtl/preprocessor.v
+18 −26 src/tb/memory/bram_tb.v
+18 −26 src/tb/memory/memory_ctrl_tb.v
+18 −26 src/tb/nts_dispatcher_tb.v
+18 −26 src/tb/nts_engine/nts_api_tb.v
+18 −26 src/tb/nts_engine/nts_engine_tb.v
+18 −26 src/tb/nts_engine/nts_parser_ctrl_tb.v
+18 −26 src/tb/nts_engine/nts_rx_buffer_tb.v
+18 −26 src/tb/nts_engine/nts_timestamp_tb.v
+18 −26 src/tb/nts_engine/nts_tx_buffer_tb.v
+18 −26 src/tb/nts_engine/nts_verify_secure_tb.v
+18 −26 src/tb/nts_engine/tb_ntp_auth.v
+18 −26 src/tb/nts_extractor_tb.v
+18 −26 src/tb/nts_top_tb.v
2 changes: 1 addition & 1 deletion FPGA/network_path/nts_noncegen
Open in desktop
Submodule nts_noncegen updated 2 files
+2 −6 src/rtl/nts_noncegen.v
+2 −6 src/tb/tb_nts_noncegen.v
27 changes: 16 additions & 11 deletions FPGA/targets/ntps_arista/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ BUILD_ID ?= 1

PROJECT_DIR = $(CURDIR)
ARISTA_FDK_VERSION ?= 2.5.0
ARISTA_FDK_DIR ?= $(PROJECT_DIR)/../../../arista_fdk-$(ARISTA_FDK_VERSION)
ARISTA_FDK_DIR ?= $(PROJECT_DIR)/../../openfdk
ARISTA_SRC_DIR = $(ARISTA_FDK_DIR)/src

SOURCE_FILES = $(PROJECT_DIR)/src_files.json
Expand Down Expand Up @@ -131,20 +131,25 @@ app::
/bin/time nice make BOARDSTD="$(BOARDSTD)" 2>&1 | tee log

#-------------------------------------------------------------------------------
# Include Arista Build Scripts
#-------------------------------------------------------------------------------
include $(ARISTA_FDK_DIR)/resources/app.mk
include $(ARISTA_FDK_DIR)/resources/vivado.mk

#-------------------------------------------------------------------------------
# Rules to copy user files from the FDK.
# FIXME: These should be migrated to the IP core instead.
# Rules to copy user files from the FDK.
# FIXME: These should be migrated to the IP core instead.
#-------------------------------------------------------------------------------

$(APP_STAGING_DIR)/clockappdaemon.py $(APP_STAGING_DIR)/format_docstring.py: $(ARISTA_FDK_DIR)/examples/tscore/src/$$(@F)
$(APP_STAGING_DIR)/clockappdaemon.py $(APP_STAGING_DIR)/format_docstring.py: $(ARISTA_FDK_DIR)/examples/tscore_nomac/src/$$(@F)
mkdir -p $(@D) && cp $< $@
echo $(APP_STAGING_DIR)

$(APP_STAGING_DIR)/daemon/%:$(ARISTA_FDK_DIR)/examples/tscore/src/daemon/%
$(APP_STAGING_DIR)/daemon/%:$(ARISTA_FDK_DIR)/examples/tscore_nomac/src/daemon/%
mkdir -p $(@D) && cp $< $@
echo $(APP_STAGING_DIR)


#-------------------------------------------------------------------------------
# Download the Xilinx sources if they don't exist
#-------------------------------------------------------------------------------

$(PROJECT_DIR)/../../cores/v7_xt_conn_trd/%: |$(PROJECT_DIR)/../../cores/v7_xt_conn_trd
@

$(PROJECT_DIR)/../../cores/v7_xt_conn_trd: $(PROJECT_DIR)/../../cores/download-and-unpack.sh
cd $(<D) && bash $(<F)
4 changes: 2 additions & 2 deletions FPGA/targets/ntps_arista/build.sh
View file
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
#! /bin/bash
set -euxo pipefail

ARISTA_FDK_DIR=${ARISTA_FDK_DIR:-$(pwd)/../../../arista_fdk-2.5.0}
ARISTA_FDK_DIR=${ARISTA_FDK_DIR:-$(pwd)/../../cores/openfdk}
echo "Building using Arista FDK in $ARISTA_FDK_DIR"

# I can't figure out how to put vhdl files in a library using the
Expand All @@ -17,7 +17,7 @@ find build/neorv32 build/processor -type f | xargs sed -i 's/neorv32\./work./g'
vivado -nojournal -nolog -notrace -mode batch -source create_buildinfo.tcl

/bin/time nice make ARISTA_FDK_DIR=$ARISTA_FDK_DIR BOARDSTD=lb2 2>&1 | tee log
if ! test -f ntps-4.0.0.x86_64.rpm; then
if ! test -f ntps-4.0.0.swix; then
echo "Build failed" 1>&2
exit 1
fi
91 changes: 45 additions & 46 deletions FPGA/targets/ntps_arista/src/ntps-lb2-cfg.json
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Original file line number Diff line number Diff line change
Expand Up @@ -2,54 +2,53 @@
"license": "bsd-3-clause",
"sources_1": [
"${ARISTA_FDK_DIR}/src/arista_sysctl/arista_sysctl_v2.vhd",
"${ARISTA_FDK_DIR}/src/arista_sysctl/eeprom_ctrl_wrapper.vhd",
"${ARISTA_FDK_DIR}/src/arista_sysctl/eeprom_parser_core.vhd",
"${ARISTA_FDK_DIR}/src/arista_sysctl/i2c_base_slave.vhd",
"${ARISTA_FDK_DIR}/src/arista_sysctl/i2c_drp_bridge.vhd",
"${ARISTA_FDK_DIR}/src/arista_sysctl/i2c_eeprom_controller.vhd",
"${ARISTA_FDK_DIR}/src/arista_sysctl/i2c_master.vhd",
"${ARISTA_FDK_DIR}/src/arista_sysctl/i2c_reg_protocol.vhd",
"${ARISTA_FDK_DIR}/src/axi/amba_pkg.vhd",
"${ARISTA_FDK_DIR}/src/arista_sysctl/eeprom_ctrl_wrapper.vhd",
"${ARISTA_FDK_DIR}/src/arista_sysctl/eeprom_parser_core.vhd",
"${ARISTA_FDK_DIR}/src/arista_sysctl/i2c_base_slave.vhd",
"${ARISTA_FDK_DIR}/src/arista_sysctl/i2c_drp_bridge.vhd",
"${ARISTA_FDK_DIR}/src/arista_sysctl/i2c_eeprom_controller.vhd",
"${ARISTA_FDK_DIR}/src/arista_sysctl/i2c_master.vhd",
"${ARISTA_FDK_DIR}/src/arista_sysctl/i2c_reg_protocol.vhd",
"${ARISTA_FDK_DIR}/src/axi/amba_pkg.vhd",
"${ARISTA_FDK_DIR}/src/board_common/board_common_pkg.vhd",
"${ARISTA_FDK_DIR}/src/boards/lb2/board_pkg.vhd",
"${ARISTA_FDK_DIR}/src/clock_modules/ocxo_freq_trim_spi.vhd",
"${ARISTA_FDK_DIR}/src/crc/crc8_pkg.vhd",
"${ARISTA_FDK_DIR}/src/fpga_spec/fpga_spec_pkg.vhd",
"${ARISTA_FDK_DIR}/src/boards/lb2/board_pkg.vhd",
"${ARISTA_FDK_DIR}/src/clock_modules/ocxo_freq_trim_spi.vhd",
"${ARISTA_FDK_DIR}/src/crc/crc8_pkg.vhd",
"${ARISTA_FDK_DIR}/src/fpga_spec/fpga_spec_pkg.vhd",
"${ARISTA_FDK_DIR}/src/hermes/hermes_pkg.vhd",
"${ARISTA_FDK_DIR}/src/hphy_xilinx/phy_pkg.vhd",
"${ARISTA_FDK_DIR}/src/metachron/metachron_controller.vhd",
"${ARISTA_FDK_DIR}/src/metachron/metachron_counter_ts.vhd",
"${ARISTA_FDK_DIR}/src/metachron/metachron_pkg.vhd",
"${ARISTA_FDK_DIR}/src/metachron/metachron_synchroniser.vhd",
"${ARISTA_FDK_DIR}/src/metachron/metachron_synchroniser_fe_re.vhd",
"${ARISTA_FDK_DIR}/src/metachron/metachron_synchroniser_iddr.vhd",
"${ARISTA_FDK_DIR}/src/metachron/metachron_trigger_holdoff.vhd",
"${ARISTA_FDK_DIR}/src/metamako/edge_detect.vhd",
"${ARISTA_FDK_DIR}/src/metamako/metamako_pkg.vhd",
"${ARISTA_FDK_DIR}/src/metamako/pcie_pkg.vhd",
"${ARISTA_FDK_DIR}/src/primitive_xilinx/mako_dff_clr.vhd",
"${ARISTA_FDK_DIR}/src/primitive_xilinx/mako_dff_preset.vhd",
"${ARISTA_FDK_DIR}/src/primitive_xilinx/xil_pllbase.vhd",
"${ARISTA_FDK_DIR}/src/hphy_xilinx/phy_pkg.vhd",
"${ARISTA_FDK_DIR}/src/metachron/metachron_controller.vhd",
"${ARISTA_FDK_DIR}/src/metachron/metachron_counter_ts.vhd",
"${ARISTA_FDK_DIR}/src/metachron/metachron_pkg.vhd",
"${ARISTA_FDK_DIR}/src/metachron/metachron_synchroniser.vhd",
"${ARISTA_FDK_DIR}/src/metachron/metachron_synchroniser_fe_re.vhd",
"${ARISTA_FDK_DIR}/src/metachron/metachron_synchroniser_iddr.vhd",
"${ARISTA_FDK_DIR}/src/metachron/metachron_trigger_holdoff.vhd",
"${ARISTA_FDK_DIR}/src/metamako/edge_detect.vhd",
"${ARISTA_FDK_DIR}/src/metamako/metamako_pkg.vhd",
"${ARISTA_FDK_DIR}/src/metamako/pcie_pkg.vhd",
"${ARISTA_FDK_DIR}/src/primitive_xilinx/mako_dff_clr.vhd",
"${ARISTA_FDK_DIR}/src/primitive_xilinx/mako_dff_preset.vhd",
"${ARISTA_FDK_DIR}/src/primitive_xilinx/xil_pllbase.vhd",
"${ARISTA_FDK_DIR}/src/regfile/i2c_slave_deglitch.vhd",
"${ARISTA_FDK_DIR}/src/regfile/reg_file_pkg.vhd",
"${ARISTA_FDK_DIR}/src/regfile/reg_flexi_pkg.vhd",
"${ARISTA_FDK_DIR}/src/regfile/reg_hs_counter.vhd",
"${ARISTA_FDK_DIR}/src/seu/ip/xcvu9p-flgb2104-3-e/sem_mit_100M/sem_mit_100M.xci",
"${ARISTA_FDK_DIR}/src/seu/ip/xcvu9p-flgb2104-3-e/sem_mit_78M125/sem_mit_78M125.xci",
"${ARISTA_FDK_DIR}/src/regfile/reg_file_pkg.vhd",
"${ARISTA_FDK_DIR}/src/regfile/reg_flexi_pkg.vhd",
"${ARISTA_FDK_DIR}/src/regfile/reg_hs_counter.vhd",
"${ARISTA_FDK_DIR}/src/seu/ip/xcvu9p-flgb2104-3-e/sem_mit_100M/sem_mit_100M.xci",
"${ARISTA_FDK_DIR}/src/seu/ip/xcvu9p-flgb2104-3-e/sem_mit_78M125/sem_mit_78M125.xci",
"${ARISTA_FDK_DIR}/src/seu/ip/xcvu9p-flgb2104-3-e/sem_mit_test_100M/sem_mit_test_100M.xci",
"${ARISTA_FDK_DIR}/src/seu/xil_sem.vhd",
"${ARISTA_FDK_DIR}/src/spi/spi_master.vhd",
"${ARISTA_FDK_DIR}/src/synchroniser/sync_pulse.vhd",
"${ARISTA_FDK_DIR}/src/synchroniser/sync_tgl_to_pulse.vhd",
"${ARISTA_FDK_DIR}/src/synchroniser/sync_vec.vhd",
"${ARISTA_FDK_DIR}/src/synchroniser/synchroniser.vhd",
"${ARISTA_FDK_DIR}/src/ts_ipcore/clk_gen.vhd",
"${ARISTA_FDK_DIR}/src/ts_ipcore/time_sync.vhd",
"${ARISTA_FDK_DIR}/src/ts_ipcore/timestamper.vhd",
"${ARISTA_FDK_DIR}/src/ts_ipcore/timing_controller.vhd",
"${ARISTA_FDK_DIR}/src/seu/xil_sem.vhd",
"${ARISTA_FDK_DIR}/src/spi/spi_master.vhd",
"${ARISTA_FDK_DIR}/src/synchroniser/sync_pulse.vhd",
"${ARISTA_FDK_DIR}/src/synchroniser/sync_tgl_to_pulse.vhd",
"${ARISTA_FDK_DIR}/src/synchroniser/sync_vec.vhd",
"${ARISTA_FDK_DIR}/src/synchroniser/synchroniser.vhd",
"${ARISTA_FDK_DIR}/src/ts_ipcore/clk_gen.vhd",
"${ARISTA_FDK_DIR}/src/ts_ipcore/time_sync.vhd",
"${ARISTA_FDK_DIR}/src/ts_ipcore/timestamper.vhd",
"${ARISTA_FDK_DIR}/src/ts_ipcore/timing_controller.vhd",
"${ARISTA_FDK_DIR}/src/ts_ipcore/tscore.vhd",
"${ARISTA_FDK_DIR}/src/ts_ipcore/tscore_wrapper.vhd",
"${ARISTA_FDK_DIR}/src/yart/drp_pkg.vhd",
"${ARISTA_FDK_DIR}/src/ts_ipcore/tscore_wrapper.vhd",
"${ARISTA_FDK_DIR}/src/yart/yart_i2c.vhd",
"${ARISTA_FDK_DIR}/src/yart/yart_leaf_decode_v2.vhd",
"${ARISTA_FDK_DIR}/src/yart/yart_pkg.vhd",
Expand Down Expand Up @@ -188,8 +187,8 @@
],
"constrs_1": [
"${PROJECT_DIR}/../../cores/verilog-ethernet/lib/axis/syn/sync_reset.tcl",
"${ARISTA_FDK_DIR}/src/boards/lb2/board_constraints.xdc",
"${ARISTA_FDK_DIR}/src/ts_ipcore/tscore.xdc",
"${ARISTA_FDK_DIR}/src/boards/lb2/board_constraints.xdc",
"${ARISTA_FDK_DIR}/src/ts_ipcore/tscore.xdc",
"${PROJECT_DIR}/src/ntps-lb2-top.xdc"
]
]
}