Multi layer buffer placement #587

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Draft

tomasoignons wants to merge 2 commits into EPFL-LAP:skippable-sequentializer from tomasoignons:multi-layer-buffer-placement

tomasoignons commented Aug 29, 2025

Added multi layer graph placement, to solve the FTD buffer placement issue

Check wich Data flow edges are not contained in the Control flow
Add Active path constraints to these edges

tomasoignons added 2 commits

August 27, 2025 15:35


          added multigraph for fpga20

7a882a1


          implemented multiple graphs on fpl22

c214502

tomasoignons marked this pull request as draft

August 29, 2025 10:34

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet