Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf

RawHash can accurately and efficiently map raw nanopore signals to reference genomes of varying sizes (e.g., from viral to a human genomes) in real-time without basecalling. Described by Firtina et al. (published at https://academic.oup.com/bioinformatics/article/39/Supplement_1/i297/7210440).

DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM2 chips and DDR4 modules of different form factors. Six prototypes are available on different FPGA boards. Described in our preprint: https://arxiv.org/pdf/2211.05838.pdf

EasyDRAM is an FPGA-based framework for rapid and accurate end-to-end evaluation of DRAM techniques on real DRAM chips. Described in our DSN 2025 paper: https://arxiv.org/abs/2506.10441

MQSim is a fast & accurate simulator for modern multi-queue (MQ) and SATA SSDs. MQSim faithfully models new high-bandwidth protocol implementations, steady-state SSD conditions, and full end-to-end latency of requests in modern SSDs. Described in detail in the FAST 2018 paper: http://usenix.org/system/files/conference/fast18/fast18-tavakkol.pdf

Data and code for the VTS'25 paper "Revisiting DRAM Read Disturbance: Identifying Inconsistencies Between Experimental Characterization and Device-Level Studies." Described in our VTS 2025 paper: https://www.arxiv.org/pdf/2503.16749

Virtuoso is a fast, accurate and versatile simulation framework designed for virtual memory research. Virtuoso uses a new simulation methodology for estimating OS overheads and models diverse VM designs, incorporating state-of-the-art TLB techniques, page table structures etc. More details in our ASPLOS 2025 paper: https://arxiv.org/pdf/2403.04635

PIM-TC implements a distributed Triangle Counting (TC) algorithm specifically designed for and evaluated on the UPMEM Processing-in-Memory (PIM) architecture. Described in our paper https://arxiv.org/abs/2505.04269.

PyGim is the first runtime framework to efficiently execute Graph Neural Networks (GNNs) on real Processing-in-Memory systems. It provides a high-level Python interface, currently integrated with PyTorch, and supports various GNN models and real-world input graphs. Described by SIGMETRICS'25 by Giannoula et al. (https://arxiv.org/pdf/2402.16731)

IMPACT is a new framework that leverages Processing-in-Memory (PiM) to amplify data leakage in main memory-based timing attacks. More details: https://arxiv.org/abs/2404.11284