diff --git a/.github/ISSUE_TEMPLATE/application-note-not-compliant.md b/.github/ISSUE_TEMPLATE/application-note-not-compliant.md deleted file mode 100644 index 90723cb..0000000 --- a/.github/ISSUE_TEMPLATE/application-note-not-compliant.md +++ /dev/null @@ -1,17 +0,0 @@ ---- -name: Application Note Issue -about: Template for an Application note issue report -title: examples/ANXXXXX Application Note not compliant -labels: documentation -assignees: '' - ---- - - - - -**Issues:** - - - xdoc-custom RST directives used in the Application Note README - - application note code not compiling for xcore-ai - - application note code not running successfully on xcore-ai diff --git a/.github/ISSUE_TEMPLATE/example-not-compliant.md b/.github/ISSUE_TEMPLATE/example-not-compliant.md deleted file mode 100644 index 5e68cdb..0000000 --- a/.github/ISSUE_TEMPLATE/example-not-compliant.md +++ /dev/null @@ -1,18 +0,0 @@ ---- -name: Example Issue -about: Template for an example issue report -title: examples/xxx Example not compliant -labels: documentation -assignees: '' - ---- - - - - -**Issues:** - - - convert example to Application Note - - xdoc-custom RST directives used in the README - - example code not compiling for xcore-ai - - example code not running successfully on xcore-ai diff --git a/.github/ISSUE_TEMPLATE/missing-application-note.md b/.github/ISSUE_TEMPLATE/missing-application-note.md deleted file mode 100644 index 9404dde..0000000 --- a/.github/ISSUE_TEMPLATE/missing-application-note.md +++ /dev/null @@ -1,10 +0,0 @@ ---- -name: Missing Application Note -about: Template for a Missing Application Note issue report -title: Missing Application Note -labels: documentation -assignees: '' - ---- - - diff --git a/.github/ISSUE_TEMPLATE/missing-c-api.md b/.github/ISSUE_TEMPLATE/missing-c-api.md deleted file mode 100644 index 6230ef7..0000000 --- a/.github/ISSUE_TEMPLATE/missing-c-api.md +++ /dev/null @@ -1,10 +0,0 @@ ---- -name: Missing C API Issue -about: Template for a Missing C API issue report -title: Missing C API -labels: enhancement -assignees: '' - ---- - - diff --git a/.github/ISSUE_TEMPLATE/missing-xcore-test.md b/.github/ISSUE_TEMPLATE/missing-xcore-test.md deleted file mode 100644 index 866e97c..0000000 --- a/.github/ISSUE_TEMPLATE/missing-xcore-test.md +++ /dev/null @@ -1,10 +0,0 @@ ---- -name: Missing xCore Test Issue -about: Template for a Missing xCore test issue report -title: Missing xCore test -labels: testing -assignees: '' - ---- - - diff --git a/.github/ISSUE_TEMPLATE/test-not-compliant.md b/.github/ISSUE_TEMPLATE/test-not-compliant.md deleted file mode 100644 index cce3e91..0000000 --- a/.github/ISSUE_TEMPLATE/test-not-compliant.md +++ /dev/null @@ -1,16 +0,0 @@ ---- -name: Test Issue -about: Template for a Test issue report -title: tests/XXX does not build or fails -labels: testing -assignees: '' - ---- - - - - -**Issues:** - - - Test not compiling for xcore-ai - - Test not running successfully on xcore-ai diff --git a/.github/ISSUE_TEMPLATE/top-level-readme-not-compliant.md b/.github/ISSUE_TEMPLATE/top-level-readme-not-compliant.md deleted file mode 100644 index 931414c..0000000 --- a/.github/ISSUE_TEMPLATE/top-level-readme-not-compliant.md +++ /dev/null @@ -1,13 +0,0 @@ ---- -name: Top-level README Issue -about: Template for the top-level README issue report -title: Top-level README not compliant -labels: documentation -assignees: '' - ---- - - -**Issues:** - - - xdoc-custom RST directives used in the README diff --git a/.gitignore b/.gitignore index 40b6123..b7fafa1 100644 --- a/.gitignore +++ b/.gitignore @@ -25,6 +25,9 @@ build/ # satisfy parsing in XMOS source check based on regular expressions # (normal parsing is based on shell wildcards) -*/.venv* +*.venv* */build/* __gen +*tests/logs/* +*.gtkw +*.xmt diff --git a/Brewfile b/Brewfile deleted file mode 100644 index 2fd6d0b..0000000 --- a/Brewfile +++ /dev/null @@ -1,7 +0,0 @@ -tap 'homebrew/core' - -brew 'perl' -brew 'cpanm' - -brew 'python@2' -brew 'pipenv' diff --git a/CHANGELOG.rst b/CHANGELOG.rst index 4029b95..bed6c0c 100644 --- a/CHANGELOG.rst +++ b/CHANGELOG.rst @@ -1,5 +1,32 @@ -SPI library change log -====================== +lib_spi change log +================== + +4.0.0 +----- + + * CHANGED: SPI master async reduced clock blocks from two to one + * CHANGED: SPI master sync increased max speed to 50+ Mbps + * ADDED: Shutdown method for SPI sync + * ADDED: Shutdown method for SPI slave + * ADDED: SPI master optional MISO and SS timing adjustments + * ADDED: Array transfer method for SPI master sync + * FIXED: SPI slave MISO now goes Hi-Z when SS is deasserted + * FIXED: SPI master (all) swapping of SPI modes 0 and 1 + * FIXED: SPI master async non-functional SPI modes 1 and 2 + * FIXED: SPI slave swapping of SPI modes 0 and 1 + * FIXED: Passing NULL ptr to SPI asynch throws exception + * FIXED: Non-functional tests + * CHANGED: State diagrams and wavedrom now rendered by xmosdoc + * CHANGED: Examples AN00160 and AN00161 now integrated into main document as + app_spi_master and app_spi_slave examples + * REMOVED: Support for XS1 devices + +3.4.0 +----- + + * CHANGED: Refresh to use latest doc builder and library format + * ADDED: Support for XCommon CMake build system + * REMOVED: XCORE-200 targets in examples (now targets XK-EVK-XU316) 3.3.0 ----- diff --git a/Jenkinsfile b/Jenkinsfile index c19ede0..161b69c 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -1,193 +1,122 @@ -@Library('xmos_jenkins_shared_library@v0.16.4') _ +// This file relates to internal XMOS infrastructure and should be ignored by external users + +@Library('xmos_jenkins_shared_library@v0.42.0') _ getApproval() pipeline { agent none + parameters { + choice(name: 'TEST_LEVEL', choices: ['smoke', 'default', 'extended'], + description: 'The level of test coverage to run' + ) string( name: 'TOOLS_VERSION', - defaultValue: '15.1.1', - description: 'The tools version to build with (check /projects/tools/ReleasesTools/)' + defaultValue: '15.3.1', + description: 'The XTC tools version' + ) + string( + name: 'XMOSDOC_VERSION', + defaultValue: 'v7.3.0', + description: 'The xmosdoc version' + ) + string( + name: 'INFR_APPS_VERSION', + defaultValue: 'v3.1.1', + description: 'The infr_apps version' ) } + + options { + buildDiscarder(xmosDiscardBuildSettings()) + skipDefaultCheckout() + timestamps() + } + stages { - stage('Standard build and XS1/2 tests') { + stage('🏗️ Build and test') { agent { - label 'x86_64&&brew' + label 'x86_64 && linux && documentation' } - environment { - REPO = 'lib_spi' - VIEW = getViewName(REPO) - } - options { - skipDefaultCheckout() - } stages { - stage('Get view') { + stage('Checkout') { steps { - xcorePrepareSandbox("${VIEW}", "${REPO}") - } - } - stage('Library checks') { - steps { - xcoreLibraryChecks("${REPO}") - } - } - stage('Legacy tests') { - steps { - dir("${REPO}/legacy_tests") { - viewEnv() { - // Use Pipfile in legacy_tests, not lib_spi/Pipfile - installPipfile(true) - runPython("./runtests.py --junit-output=${REPO}_tests.xml") - } + println "Stage running on ${env.NODE_NAME}" + script { + def (server, user, repo) = extractFromScmUrl() + env.REPO_NAME = repo } - } - } - stage('Build XCOREAI') { - steps { - dir("${REPO}") { - forAllMatch("examples", "AN*/") { path -> - runXmake(path, '', 'XCOREAI=1') - dir(path) { - stash name: path.split("/")[-1], includes: 'bin/*, ' - } - } - stash name: "reset_xtags", includes: "**/python/reset_xtags.py" - - // Build Tests - dir('legacy_tests/') { - script { - tests = [ - "spi_master_async_multi_client", - "spi_master_async_multi_device", - "spi_master_async_rx_tx", - "spi_master_async_shutdown", - "spi_master_sync_benchmark", - "spi_master_sync_clock_port_sharing", - "spi_master_sync_multi_client", - "spi_master_sync_multi_device", - "spi_master_sync_rx_tx", - "spi_slave_benchmark", - "spi_slave_rx_tx" - ] - tests.each() { - dir(it) { - //Build all tests tagetting XS3 to check for build errors only - runXmake(".", "", "XCOREAI=1") - stash name: it, includes: 'bin/**/*.xe, ' - } - } - } - } + dir(REPO_NAME){ + checkoutScmShallow() } } } - }//stages - post { - cleanup { - xcoreCleanSandbox() - } - } - }//stage - Standard build and XS1/2 tests - stage('Documentation'){ - agent{ - label 'x86_64&&brew&&macOS' - } - environment { - REPO = 'lib_spi' - VIEW = getViewName(REPO) - } - stages{ - stage('Get view') { + stage('Examples build') { steps { - xcorePrepareSandbox("${VIEW}", "${REPO}") + dir("${REPO_NAME}/examples") { + xcoreBuild() + } } } - stage('Builds') { + + stage('Repo checks') { steps { - forAllMatch("${REPO}/examples", "AN*/") { path -> - runXdoc("${path}/doc") + warnError("Repo checks failed") + { + runRepoChecks("${WORKSPACE}/${REPO_NAME}") } - runXdoc("${REPO}/${REPO}/doc") - - // Archive all the generated .pdf docs - archiveArtifacts artifacts: "${REPO}/**/pdf/*.pdf", fingerprint: true, allowEmptyArchive: true } } - } - post { - cleanup { - xcoreCleanSandbox() - } - } - } - stage('xcore.ai Verification'){ - agent { - label 'xcore.ai-explorer' - } - environment { - // '/XMOS/tools' from get_tools.py and rest from tools installers - TOOLS_PATH = "/XMOS/tools/${params.TOOLS_VERSION}/XMOS/XTC/${params.TOOLS_VERSION}" - } - stages{ - stage('Install Dependencies') { + stage('Doc build') { steps { - sh '/XMOS/get_tools.py ' + params.TOOLS_VERSION - installDependencies() + dir(REPO_NAME) { + buildDocs() + } } } - stage('Reset XTAGs'){ - steps{ - toolsEnv(TOOLS_PATH) { // load xmos tools - unstash "reset_xtags" - sh 'rm -f ~/.xtag/acquired' //Hacky but ensure it always works even when previous failed run left lock file present - withVenv{ - sh "python -m pip install git+git://github0.xmos.com/xmos-int/xtagctl.git@v1.3.1" - sh "python python/reset_xtags.py 2" //Note 2 xtags to reset on xcore.ai-explorer - } + + stage('Tests') { + steps { + withTools(params.TOOLS_VERSION) { + dir("${REPO_NAME}/tests") { + createVenv(reqFile: "requirements.txt") + xcoreBuild() + withVenv{ + runPytest("--numprocesses=auto --testlevel=${params.TEST_LEVEL}") + } + } // dir + } // withTools + } // steps + post { + always { + archiveArtifacts artifacts: "${REPO_NAME}/tests/logs/*.txt", fingerprint: true, allowEmptyArchive: true } } } - stage('xrun'){ - steps{ - toolsEnv(TOOLS_PATH) { // load xmos tools - forAllMatch("examples", "AN*/") { path -> - unstash path.split("/")[-1] - } - // Run the tests and look for what we expect - sh 'xrun --io --id 0 bin/AN00160_using_SPI_master.xe &> AN00160_using_SPI_master.txt' - // Look for config register 0 value from wifi module - sh 'grep 2005400 AN00160_using_SPI_master.txt' - //Just run this and ensure we get no error (like wrong arch). We have no SPI master HW so cannot test it - sh 'xrun --id 0 bin/AN00161_using_SPI_slave.xe' - } + stage("Archive sandbox") { + steps { + archiveSandbox(REPO_NAME) } } - }//stages + } // stages + post { cleanup { - cleanWs() + xcoreCleanSandbox() } } - }// xcore.ai + } // stage build and test - stage('Update view files') { - agent { - label 'x86_64&&brew' - } - when { - expression { return currentBuild.currentResult == "SUCCESS" } - } + stage('🚀 Release') { steps { - updateViewfiles() + triggerRelease() } } - }//stages -}//pipeline + } // stages +} // pipeline diff --git a/README.rst b/README.rst index a06322a..ad5c63d 100644 --- a/README.rst +++ b/README.rst @@ -1,38 +1,68 @@ -SPI Library -=========== +:orphan: -Summary -------- +#################### +lib_spi: SPI library +#################### + +:vendor: XMOS +:version: 4.0.0 +:scope: General Use +:description: SPI Master and Slave components +:category: General Purpose +:keywords: SPI +:devices: xcore-200, xcore.ai -A software defined, industry-standard, SPI (serial peripheral -interface) component -that allows you to control an SPI bus via the -xCORE GPIO hardware-response ports. SPI is a four-wire hardware -bi-directional serial interface. +******* +Summary +******* -The SPI bus can be used by multiple tasks within the xCORE device -and (each addressing the same or different slaves) and -is compatible with other slave devices on the same bus. +SPI is a four-wire hardware bi-directional serial interface. +This library provides a software defined, industry-standard, SPI (serial peripheral +interface) component that allows control a SPI bus via the `xcore` GPIO ports. +******** Features -........ +******** + +* SPI master and SPI slave modes. +* Supports speed of up to 75 Mbit. +* Multiple slave device support +* All clock polarity and phase configurations supported. + +************ +Known issues +************ - * SPI master and SPI slave modes. - * Supports speed of up to 100 Mbit. - * Multiple slave device support - * All clock polarity and phase configurations supported. +* None +**************** +Development repo +**************** -Software version and dependencies -................................. +* `lib_spi `_ -The CHANGELOG contains information about the current and previous versions. -For a list of direct dependencies, look for DEPENDENT_MODULES in lib_spi/module_build_info. +************** +Required tools +************** +* XMOS XTC Tools: 15.3.1 + +********************************* +Required libraries (dependencies) +********************************* + +* None + +************************* Related application notes -......................... +************************* + +Please see `examples` section of user guide for SPI slave and SPI master examples. + -The following application notes use this library: +******* +Support +******* - * AN00160 - How to communicate as SPI master - * AN00161 - How to communicate as SPI slave +This package is supported by XMOS Ltd. Issues can be raised against the software at +`www.xmos.com/support `_ diff --git a/doc/Doxyfile.inc b/doc/Doxyfile.inc new file mode 100644 index 0000000..12418ea --- /dev/null +++ b/doc/Doxyfile.inc @@ -0,0 +1,8 @@ +# This file provides overrides to the Doxyfile configuration + +PROJECT_NAME = lib_spi +PROJECT_BRIEF = "SPI Library" + +INPUT = ../lib_spi/api + +PREDEFINED = C_API= EXTERN_C= slave= __DOXYGEN__=1 diff --git a/doc/exclude_patterns.inc b/doc/exclude_patterns.inc new file mode 100644 index 0000000..a36136a --- /dev/null +++ b/doc/exclude_patterns.inc @@ -0,0 +1,10 @@ +# The following patterns are to be excluded from the documentation build + +**CHANGELOG* +**LICENSE* +**.pytest_cache/* +#TODO remove these +**index* +**resource_usage_summary* +**app_spi_master* +**app_spi_slave* diff --git a/doc/images/spi_master_connect.odg b/doc/images/spi_master_connect.odg new file mode 100644 index 0000000..f77d0ee Binary files /dev/null and b/doc/images/spi_master_connect.odg differ diff --git a/doc/images/spi_master_connect.svg b/doc/images/spi_master_connect.svg new file mode 100644 index 0000000..b74df56 --- /dev/null +++ b/doc/images/spi_master_connect.svg @@ -0,0 +1,924 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + xCORE device + + + + + + + + + + + + SCLK + + + + + + + + 1 bitport + + + + + + + + + + + + MOSI + + + + + + + + 1 bitport + + + + + + + + + + + + MISO + + + + + + + + 1 bitport + + + + + + + + + + + + SS0 + + + + + + + + + + + + SSn + + + + + + + + Anyport + + + + + + ... + + + + + + + + diff --git a/lib_spi/doc/rst/images/spi_master_task_diag.odg b/doc/images/spi_master_task_diag.odg similarity index 100% rename from lib_spi/doc/rst/images/spi_master_task_diag.odg rename to doc/images/spi_master_task_diag.odg diff --git a/doc/images/spi_master_task_diag.svg b/doc/images/spi_master_task_diag.svg new file mode 100644 index 0000000..94e821d --- /dev/null +++ b/doc/images/spi_master_task_diag.svg @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + + + + + +SPI +master + + + + +SPI +master + + + + +app + + + + +app + + +spi_master_if + + + + + diff --git a/lib_spi/doc/rst/images/spi_slave_connect.odg b/doc/images/spi_slave_connect.odg similarity index 100% rename from lib_spi/doc/rst/images/spi_slave_connect.odg rename to doc/images/spi_slave_connect.odg diff --git a/doc/images/spi_slave_connect.svg b/doc/images/spi_slave_connect.svg new file mode 100644 index 0000000..42ac8cd --- /dev/null +++ b/doc/images/spi_slave_connect.svg @@ -0,0 +1,807 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + xCORE device + + + + + + + + + + + + SCLK + + + + + + + + 1 bitport + + + + + + + + + + + + MOSI + + + + + + + + 1 bitport + + + + + + + + + + + + MISO + + + + + + + + 1 bitport + + + + + + + + + + + + SS + + + + + + + + 1 bitport + + + + + + + + diff --git a/doc/images/spi_slave_example_block_diagram.png b/doc/images/spi_slave_example_block_diagram.png new file mode 100644 index 0000000..8b17d42 Binary files /dev/null and b/doc/images/spi_slave_example_block_diagram.png differ diff --git a/doc/images/spi_slave_simulation.png b/doc/images/spi_slave_simulation.png new file mode 100644 index 0000000..52ceb2d Binary files /dev/null and b/doc/images/spi_slave_simulation.png differ diff --git a/lib_spi/doc/rst/images/spi_slave_task_diag.odg b/doc/images/spi_slave_task_diag.odg similarity index 100% rename from lib_spi/doc/rst/images/spi_slave_task_diag.odg rename to doc/images/spi_slave_task_diag.odg diff --git a/doc/images/spi_slave_task_diag.svg b/doc/images/spi_slave_task_diag.svg new file mode 100644 index 0000000..0e86af1 --- /dev/null +++ b/doc/images/spi_slave_task_diag.svg @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + + + + + +SPI +slave + + + + +SPI +slave + + + + +app + + + + +app + + +spi_slave_callback_if + + + + + diff --git a/doc/images/wavedrom_mode0.js b/doc/images/wavedrom_mode0.js new file mode 100644 index 0000000..d01932f --- /dev/null +++ b/doc/images/wavedrom_mode0.js @@ -0,0 +1,9 @@ +{ signal: [ + {name: 'CLK', wave: '0...10101|010...', node: '....B......C......'}, + {name: 'MOSI', wave: 'x..2.2.2.|2.x...', data: ['MSB', '', '', 'LSB'] }, + {name: 'MISO', wave: 'x..2.2.2.|2.x...', data: ['MSB', '', '', 'LSB'], node: '...................' }, + {name: 'SS', wave: '10.......|...1.0', node: '.A...........D.E..'}, + { node: '.a..b......c.d.e.' } +], + edge: [ 'A|a','B|b','C|c','D|d', 'E|e' ,'a<->b t1','c<->d t2', 'd<->e t3' ] +} \ No newline at end of file diff --git a/doc/images/wavedrom_mode1.js b/doc/images/wavedrom_mode1.js new file mode 100644 index 0000000..8dce71e --- /dev/null +++ b/doc/images/wavedrom_mode1.js @@ -0,0 +1,9 @@ +{ signal: [ + {name: 'CLK', wave: '0..101010|10....', node: '....B......C......'}, + {name: 'MOSI', wave: 'x..2.2.2.|2.x...', data: ['MSB', '', '', 'LSB'] }, + {name: 'MISO', wave: 'x..2.2.2.|2.x...', data: ['MSB', '', '', 'LSB'], node: '...................' }, + {name: 'SS', wave: '10.......|...1.0', node: '.A...........D.E..'}, + { node: '.a..b......c.d.e.' } +], + edge: [ 'A|a','B|b','C|c','D|d', 'E|e' ,'a<->b t1','c<->d t2', 'd<->e t3' ] +} \ No newline at end of file diff --git a/doc/images/wavedrom_mode2.js b/doc/images/wavedrom_mode2.js new file mode 100644 index 0000000..a0bb5ad --- /dev/null +++ b/doc/images/wavedrom_mode2.js @@ -0,0 +1,9 @@ +{ signal: [ + {name: 'CLK', wave: '1...01010|101...', node: '....B......C......'}, + {name: 'MOSI', wave: 'x..2.2.2.|2.x...', data: ['MSB', '', '', 'LSB'] }, + {name: 'MISO', wave: 'x..2.2.2.|2.x...', data: ['MSB', '', '', 'LSB'], node: '....................' }, + {name: 'SS', wave: '10.......|...1.0', node: '.A...........D.E..'}, + { node: '.a..b......c.d.e' } +], + edge: [ 'A|a','B|b','C|c','D|d','E|e','a<->b t1','c<->d t2', 'd<->e t3' ] +} \ No newline at end of file diff --git a/doc/images/wavedrom_mode3.js b/doc/images/wavedrom_mode3.js new file mode 100644 index 0000000..dc354a5 --- /dev/null +++ b/doc/images/wavedrom_mode3.js @@ -0,0 +1,9 @@ +{ signal: [ + {name: 'CLK', wave: '1..010101|01.....', node: '....B......C.......'}, + {name: 'MOSI', wave: 'x..2.2.2.|2.x....', data: ['MSB', '', '', 'LSB'] }, + {name: 'MISO', wave: 'x..2.2.2.|2.x....', data: ['MSB', '', '', 'LSB'], node: '....................' }, + {name: 'SS', wave: '10.......|...1.0.', node: '.A...........D.E..'}, + { node: '.a..b......c.d.e.' } +], + edge: [ 'A|a','B|b','C|c','D|d','E|e', 'a<->b t1','c<->d t2', 'd<->e t3' ] +} \ No newline at end of file diff --git a/doc/rst/lib_spi.rst b/doc/rst/lib_spi.rst new file mode 100644 index 0000000..f0dc94f --- /dev/null +++ b/doc/rst/lib_spi.rst @@ -0,0 +1,1441 @@ +#################### +lib_spi: SPI library +#################### + +************ +Introduction +************ + +SPI is a four-wire hardware bi-directional serial interface. +This library provides a software defined, industry-standard, SPI (serial peripheral +interface) component that allows you to control an SPI bus via the +``xcore`` GPIO ports. + +The SPI bus can be used by multiple tasks within the ``xcore`` device +and (each addressing the same or different slaves) and +is compatible with other slave devices on the same bus. + +|newpage| + +************************ +Available SPI components +************************ + +Three components are provided in this library which offer different functionality. +They are all defined as a task with an interface which provides methods for transmitting +and receiving data. All components offer a `shutdown()` method allowing the component +to be exited at runtime which frees any resources used. + +SPI Master (Synchronous) +======================== + +This component is the standard SPI master and is simplest to use. The `synchronous` aspect refers to the API and operation and +means that calls to this component block until the transaction has completed. The component +server may be placed on the same or a different tile from the client. If placed on the same +tile, the task may be `distributed` by the compiler which means it gets turned into a function +call and consequently does not consume an ``xcore`` thread. + +Multiple clients are supported and are arbitrated by the component. Multiple devices are also +supported by means of individual slave select bits within a port. + +SPI Master (Asynchronous) +========================= + +This component offers buffering functionality over the `synchronous` SPI master. +The `asynchronous` feature means that calls to this component can be non-blocking and SPI transfers +may be queued. The component server may be placed on the same or a different tile from the client. + +Due to the buffering logic, the `asynchronous` version always consumes an ``xcore`` thread. + +Multiple clients are supported and are arbitrated by the component. Multiple devices are also +supported by means of individual slave select bits within a port. + +SPI Slave +========= + +The SPI slave component task always runs in its own ``xcore`` thread because it needs to be +responsive to the external master requests. It offers a single slave device with basic +8 or 32 bit transfer support. +It provides callbacks for when the slave needs data to transmit or has received data, as +well as a callback to indicate the end of a transaction. + + +|newpage| + +********* +SPI Modes +********* + +The data sample points for SPI are defined by the clock polarity (CPOL) and clock phase (CPHA) +parameters. SPI clock polarity may be inverted or non-inverted by the CPOL and the CPHA parameter +is used to shift the sampling phase. The following four sections illustrate the MISO and MOSI data lines +relative to the clock. The timings are given by: + +.. list-table:: SPI timings + :header-rows: 1 + :class: vertical-borders horizontal-borders + + * - Parameter + - Description + * - *t1* + - The minimum time from the start of the transaction (SS asserted) to the first sample point/active clock edge. + * - *t2* + - The minimum amount of time from the last sample point/active clock before SS is de-asserted. + * - *t3* + - The inter-transmission gap. This is the minimum amount of time that the slave select must be de-asserted between accesses on the same device. + * - *MAX CLOCK RATE* + - This is the maximum clock rate supported by the configuration. + +The setup and hold timings are inherited from the underlying ``xcore`` +device. For details on these timing please refer to the device datasheet. + +When operating above 20 Mbps please also see the :ref:`MISO port timing` section. + +Mode 0 - CPOL: 0 CPHA 0 +======================= + +.. wavedrom:: ../images/wavedrom_mode0.js + :caption: Mode 0 + :width: 100% + :align: center + +The master and slave will drive out their first data bit before the first rising edge of the clock then drive on subsequent falling edges. They will sample on rising edges. + +Mode 1 - CPOL: 0 CPHA 1 +======================= + +.. wavedrom:: ../images/wavedrom_mode1.js + :caption: Mode 1 + :width: 100% + :align: center + + +The master and slave will drive out their first data bit on the first rising edge of the clock and sample on the subsequent falling edge. + +Mode 2 - CPOL: 1 CPHA 0 +======================= + +.. wavedrom:: ../images/wavedrom_mode2.js + :caption: Mode 2 + :width: 100% + :align: center + +The master and slave will drive out their first data bit before the first falling edge of the clock then drive on subsequent rising edges. They will sample on falling edges. + + +Mode 3 - CPOL: 1 CPHA 1 +======================= + +.. wavedrom:: ../images/wavedrom_mode3.js + :caption: Mode 3 + :width: 100% + :align: center + +The master and slave will drive out their first data bit on the first falling edge of the clock and sample on the subsequent rising edge. + +|newpage| + +*************************** +External signal description +*************************** + +The SPI protocol requires a clock, one or more slave selects +and either one or two data wires. + +.. _spi_wire_table: + +.. list-table:: SPI data wires + :header-rows: 1 + :class: vertical-borders horizontal-borders + + * - Signal + - Description + * - *SCLK* + - Clock line, driven by the master + * - *MOSI* + - Master Output, Slave Input data line, driven by the master + * - *MISO* + - Master Input, Slave Output data line, driven by the slave + * - *SS* + - Slave select line, driven by the master + +During any transfer of data, the master will assert the *SS* +line and then output a series of transitions on the *SCLK* +wire. During this time, the slave will drive data to be sampled by the +master and the master will drive data to be sampled by the slave. At +the end of the transfer, the *SS* is de-asserted. + +If the slave select line is not driven high then the slave should +ignore any transitions on the other lines. + +|newpage| + + +************************************** +Connecting to the ``xcore`` SPI master +************************************** + +The SPI wires need to be connected to the ``xcore`` device as shown in +:numref:`spi_master_xcore_connect`. The signals can be connected to any +one bit ports, with the exception of slave select which may be any width +port. All ports must be on the same tile. + +.. _spi_master_xcore_connect: + +.. figure:: ../images/spi_master_connect.* + :width: 40% + + SPI master connection to the ``xcore`` device + +If only one data direction is required then the *MOSI* or *MISO* line +need not be connected. However, **asynchronous mode is only supported +if the MISO line is connected**. + +The master component of this library supports multiple slaves on unique +slave select wires. The bit of the port used for each device is configurable +and so multiple slaves may share the same select bit if needed. + + +Disabling master data lines +=========================== + +The *MOSI* and *MISO* parameters of the ``spi_master()`` task are +optional. So in the top-level ``par`` statement the function can be +called with ``null`` instead of a port e.g. + +.. code-block:: C + + spi_master(i_spi, 1, p_sclk, null, p_miso , p_ss, 1, clk_spi); + + +Similarly, the *MOSI* parameter of the ``spi_master_async()`` task is +optional (but the *MISO* port must be provided). + +|newpage| + + +************************************* +Connecting to the ``xcore`` SPI slave +************************************* + +The SPI wires need to be connected to the ``xcore`` device as shown in +:numref:`spi_slave_xcore_connect`. The signals can be connected to any +one bit ports on the device. + +.. _spi_slave_xcore_connect: + +.. figure:: ../images/spi_slave_connect.* + :width: 40% + + SPI slave connection to the ``xcore`` device + +The slave will only send and receive data when the slave select is +driven high. Additionally the *MISO* line is set to high impedance +when not in use. + +If the *MISO* line is not required then it need not be connected. The +*MOSI* line must always be connected. + +Disabling slave data lines +========================== + +The ``spi_slave()`` task has an optional *MISO* parameter (but the +*MOSI* port must be supplied). + + +|newpage| + +************ +Master Usage +************ + +SPI master synchronous operation +================================ + +There are two types of interface for SPI master components: +synchronous and asynchronous. + +The synchronous API provides blocking operation. Whenever a client makes a +read or write call the operation will complete before the client can +move on - this will occupy the core that the client code is running on +until the end of the operation. This method is easy to use, has low +resource use and is very suitable for applications such as setup and +configuration of attached peripherals. + +SPI master components are instantiated as parallel tasks that run in a +``par`` statement. For synchronous operation, the application can +connect via an interface connection using the ``spi_master_if`` interface type: + +.. figure:: ../images/spi_master_task_diag.* + + SPI master task diagram + +For example, the following code instantiates an SPI master component +and connect to it. + +.. code-block:: C + + out buffered port:32 p_miso = XS1_PORT_1A; + out port p_ss = XS1_PORT_1B; + out buffered port:22 p_sclk = XS1_PORT_1C; + out buffered port:32 p_mosi = XS1_PORT_1D; + clock clk_spi = XS1_CLKBLK_1; + + int main(void) { + spi_master_if i_spi[1]; + par { + spi_master(i_spi, 1, p_sclk, p_mosi, p_miso , p_ss, 1, clk_spi); + my_application(i_spi[0]); + } + return 0; + } + +.. note:: The connection is an array of interfaces, so several tasks + can connect to the same component instance. The slave select ports are + also an array since the same SPI data lines can connect to several + devices via different slave lines. + +The final parameter of the ``spi_master()`` task is an optional clock +block. If the clock block is supplied then the maximum transfer rate +of the SPI bus is increased (see :numref:`spi_master_sync_timings`). If +``null`` is supplied instead then the performance is lower but no clock +block is used. + +The application can use the client end of the interface connection to +perform SPI bus operations e.g. + +.. code-block:: C + + void my_application(client spi_master_if spi) { + uint8_t val; + printf("Doing one byte transfer. Sending 0x22.\n"); + spi.begin_transaction(0, 100, SPI_MODE_0); + val = spi.transfer8(0x22); + spi.end_transaction(1000); + printf("Read data %d from the bus.\n", val); + } + + +Here, ``begin_transaction`` selects the device ``0`` and asserts its +slave select line. The application can then transfer data to and from +the slave device and finish with ``end_transaction``, which de-asserts +the slave select line. + +Operations such as ``spi.transfer8`` will +block until the operation is completed on the bus. +More information on interfaces and tasks can be be found in +the `XMOS Programming Guide `_. By default the +SPI synchronous master mode component does not use any ``xcore`` threads of its +own. It is a *distributed* task which means it will perform its +function on the ``xcore`` thread of the application task connected to +it (provided the application task is on the same tile). + +Synchronous master usage state machine +...................................... + +The function calls made on the SPI master interface must follow the +sequence shown by the state machine in :numref:`spi_master_usage_state_machine`. +If this sequence is not followed then the behaviour is undefined. + +.. _spi_master_usage_state_machine: + +.. uml:: + :width: 60% + :caption: SPI master use state machine (synchronous) + + @startuml + title SPI master use state machine (synchronous) + + [*] --> begin_transaction + + begin_transaction --> transfer8 + begin_transaction --> transfer32 + transfer8 --> transfer8 + transfer8 --> transfer32 + transfer8 --> end_transaction + transfer32 --> transfer8 + transfer32 --> transfer32 + transfer32 --> end_transaction + end_transaction --> begin_transaction + begin_transaction --> end_transaction + + begin_transaction --> [*] : shutdown + transfer8 --> [*] : shutdown + transfer32 --> [*] : shutdown + end_transaction --> [*] : shutdown + + @enduml + +|newpage| + + +SPI master asynchronous operation +================================= + +The synchronous API will block your application until the bus +operation is complete. In cases where the application cannot afford to +wait for this long, the asynchronous API can be used. + +The asynchronous API offloads operations to another task. Calls are +provided to initiate reads and writes and notifications are provided +when the operation completes. This API requires more management in the +application but can provide much more efficient operation. + +It is particularly suitable for applications where the SPI bus is +being used for continuous data transfer. + +Setting up an asynchronous SPI master component is done in the same +manner as the synchronous component. + +.. code-block:: C + + out buffered port:32 p_miso = XS1_PORT_1A; + out port p_ss = XS1_PORT_1B; + out buffered port:22 p_sclk = XS1_PORT_1C; + out buffered port:32 p_mosi = XS1_PORT_1D; + + clock cb = XS1_CLKBLK_1; + + int main(void) { + spi_master_async_if i_spi[1]; + par { + spi_master_async(i_spi, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb); + my_application(i_spi[0]); + } + return 0; + } + + +|newpage| + +The application can use the asynchronous API to offload bus +operations to the component. This is done by moving pointers to the +SPI slave task to transfer and then retrieving pointers when the +operation is complete. For example, the following code +repeatedly calculates 100 bytes to send over the bus and handles 100 +bytes coming back from the slave. + +.. code-block:: C + + void my_application(client spi_master_async_if spi) { + uint8_t outdata[100]; + uint8_t indata[100]; + uint8_t * movable buf_in = indata; + uint8_t * movable buf_out = outdata; + + // create and send initial data + fill_buffer_with_data(outdata); + spi.begin_transaction(0, 1000, SPI_MODE_0); + spi.init_transfer_array_8(move(buf_in), move(buf_out), 100); + while (1) { + select { + case spi.transfer_complete(): + spi.retrieve_transfer_buffers_8(buf_in, buf_out); + spi.end_transaction(); + + // Handle the data that has come in + handle_incoming_data(buf_in); + // Calculate the next set of data to go + fill_buffer_with_data(buf_out); + + spi.begin_transaction(0, 100, SPI_MODE_0); + spi.init_transfer_array_8(move(buf_in), move(buf_out)); + break; + } + } + } + + +The SPI asynchronous task is combinable so can be run on a logical +core with other tasks (including the application task it is connected to). + +|newpage| + +Asynchronous master command buffering +..................................... + +In order to provide asynchronous behaviour for multiple clients the asynchronous master +will store up to one ``begin_transaction`` and one ``init_transfer_array_8`` or +``init_transfer_array_32`` from each client. This means that if the +master is busy doing a transfer for client *X*, then client *Y* will +still be able to begin a transaction and send data fully +asynchronously. Consequently, after client *Y* has issued +``init_transfer_array_8`` or ``init_transfer_array_32`` it will be +able to continue operation whilst waiting for the notification. + +Asynchronous master usage state machine +....................................... + +The function calls made on the SPI master asynchronous interface must follow the +sequence shown by the state machine in :numref:`spi_master_usage_state_machine_async`. +If this sequence is not followed then the behaviour is undefined. + +.. _spi_master_usage_state_machine_async: + +.. uml:: + :caption: SPI master use state machine (asynchronous) + :width: 60% + + @startuml + title SPI master use state machine (asynchronous) + + [*] --> begin_transaction + begin_transaction --> init_transfer_array_8 + begin_transaction --> init_transfer_array_32 + init_transfer_array_8 --> transfer_complete + init_transfer_array_32 --> transfer_complete + transfer_complete --> retrieve_transfer_buffers_8 + transfer_complete --> retrieve_transfer_buffers_32 + retrieve_transfer_buffers_8 --> retrieve_transfer_buffers_8 + retrieve_transfer_buffers_8 --> retrieve_transfer_buffers_32 + retrieve_transfer_buffers_8 --> end_transaction + retrieve_transfer_buffers_32 --> retrieve_transfer_buffers_8 + retrieve_transfer_buffers_32 --> retrieve_transfer_buffers_32 + retrieve_transfer_buffers_32 --> end_transaction + end_transaction --> begin_transaction + begin_transaction --> end_transaction + end_transaction --> [*] : shutdown + + @enduml + + + +Master inter-transaction gap +============================ + +For both synchronous and asynchronous modes the ``end_transaction`` requires a +slave select de-assert time. This parameter will provide a minimum de-assert time between +two transaction on the same slave select. In the case where a ``begin_transaction`` +asserting the slave select would violate the previous ``end_transaction`` then the +``begin_transaction`` will block until the slave select de-assert time has been +satisfied. + +|newpage| + + +*********** +Slave usage +*********** + +SPI slave components are instantiated as parallel tasks that run in a +``par`` statement. The application can connect via an interface +connection. + +.. figure:: ../images/spi_slave_task_diag.svg + + SPI slave task diagram + +For example, the following code instantiates an SPI slave component +and connect to it. + +.. code-block:: C + + out buffered port:32 p_miso = XS1_PORT_1E; + in port p_ss = XS1_PORT_1F; + in port p_sclk = XS1_PORT_1G; + in buffered port:32 p_mosi = XS1_PORT_1H; + clock cb = XS1_CLKBLK_1; + + int main(void) { + interface spi_slave_callback_if i_spi; + par { + spi_slave(i_spi, p_sclk, p_mosi, p_miso, p_ss, cb, SPI_MODE_0, + SPI_TRANSFER_SIZE_8); + my_application(i_spi); + } + return 0; + } + + +When a slave component is instantiated the mode and transfer size +needs to be specified. If you wish to change mode or width, you can +shutdown the component and re-start it. + +|newpage| + +The slave component acts as the client of the interface +connection. This means it can "callback" to the application to respond +to requests from the bus master. For example, the following code +snippet shows part of an application that responds to SPI transactions +where the first word is a command to read or write command and +subsequent transfers either provide or consume data. + + +.. code-block:: C + + while (1) { + uint32_t command = 0; + size_t index = 0; + select { + case spi.master_requires_data() -> uint32_t data: + if (command == 0) { + // Not got the command yet. This will be the + // first word of the transaction. + data = 0; + } else if (command == READ_COMMAND) { + data = get_read_data_item(index); + index++; + } else { + data = 0; + } + break; + case spi.master_supplied_data(uint32_t data, uint32_t valid_bits): + if (command == 0) { + command = data; + } else if (command == WRITE_COMMAND) { + handle_write_data_item(data, index); + index++; + } + break; + case spi.master_ends_transaction(): + // The master has de-asserted slave select. + command = 0; + index = 0; + break; + } + } + + +.. note:: + + The time taken to handle the callbacks will determine the + timing requirements of the SPI slave and so should be kept as short as possible. + See the SPI slave example in ``examples/app_spi_slave`` for more details on different ways of working with the SPI slave component. + +|newpage| + + +********************************* +SPI master timing characteristics +********************************* + +Synchronous SPI master clock speeds +=================================== + +The maximum speed that the SPI bus can be driven depends on whether a +clock block is used, the speed of the ``xcore`` thread that the SPI code +is running on and where both the *MISO* and *MOSI* lines are used. The +timings can be seen in :numref:`spi_master_sync_timings`. + +.. _spi_master_sync_timings: + +.. list-table:: SPI master timings (synchronous) + :header-rows: 1 + + * - Clock blocks + - MOSI enabled + - MISO enabled + - Max kbps (62.5 MHz core) + - Max kbps (100 MHz core) + * - 0 + - 1 + - 0 + - 2500 + - 3500 + * - 0 + - 1 + - 1 + - 1200 + - 1300 + * - 1 + - 1 + - 0 + - 62500 + - 75000 + * - 1 + - 1 + - 1 + - 62500 + - 75000 + + +Asynchronous SPI master clock speeds +==================================== + +The asynchronous SPI master uses the same transport layer as the SPI master using a clock block +and so achieves similar performance. + +.. list-table:: SPI master timings (asynchronous) + :header-rows: 1 + + * - Clock blocks + - MISO enabled + - MOSI enabled + - Max kbps (62.5 MHz core) + - Max kbps (100 MHz core) + * - 1 + - x + - x + - 62500 + - 75000 + +.. _miso_port_timing: + +MISO port timing +================ + +Port timing is affected by chip pad and PCB delays. For the clock, slave-select and MOSI signals, all of the delays will be broadly matched. +This means port timing adjustment is normally not required even up to the fastest supported SPI clock rates. + +For the MISO signal, there will be a 'round trip delay' starting with the clock edge output and finishing at the ``xcore``'s input port. +The presence of this delay will mean the ``xcore`` may sample too early since data signal will arrive later. +It may be necessary to delay the sampling of the MISO pin to capture within the required window, particularly if the SPI clock is above 20 MHz. + +Control over the signal capture is provided for all SPI master implementations that require a clock block. Please see the :ref:`API section` `spi_master_sync_timings()` method which exposes the controls available for optimising setup and hold capture. + +For details on how to calculate and adjust round-trip port timing, please consult the `IO timings for xcore.ai `_ or `IO timings for xCORE200 `_ document. + +|newpage| + +******************************** +SPI slave timing characteristics +******************************** + +The ``xcore`` thread running the SPI slave task will wait for the slave +select line to assert and then begin processing the transaction. At +this point it will call the ``master_requires_data`` callback to +application code. The time taken for the application to perform this +call will affect how long the ``xcore`` thread has to resume processing +SPI data. This will affect the minimum allowable time between slave +select changing and data transfer from the master (*t1*). + +The user of the library will need to determine this time based on their application. + +After slave select is de-asserted the SPI slave task will call the +``master_ends_transaction`` callback. The time the application takes +to process this will affect the minimum allowable inter-transmission +gap between transactions (*t2*). The user of the library will also need to +determine this time based on their application. + +If the SPI slave task is combined will other tasks running on the same +``xcore`` thread then the other task may process an event delaying the +time it takes for the SPI slave task to react to events. This will add +these delays to the minimum times for both *t1* and *t2*. The library +user will need to take these into account in determining the timing +restrictions on the master. + +.. note:: + + The time taken to handle the callbacks will determine the + timing requirements of the SPI slave, and so must be kept as short as possible. + + +Throughput for SPI slave versus mode and MOSI usage is shown in the following table. + +.. list-table:: SPI slave timings + :header-rows: 1 + + * - SPI Mode + - MOSI enabled + - Max kbps (62.5 MHz core) + - Max kbps (100 MHz core) + * - 0 + - 0 + - 40000 + - 62500 + * - 1 + - 0 + - 40000 + - 62500 + * - 2 + - 0 + - 40000 + - 62500 + * - 3 + - 0 + - 40000 + - 62500 + * - 0 + - 1 + - 7000 + - 10000 + * - 1 + - 1 + - 7000 + - 10000 + * - 2 + - 1 + - 7000 + - 10000 + * - 3 + - 1 + - 7000 + - 10000 + + +|newpage| + + +******** +Examples +******** + +SPI Master Example +================== + +Overview +........ + +The example uses the XMOS SPI library to perform some bus transactions as SPI master. The SPI master examples are run on the `xcore.ai` evaluation kit, `XK-EVK-XU316 `_ using the WFM200 WiFi device as a simple SPI slave. + +The application consists of two tasks: + + - A task that drives the SPI bus + + - An application task that connects to the SPI task + +These tasks communicate via the use of xC interfaces. Note that for the SPI `synchronous` cases, even though +the SPI master and app are separate tasks, the compiler is able to `distribute` the SPI master so that the +application only uses a single hardware thread. + +:numref:`spi_master_example` shows the task and communication structure of the application. + +.. _spi_master_example: + +.. uml:: + :width: 60% + :caption: Task diagram of SPI master example + + @startuml + left to right direction + circle app + circle SPI_master + app --> SPI_master : spi_master_if\nor\nspi_master_async_if + @enduml + +Declaring ports +............... + +The SPI library connects to external pins via ``xcore`` ports. In +``main.xc`` these are declared as variables of type ``port`` at the +start of the file: + +.. literalinclude:: ../../examples/app_spi_master/src/main.xc + :language: c + :start-at: p_sclk + :end-at: p_mosi + +.. note:: + + The slave select declaration is for a mulit-bit port. The pin in this + port that will be used as SPI SS set by ``spi.set_ss_port_bit(0, 1);`` + +How the ports (e.g. ``XS1_PORT_1I``) relate to external pins will +depend on the exact device being used. See the device datasheet for details. + +|newpage| + +The application main() function +............................... + +Below is the source code for the main function of this application, +which is taken from the source file ``main.xc`` + +.. literalinclude:: ../../examples/app_spi_master/src/main.xc + :language: c + :start-after: // SPI async main + :end-before: // end async main + +.. literalinclude:: ../../examples/app_spi_master/src/main.xc + :language: c + :start-after: // SPI sync main + :end-before: // end sync main + +Looking at this in more detail you can see the following: + + - The par functionality describes running two separate tasks in parallel + + - The ``spi_master()`` or ``spi_master_async()`` task drives the SPI bus and takes the ports it + will use as arguments. + + - The ``app()`` or ``app_async()`` task communicates to the SPI master task via the + shared interface argument ``i_spi`` or ``i_spi_async``. This is an array since the + SPI master task could connect to many other tasks (clients) in parallel. + +The app() task +.............. + +The ``app()`` task uses its interface connection to the SPI master +task to perform SPI transactions. It performs two transactions (each +transaction will assert the slave select line, transfer some data and then +de-assert the slave select line). The functions in the SPI master +interface can be found in the SPI library user guide. + +.. literalinclude:: ../../examples/app_spi_master/src/main.xc + :language: c + :start-at: void app + :end-at: spi.shutdown + +.. literalinclude:: ../../examples/app_spi_master/src/main.xc + :language: c + :start-at: void async_app + :end-at: spi.shutdown + + +.. note:: + + When ``begin_transaction`` is called the SPI device selected is determined + by the first argument. In this case it is ``0``. + This is the method that is used to communiate with multiple SPI + slave devices. The speed and mode of the SPI protocol is also set at + in the ``begin_transaction`` call. + +|newpage| + + + +Building +........ + +The following section assumes that the `XMOS XTC tools `_ has +been downloaded and installed (see `README` for required version). + +Installation instructions can be found `here `_. Particular +attention should be paid to the section `Installation of required third-party tools +`_. + +The application uses the `XMOS` build and dependency system, `xcommon-cmake `_. `xcommon-cmake` +is bundled with the `XMOS` XTC tools. It runs on the `xcore.ai` evaluation kit, `XK-EVK-XU316 `_. + +To configure the build, run the following from an XTC command prompt: + +.. code-block:: console + + cd examples + cd app_spi_master + cmake -G "Unix Makefiles" -B build + +Any missing dependencies will be downloaded by the build system at this configure step. + + +Finally, the application binaries can be built using ``xmake``: + +.. code-block:: console + + xmake -j -C build + +Multiple build profiles are included and will be built as follows: + +* ASYNC - Example of using the `asynchronous` SPI master +* SYNC - Example of using the `synchronous` SPI master with clock-block (high performance) +* SYNC_NO_CLKBLK - Example of using the `synchronous` SPI master without clock-block (low performance / low resource usage) + +The build profiles are guarded by the defines `SPI_USE_ASYNC=1` for specifying the asynchronous SPI master and `CLKBLK=null` +when using the synchronous SPI master which determines which underlying SPI master transport to use. + +Running +....... + +To run the application return to the ``/examples/app_spi_master`` directory and run the following +command: + +.. code-block:: console + + xrun --xscope bin/SYNC/app_spi_master_SYNC.xe + +As application runs that reads a value from the SPI connected WiFi chip and prints the following output to the console:: + + Sending SPI traffic + 5400 + Done. + +The value `5400` represents bits 15 to 0 of the default value of the CONFIG register of the WFM200. + +Likewise, the following two commands should yield the same console output: + +.. code-block:: console + + xrun --xscope bin/SYNC/app_spi_master_SYNC_NO_CLKBLK.xe + xrun --xscope bin/SYNC/app_spi_master_ASYNC.xe + + +|newpage| + + +SPI Slave Example +================= + +Overview +........ + +The example in this application note uses the XMOS SPI library to +act as SPI slave. It maintains a register file which can be read and +written by the internal application *or* by the master on the SPI bus. +To show the bus functioning the demo application also has a tester +component connected to an SPI master bus which is connected (in +simulation) to the the SPI slave, using the simulator loopback plug-in. +This allows generation of SPI traffic to show the communication functioning. + +The application consists of five tasks: + + - A task that controls the SPI slave ports + + - A task that implements the register file handling calls from the + SPI slave component and the application + + - An application task that connects to the register file task + + - A task that controls the SPI master ports used for testing + + - A tester task that outputs commands to the SPI master task + +:numref:`spi_slave_example_block` shows the task and communication structure of the application. + +.. _spi_slave_example_block: + +.. figure:: ../images/spi_slave_example_block_diagram.png + :width: 90% + :align: center + + Block diagram of SPI slave application example + + +These tasks communicate via the use of xC interfaces. :numref:`spi_slave_example_task` shows +the task and communication structure of the application. + +.. _spi_slave_example_task: + +.. uml:: + :width: 60% + :caption: Task diagram of SPI slave example + + @startuml + circle tester + circle SPI_master + circle app + circle reg_file + circle SPI_slave + + ' Force layout order with hidden links + SPI_master -[hidden]-> SPI_slave + + ' Actual displayed nodes + tester -r-> SPI_master : spi_master_if + SPI_slave -r-> reg_file : spi_slave_callback_if + app -l-> reg_file : reg_if + @enduml + + +Declaring ports +............... + +The SPI library connects to external pins via ``xcore`` ports. In +``main.xc`` these are declared as variables of type ``port`` at the +start of the file: + +.. literalinclude:: ../../examples/app_spi_slave/src/main.xc + :language: c + :start-at: p_sclk + :end-at: clock + +.. note:: + + There is also a clock declaration since the slave needs to use an internal clock as well as ports inside the ``xcore`` device. + +How the ports (e.g. ``XS1_PORT_1I``) relate to external pins will +depend on the exact device being used. See the device datasheet for details. + +This application also has an SPI master interface on different ports: + +.. literalinclude:: ../../examples/app_spi_slave/src/main.xc + :language: c + :start-at: p_test_sclk + :end-at: p_test_mosi + +|newpage| + +The application main() function +............................... + +Below is the source code for the main function of this application, +which is taken from the source file ``main.xc`` + +.. literalinclude:: ../../examples/app_spi_slave/src/main.xc + :language: c + :start-at: int main + +Looking at this in a more detail you can see the following: + + - The par functionality describes running five separate tasks in + parallel; three are for the main application and two are for the + tester. + + - The ``spi_slave()`` task controls the application + SPI bus and takes the ports it will use as arguments. + + - The ``reg_file()`` task is connected to the ``app()`` task and the + ``spi_slave()`` task. + + - The ``spi_slave()`` task has an argument for the mode it expects - + in this case Mode 0 (see the SPI library user guide for more + details on modes) + + - The ``spi_slave()`` task also has an argument + ``SPI_TRANSFER_SIZE_8`` which specifies the size of data chunk it + will use when making callbacks to the application. + + - The ``spi_master()`` task controls the test SPI bus and takes + different ports to the SPI slave bus as arguments. For details on + using SPI master see application note AN00160. + + +The reg_file() task +................... + +The ``reg_file()`` task is the main logic of this example. It will +respond to calls from the application and the SPI slave bus whilst +maintaining a set of register values. + +The task is marked as ``[[distributable]]`` which means it can only +responds to calls from other tasks, rather than resource events. +The main reason for this is so +that the ``reg_file()`` task itself does not need a hardware thread of its +own it can use the hardware thread of the task that calls it. See the +XMOS programming guide for details of distributable tasks. + +The function takes two arguments, the interface connections to the +application task and the SPI slave task: + +.. literalinclude:: ../../examples/app_spi_slave/src/main.xc + :language: c + :start-at: [[distributable]] + :end-at: { + +The ``reg_if`` interface has been defined in ``main.xc`` earlier. It +defines the functions that the app may call in the ``reg_file()`` tasks: + +.. literalinclude:: ../../examples/app_spi_slave/src/main.xc + :language: c + :start-at: interface + :end-at: } + +In this case we have two functions - one for reading a register value +and one for writing a register value. + +The ``reg_file()`` task first declares its state - an array to hold +register value, a state variable to hold what stage of an SPI +transaction it is in and the currently addressed register by the SPI bus. + +.. literalinclude:: ../../examples/app_spi_slave/src/main.xc + :language: c + :start-at: This array holds + :end-at: addr = 0 + +The state variable is just an integer from the following ``enum`` type +defined earlier in the file: + +.. literalinclude:: ../../examples/app_spi_slave/src/main.xc + :language: c + :start-at: enum + :end-at: } + +The implemented protocol on the SPI bus is as follows: + + * The master will start a transaction (assert slave select) + * It will then send a byte of either a 0 for a write or a + 1 for a read. + * It will then send the address of the register to read/write + * It will then send or receive the value of the register + +|newpage| + +To implement the protocol logic the ``reg_file()`` task must continually react +to events from the SPI slave tasks keeping track of its state, +updating registers and supplying the correct outputs. This is done via +a ``while(1)`` loop with an xC ``select`` statement inside it. A +``select`` statement will wait and then react to various events or +calls from different tasks - see the XMOS programming guide for more details. + +The following cases in the main loop of the function handle this: + +.. literalinclude:: ../../examples/app_spi_slave/src/main.xc + :language: c + :start-at: while (1) + :end-before: respond to the application + +We can see that the slave will always send the value of the currently +addressed register on every data transfer (this is allowable in the +described protocol). + +When the SPI master supplies some data to the slave then what happens +depends on the current state - either the state variable is updated, +the currently addressed register is updated or a register value is +updated. This state machine will implement the previously described +protocol. + +|newpage| + +The main ``select`` statement also needs to react to request from the +application. The following cases implement this: + +.. literalinclude:: ../../examples/app_spi_slave/src/main.xc + :language: c + :start-at: respond to the application + :end-before: } + +The app() task +.............. + +The ``app()`` task represents a sample application task that uses the +register file. In this demo, it doesn't do much - it simple sets one +register and repeatedly polls the value of another register and prints +out its value: + +.. literalinclude:: ../../examples/app_spi_slave/src/main.xc + :language: c + :start-at: app( + :end-before: tester + + +.. note:: + + The ``debug_printf`` function comes from the ``debug_print.h`` header supplied by ``lib_logging``. It is a low + memory debug printing function that will print out messages to the + console (either using JTAG or xSCOPE to + communicate to the host via the debug adaptor). + +The tester() task +................. + +The tester task will send some test data to the SPI master +bus. It does this using the SPI master interface to communicate with +the SPI master task: + +.. literalinclude:: ../../examples/app_spi_slave/src/main.xc + :language: c + :start-at: tester( + :end-before: main + + + +Building +........ + +The following section assumes that the `XMOS XTC tools `_ has +been downloaded and installed (see `README` for required version). + +Installation instructions can be found `here `_. Particular +attention should be paid to the section `Installation of required third-party tools +`_. + +The application uses the `XMOS` build and dependency system, `xcommon-cmake `_. `xcommon-cmake` +is bundled with the `XMOS` XTC tools. It runs on the `xcore.ai` evaluation kit, `XK-EVK-XU316 `_. + +To configure the build, run the following from an XTC command prompt: + +.. code-block:: console + + cd examples + cd app_spi_slave + cmake -G "Unix Makefiles" -B build + +Any missing dependencies will be downloaded by the build system at this configure step. + + +Finally, the application binaries can be built using ``xmake``: + +.. code-block:: console + + xmake -j -C build + + +Running +....... + +To run the application return to the ``/examples/app_spi_slave`` directory and run the following command: + +.. code-block:: console + + xsim --xscope '-offline trace.xmt' bin/app_spi_slave.xe \ + --trace-plugin VcdPlugin.dll '-tile tile[0] -o trace.vcd -xe bin/app_spi_slave.xe \ + -ports -functions -cores -instructions' --plugin LoopbackPort.dll \ + '-port tile[0] XS1_PORT_1I 1 0 -port tile[0] XS1_PORT_1E 1 0 \ + -port tile[0] XS1_PORT_1J 1 0 -port tile[0] XS1_PORT_1F 1 0 \ + -port tile[0] XS1_PORT_1K 1 0 -port tile[0] XS1_PORT_1G 1 0 \ + -port tile[0] XS1_PORT_1L 1 0 -port tile[0] XS1_PORT_1H 1 0' + +.. note:: + + This command line is provided as a file in the ``/examples/app_spi_slave`` directory under the filename ``simulate_cmd.txt``. + You can rename this file to ``simulate_cmd.sh`` or ``simulate_cmd.bat`` and run it directly, depending on your host OS. + +As application runs that reads a value from the SPI connected WiFi chip and prints the following output to the console:: + + APP: Set register 0 to 0xED + APP: Register 0 is 0xED, Register 1 is 0x0 + APP: Register 0 is 0xED, Register 1 is 0x0 + SPI MASTER: Read register 0: 0xED + APP: Register 0 is 0xED, Register 1 is 0x0 + SPI MASTER: Set register 1 to 0xAC + APP: Register 0 is 0xED, Register 1 is 0xAC + APP: Register 0 is 0xED, Register 1 is 0xAC + APP: Register 0 is 0xED, Register 1 is 0xAC + +Both registers were initialised to 0x00 so you can see the successful application side write to register 0 of value 0xED, followed by the +SPI master read of that register shortly afterwards. You can also see that the SPI master writes to register 1 with the value of 0xAC +which is then successfully read by the application. + +If you wish, you can also view the simulation in a VCD (Voltage Change Description) viewer, such as ``gtkwave``, by running the following command: + +.. code-block:: console + + gtkwave slave_simulation.gtkw + +This will show the four SPI lines and zoom into the section where the SPI transactions occur, as can be seen in :numref:`spi_slave_simulation`. + +.. _spi_slave_simulation: + +.. figure:: ../images/spi_slave_simulation.png + :width: 100% + :align: center + + VCD waveform trace for SPI slave with registers simulation + +|newpage| + +************** +Resource Usage +************** + +Each of the SPI implementations use a number of `xcore` resources which include ports, clock-blocks and may include hardware threads. The table :numref:`res_use_table` + + +.. _res_use_table: + +.. list-table:: `xcore` resource usage for SPI + :widths: 20 30 5 10 5 + :header-rows: 1 + :stub-columns: 1 + + * - configuration + - api + - pins + - ports + - threads + * - Master (synchronous, zero clock blocks) + - spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, null); + - 4 + - 3 * 1-bit, 1 * any-bit + - 0 + * - Master (synchronous, one clock block) + - spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb); + - 4 + - 3 * 1-bit, 1 * any-bit + - 0 + * - Master (asynchronous) + - spi_master_async(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb); + - 4 + - 3 * 1-bit, 1 * any-bit + - 1 + * - Slave (32 bit transfer mode) + - spi_slave(i, p_sclk, p_mosi, p_miso, p_ss, cb, SPI_MODE_0, SPI_TRANSFER_SIZE_32); + - 4 + - 4 (1-bit) + - 1 + * - Slave (8 bit transfer mode) + - spi_slave(i, p_sclk, p_mosi, p_miso, p_ss, cb, SPI_MODE_0, SPI_TRANSFER_SIZE_8); + - 4 + - 4 (1-bit) + - 1 + + +The number of pins is reduced if either of the data lines are not required. + + +|newpage| + + +.. _api_section: + +************* +API Reference +************* + +Master API +========== + +All SPI master functions can be accessed via the ``spi.h`` header:: + + #include "spi.h" + +You will also have to add ``lib_spi`` to the application's ``APP_DEPENDENT_MODULES`` list in +`CMakeLists.txt`, for example:: + + set(APP_DEPENDENT_MODULES "lib_spi") + +Supporting types +................ + +The following type is used to configure the SPI components. + +.. doxygenenum:: spi_mode_t + +.. doxygenstruct:: spi_master_ss_clock_timing_t + +.. doxygenstruct:: spi_master_miso_capture_timing_t + +|newpage| + +Creating an SPI master instance +............................... + +.. doxygenfunction:: spi_master + +.. doxygenfunction:: spi_master_async + + +|newpage| + +SPI master interface +..................... + +.. c:namespace-push:: spi_master_if + +.. doxygengroup:: spi_master_if + +.. c:namespace-pop:: + + +|newpage| + +SPI master asynchronous interface +................................. + +.. c:namespace-push:: spi_master_async_if + +.. doxygengroup:: spi_master_async_if + +.. c:namespace-pop:: + +|newpage| + +Slave API +========= + +All SPI slave functions can be accessed via the ``spi.h`` header:: + + #include + +You will also have to add ``lib_spi`` to the +``APP_DEPENDENT_MODULES`` field of your application CMakefile. + +Creating an SPI slave instance +.............................. + +.. doxygenfunction:: spi_slave + +|newpage| + +.. doxygenenum:: spi_transfer_type_t + +|newpage| + +The SPI slave interface API +........................... + +.. c:namespace-push:: slave + +.. doxygengroup:: spi_slave_callback_if + +.. c:namespace-pop:: + diff --git a/examples/AN00160_using_SPI_master/.cproject b/examples/AN00160_using_SPI_master/.cproject deleted file mode 100644 index 27de2ed..0000000 --- a/examples/AN00160_using_SPI_master/.cproject +++ /dev/null @@ -1,851 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Default - all - true - true - true - - - xmake - CONFIG=Default - clean - true - true - true - - - - - diff --git a/examples/AN00160_using_SPI_master/.project b/examples/AN00160_using_SPI_master/.project deleted file mode 100644 index b741264..0000000 --- a/examples/AN00160_using_SPI_master/.project +++ /dev/null @@ -1,42 +0,0 @@ - - - AN00160_using_SPI_master - - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/examples/AN00160_using_SPI_master/AN00160_using_SPI_master.launch b/examples/AN00160_using_SPI_master/AN00160_using_SPI_master.launch deleted file mode 100644 index 3339834..0000000 --- a/examples/AN00160_using_SPI_master/AN00160_using_SPI_master.launch +++ /dev/null @@ -1,70 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/examples/AN00160_using_SPI_master/LICENSE.rst b/examples/AN00160_using_SPI_master/LICENSE.rst deleted file mode 100644 index ca48f20..0000000 --- a/examples/AN00160_using_SPI_master/LICENSE.rst +++ /dev/null @@ -1,84 +0,0 @@ -******************************* -XMOS PUBLIC LICENCE: Version 1 -******************************* - -Subject to the conditions and limitations below, permission is hereby granted by XMOS LIMITED (“XMOS”), free of charge, to any person or entity obtaining a copy of the XMOS Software. - -**1. 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It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = XCORE-200-EXPLORER -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -ADDITIONAL_FLAGS = -DXCORE_AI_EXPLORER=1 -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = AN00160_using_SPI_master - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -XCC_FLAGS = -O2 -g $(ADDITIONAL_FLAGS) - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/examples/AN00160_using_SPI_master/README.rst b/examples/AN00160_using_SPI_master/README.rst deleted file mode 100644 index 39f206a..0000000 --- a/examples/AN00160_using_SPI_master/README.rst +++ /dev/null @@ -1,46 +0,0 @@ -How to use the SPI library as SPI master -======================================== - -Summary -------- - -This application note shows how to use the SPI library to make the -xCORE drive an SPI bus as SPI master. The application is the simplest -example of setting up the library and performing a couple of -transactions. The code can then be run in simulation to see the -outputted waveforms. - -The note covers both the synchronous and asynchronous use of the SPI -master components provided from the library. - -Required tools and libraries -............................ - -* xTIMEcomposer Tools - Version 14.0 -* XMOS SPI library - Version 3.0.0 - -Required hardware -................. - -This application note is designed to run in simulation so requires no -XMOS hardware. - -Prerequisites -............. - - - This document assumes familiarity with the XMOS xCORE - architecture, the SPI bus protocol, the XMOS tool chain and the xC - language. Documentation related to these aspects which are not - specific to this application note are linked to in the references appendix. - - - For descriptions of XMOS related terms found in this document - please see the XMOS Glossary [#]_. - - - For the full API listing of the XMOS SPI Device Library please see - the library user guide [#]_. - - .. [#] http://www.xmos.com/published/glossary - - .. [#] http://www.xmos.com/support/libraries/lib_spi - - diff --git a/examples/AN00160_using_SPI_master/doc/rst/AN00160.rst b/examples/AN00160_using_SPI_master/doc/rst/AN00160.rst deleted file mode 100644 index 6708d25..0000000 --- a/examples/AN00160_using_SPI_master/doc/rst/AN00160.rst +++ /dev/null @@ -1,266 +0,0 @@ -.. include:: ../../README.rst - -|newpage| - -Overview --------- - -Introduction -............ - -The XMOS SPI library is a library that provides -software defined, industry-standard, SPI (serial peripheral interface) -components that allows you to control an SPI bus via the -xCORE GPIO hardware-response ports. SPI is a four-wire hardware -bi-directional serial interface. - -The SPI bus can be used by multiple tasks within the xCORE device -and (each addressing the same or different slaves) and -is compatible with other slave devices on the same bus. - -The library includes features such as SPI master and SPI slave modes, -supported speeds of up to 100 Mbit, multiple slave device support and -support for all configurations of clock polarity and phase. - -Block diagram -............. - -.. figure:: images/block_diagram.* - :scale: 100% - :align: center - - Block diagram of SPI master application example - -SPI master example ------------------- - -The example in this application note uses the XMOS SPI library to -perform some bus transactions as SPI master. The binary is then run in -simulation so the user can see the waveform output in the VCD tracing -perspective in the xTIMEcomposer. - -The application consists of two tasks: - - - A task that drives the SPI bus - - - An application task that connects to the SPI task - -These tasks communicate via the use of xC interfaces. - -The following diagram shows the task and communication structure of -the application. - -.. figure:: images/task_diag.* - - Task diagram of SPI master example - -Makefile additions for this example -................................... - -To start using the SPI library, you need to add ``lib_spi`` to your ``Makefile``:: - - USED_MODULES = ... lib_spi - -You can then access the SPI functions in your source code via the -spi.h header file:: - - #include - -Declaring ports -............... - -The SPI library connects to external pins via xCORE ports. In -``main.xc`` these are declared as variables of type ``port`` at the -start of the file: - -.. literalinclude:: main.xc - :start-on: p_sclk - :end-on: p_mosi - -Note that the slave select declaration (``p_ss``) is an array of -ports. This is what the SPI library expects since there may be many -slave select lines for multiple devices. - -How the ports (e.g. ``XS1_PORT_1I``) relate to external pins will -depend on the exact device being used. See the device datasheet for details. - -|newpage| - -The application main() function -............................... - -Below is the source code for the main function of this application, -which is taken from the source file ``main.xc`` - -.. literalinclude:: main.xc - :start-on: int main - :end-before: Uncomment - -Looking at this in more detail you can see the following: - - - The par functionality describes running two separate tasks in parallel - - - The ``spi_master`` task drives the SPI bus and takes the ports it - will use as arguments. - - - The ``app`` task communicates to the ``spi_master`` task via the - shared interface argument ``i_spi``. This is an array since the - SPI master task could connect to many other tasks in parallel. - -The app() function -.................. - -The ``app`` function uses its interface connection to the SPI master -task to perform SPI transactions. It performs two transactions (each -transaction will assert the slave select line, transfer some data and then -de-assert the slave select line). The functions in the SPI master -interface can be found in the SPI library user guide. - -.. literalinclude:: main.xc - :start-on: void app - :end-before: This application function - -Note that when ``begin_transaction`` is called the device is selected -by the first argument. In this case it is ``0``, so the zero-th -element of the ``p_ss`` array will be used for the slave select -line. This is the method that is used to communiate with multiple SPI -slave devices. The speed and mode of the SPI protocol is also set at -in the ``begin_transaction`` call. - -|newpage| - -Setting up the run configuration for the application -.................................................... - -To run the application binary in the simulator, first the application -must be built by pressing the :menuitem:`Build` button in the -xTIMEcomposer. This will create the ``AN00160_using_SPI_master.xe`` -binary in the ``bin`` folder of the project. The xTIMEcomposer may -have to import the SPI library if you do not already have it in your -workspace; this will occur automatically on build. - -Then a *Run Configuration* needs to be set up. This can be done by -selecting the :menuitem:`Run,Run Configurations..` menu. You can -create a new run configuration by right clicking on the -:menuitem:`xCORE application` group in the left hand pane and -:menuitem:`new`. However, in this example a run configuration has -already been created for you. - -Looking at this run configuration, you can see the simulator has been -selected under :menuitem:`Device Options:`: - -.. image:: images/run_config_sim.png - :width: 70% - :align: center - -|newpage| - -In the :menuitem:`Simulator` tab of the run configuration. The -:menuitem:`Enable signal tracing` check box has been enabled and a -:menuitem:`Tile Trace Option` has been added to trace the ports on -tile[0]: - -.. image:: images/run_config_trace.png - :width: 70% - :align: center - -|newpage| - -Running the application -....................... - -By clicking on the :menuitem:`Run` icon (a green arrow) in the Edit -Perspective of the xTIMEcomposer or by clicking the :menuitem:`Run` -button in the run configuration dialog, the program -will run. In the console window you will get this output:: - - Sending SPI traffic - Done. - -After this it will immediately swith the the VCD tracing perspective -(since signal tracing was enabled in the run configuration). In this -perspective you can drag ports from within the tree in the -:menuitem:`Signals` pane on the left hand side to the -:menuitem:`Waves` pane on the right: - -.. image:: images/vcd1.png - :width: 70% - :align: center - -By dragging in the four ports used by the application (1I, 1J, 1K and -1L) you can see that the application has driven the correct SPI -signal. Note that you need to expand each port and drag in just the -port value, the other traces (such as ``tile[0]_XS1_PORT_1J_inuse``) -just show the internal port state and are not so interesting here. - -.. image:: images/vcd2.png - :width: 70% - :align: center - -|newpage| - -Using the asynchronous interface -................................ - -There is an alternative ``main()`` function in the program to try: - -.. literalinclude:: main.xc - :start-on: Uncomment - -By uncommenting this main (and commenting out the original main) the -application will use the ``spi_master_async`` task instead of the -synchronous ``spi_master`` task. This task still drives the SPI bus -but runs on a separate logical core and will drive the bus in parallel -to your application. This way your application can overlap processing -with communication. - -The ``async_app()`` function performs the same function as the -``app()`` function using the asynchronous interface. The big -difference is that pointers have to be passed to the SPI task that -point to the buffers to send from/receive into. These need to be -*movable* pointers (see the xC programing guide for more information) -that can be passed to another task: - -.. literalinclude:: main.xc - :start-on: async_app - :end-on: outbuf - -|newpage| - -Once the pointers have been initialized they can be passed and later -retrieved from the SPI master task: - -.. literalinclude:: main.xc - :start-on: traffic (async) - :end-on: end_transaction - -|appendix| -|newpage| - -References ----------- - -.. nopoints:: - - * XMOS Tools User Guide - - http://www.xmos.com/published/xtimecomposer-user-guide - - * XMOS xCORE Programming Guide - - http://www.xmos.com/published/xmos-programming-guide - - * XMOS SPI Library - - http://www.xmos.com/support/libraries/lib_spi - -|newpage| - -Full source code listing ------------------------- - -.. literalinclude:: main.xc - :largelisting: - -|newpage| - diff --git a/examples/AN00160_using_SPI_master/doc/rst/images/Makefile b/examples/AN00160_using_SPI_master/doc/rst/images/Makefile deleted file mode 100644 index fddcef8..0000000 --- a/examples/AN00160_using_SPI_master/doc/rst/images/Makefile +++ /dev/null @@ -1,19 +0,0 @@ -ODGS = $(wildcard *.odg) -PDFS = $(ODGS:.odg=.pdf) - -all: $(PDFS) - @echo PDFs created - -_uncropped: - mkdir _uncropped - -_uncropped/%.pdf: %.odg | _uncropped - soffice -env:UserInstallation=file:///home/$(USER)/.libreoffice-alt --headless --convert-to pdf $< --outdir _uncropped - -%.pdf: _uncropped/%.pdf - pdfcrop $< $@ - -clean: - -rm $(PDFS) - -rm _uncropped/*.pdf - -rmdir _uncropped diff --git a/examples/AN00160_using_SPI_master/doc/rst/images/block_diagram.odg b/examples/AN00160_using_SPI_master/doc/rst/images/block_diagram.odg deleted file mode 100644 index ffffcf1..0000000 Binary files a/examples/AN00160_using_SPI_master/doc/rst/images/block_diagram.odg and /dev/null differ diff --git a/examples/AN00160_using_SPI_master/doc/rst/images/block_diagram.pdf b/examples/AN00160_using_SPI_master/doc/rst/images/block_diagram.pdf deleted file mode 100644 index 14f8776..0000000 Binary files a/examples/AN00160_using_SPI_master/doc/rst/images/block_diagram.pdf and /dev/null differ diff --git a/examples/AN00160_using_SPI_master/doc/rst/images/run_config_sim.png b/examples/AN00160_using_SPI_master/doc/rst/images/run_config_sim.png deleted file mode 100644 index e567951..0000000 Binary files a/examples/AN00160_using_SPI_master/doc/rst/images/run_config_sim.png and /dev/null differ diff --git a/examples/AN00160_using_SPI_master/doc/rst/images/run_config_trace.png b/examples/AN00160_using_SPI_master/doc/rst/images/run_config_trace.png deleted file mode 100644 index e474960..0000000 Binary files a/examples/AN00160_using_SPI_master/doc/rst/images/run_config_trace.png and /dev/null differ diff --git a/examples/AN00160_using_SPI_master/doc/rst/images/task_diag.odg b/examples/AN00160_using_SPI_master/doc/rst/images/task_diag.odg deleted file mode 100644 index f486170..0000000 Binary files a/examples/AN00160_using_SPI_master/doc/rst/images/task_diag.odg and /dev/null differ diff --git a/examples/AN00160_using_SPI_master/doc/rst/images/task_diag.pdf b/examples/AN00160_using_SPI_master/doc/rst/images/task_diag.pdf deleted file mode 100644 index 5e1db59..0000000 Binary files a/examples/AN00160_using_SPI_master/doc/rst/images/task_diag.pdf and /dev/null differ diff --git a/examples/AN00160_using_SPI_master/doc/rst/images/vcd1.png b/examples/AN00160_using_SPI_master/doc/rst/images/vcd1.png deleted file mode 100644 index 05bcf87..0000000 Binary files a/examples/AN00160_using_SPI_master/doc/rst/images/vcd1.png and /dev/null differ diff --git a/examples/AN00160_using_SPI_master/doc/rst/images/vcd2.png b/examples/AN00160_using_SPI_master/doc/rst/images/vcd2.png deleted file mode 100644 index 9f35031..0000000 Binary files a/examples/AN00160_using_SPI_master/doc/rst/images/vcd2.png and /dev/null differ diff --git a/examples/AN00160_using_SPI_master/doc/rst/xdoc.conf b/examples/AN00160_using_SPI_master/doc/rst/xdoc.conf deleted file mode 100644 index 37460ab..0000000 --- a/examples/AN00160_using_SPI_master/doc/rst/xdoc.conf +++ /dev/null @@ -1,2 +0,0 @@ -XMOSNEWSTYLE=1 -SOURCE_INCLUDE_DIRS=../../src \ No newline at end of file diff --git a/examples/AN00160_using_SPI_master/src/main.xc b/examples/AN00160_using_SPI_master/src/main.xc deleted file mode 100644 index 1270725..0000000 --- a/examples/AN00160_using_SPI_master/src/main.xc +++ /dev/null @@ -1,160 +0,0 @@ -// Copyright 2015-2021 XMOS LIMITED. -// This Software is subject to the terms of the XMOS Public Licence: Version 1. -#include -#include -#include -#include -#include -#include - -/* These ports are used for the SPI master */ -#ifdef XCORE_AI_EXPLORER -out buffered port:32 p_sclk = WIFI_CLK; -out port p_ss[1] = {WIFI_CS_N}; -in buffered port:32 p_miso = WIFI_MISO; -out buffered port:32 p_mosi = WIFI_MOSI; -out port p_rstn = WIFI_WUP_RST_N; -#else -out buffered port:32 p_sclk = on tile[0]: XS1_PORT_1I; -out port p_ss[1] = on tile[0]: {XS1_PORT_1J}; -in buffered port:32 p_miso = on tile[0]: XS1_PORT_1K; -out buffered port:32 p_mosi = on tile[0]: XS1_PORT_1L; -#endif - -clock clk0 = on tile[0]: XS1_CLKBLK_1; -clock clk1 = on tile[0]: XS1_CLKBLK_2; - -/* This application function sends some traffic as SPI master using - * the synchronous interface. Since this is run in simulation - * there is no slave, so the incoming data (stored in the 'val' - * variable) will just be zero. - */ -void app(client spi_master_if spi) -{ - uint8_t val; - printstrln("Sending SPI traffic"); -#if XCORE_AI_EXPLORER - - p_rstn <: 0x2; //Take out of reset and wait - delay_microseconds(1000); - spi.begin_transaction(0, 1000, SPI_MODE_1); - - uint32_t addr = 0; - uint32_t command = 0x8002 | (addr << 12); //Read command - val = spi.transfer8(command >> 8); - val = spi.transfer8(command & 0xff); - uint32_t reg; - reg = spi.transfer32(0x00); - spi.end_transaction(0); - printhexln(reg << 16 | reg >> 16); -#else - spi.begin_transaction(0, 100, SPI_MODE_0); - val = spi.transfer8(0xab); - val = spi.transfer32(0xcc); - val = spi.transfer8(0xfe); - spi.end_transaction(100); - - delay_microseconds(40); - spi.begin_transaction(0, 100, SPI_MODE_0); - val = spi.transfer8(0x22); - spi.end_transaction(100); -#endif - - printstrln("Done."); - _exit(0); -} - -/* This application function sends some traffic as SPI master using - * the asynchronous interface. Since this is run in simulation - * there is no slave, so the incoming data (stored in the 'val' - * variable) will just be zero. - */ -void async_app(client spi_master_async_if spi) -{ - uint8_t indata[10]; - uint8_t outdata[10]; - uint8_t * movable inbuf = indata; - uint8_t * movable outbuf = outdata; - - printstrln("Sending SPI traffic (async)"); - delay_microseconds(30); - - // Fill the out buffer with data - outbuf[0] = 0xab; - outbuf[1] = 0xcc; - outbuf[2] = 0; outbuf[3] = 0; outbuf[4] = 0; - outbuf[5] = 0xfe; - spi.begin_transaction(0, 100, SPI_MODE_0); - - // This call passes the buffers over to the SPI task, after - // this the application cannot access the buffers until - // the retrieve_transfer_buffers_8 function is called. - spi.init_transfer_array_8(move(inbuf), - move(outbuf), - 6); - - // Your application can do calculation here whilst the spi task - // transfers the buffer. - - // A select will wait for an event. In this case the event we are waiting - // for is the transfer_complete() notification event from the SPI task. - select { - case spi.transfer_complete(): - // Once the transfer is complete, we can retrieve the - // buffers back into the inbuf and outbuf pointer variables - spi.retrieve_transfer_buffers_8(inbuf, outbuf); - break; - } - - spi.end_transaction(100); - - - delay_microseconds(40); - spi.begin_transaction(0, 100, SPI_MODE_0); - outbuf[0] = 0x22; - spi.init_transfer_array_8(move(inbuf), - move(outbuf), - 1); - select { - case spi.transfer_complete(): - spi.retrieve_transfer_buffers_8(inbuf, outbuf); - break; - } - spi.end_transaction(100); - - printstrln("Done."); - - spi.shutdown(); -} - -#if 1 -int main(void) { - interface spi_master_if i_spi[1]; - par { - on tile[0]: app(i_spi[0]); - on tile[0]: spi_master(i_spi, 1, - p_sclk, p_mosi, p_miso, p_ss, 1, - null); - } - return 0; -} -#endif - -/* Uncomment the main below (and comment out the one above) to try the - async version. */ -#if 0 -int main(void) { - interface spi_master_async_if i_spi_async[1]; - par { - on tile[0]: { - par { - async_app(i_spi_async[0]); - spi_master_async(i_spi_async, 1, - p_sclk, p_mosi, p_miso, p_ss, 1, - clk0, clk1); - } - } - } - return 0; -} -#endif diff --git a/examples/AN00161_using_SPI_slave/.cproject b/examples/AN00161_using_SPI_slave/.cproject deleted file mode 100644 index 6139ffa..0000000 --- a/examples/AN00161_using_SPI_slave/.cproject +++ /dev/null @@ -1,869 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Default - all - true - true - true - - - xmake - CONFIG=Default - clean - true - true - true - - - - - diff --git a/examples/AN00161_using_SPI_slave/.project b/examples/AN00161_using_SPI_slave/.project deleted file mode 100644 index 5c1ddbb..0000000 --- a/examples/AN00161_using_SPI_slave/.project +++ /dev/null @@ -1,42 +0,0 @@ - - - AN00161_using_SPI_slave - - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/examples/AN00161_using_SPI_slave/AN00161_using_SPI_slave.launch b/examples/AN00161_using_SPI_slave/AN00161_using_SPI_slave.launch deleted file mode 100644 index 87a5113..0000000 --- a/examples/AN00161_using_SPI_slave/AN00161_using_SPI_slave.launch +++ /dev/null @@ -1,71 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/examples/AN00161_using_SPI_slave/LICENSE.rst b/examples/AN00161_using_SPI_slave/LICENSE.rst deleted file mode 100644 index ca48f20..0000000 --- a/examples/AN00161_using_SPI_slave/LICENSE.rst +++ /dev/null @@ -1,84 +0,0 @@ -******************************* -XMOS PUBLIC LICENCE: Version 1 -******************************* - -Subject to the conditions and limitations below, permission is hereby granted by XMOS LIMITED (“XMOS”), free of charge, to any person or entity obtaining a copy of the XMOS Software. - -**1. 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IN SOME JURISDICTIONS PARTIES ARE UNABLE TO LIMIT LIABILTY IN THIS WAY, IF THIS APPLIES TO YOUR JURISDICTION THIS LIABILITY CLAUSE ABOVE MAY NOT APPLY. NOTWITHSTANDING THE ABOVE, IN NO EVENT SHALL XMOS’s TOTAL LIABILITY TO YOU FOR ALL DAMAGES, LOSS OR OTHERWISE EXCEED $50. - -**11. Governing Law and Jurisdiction.** This Licence constitutes the entire agreement between the parties with respect to the subject matter hereof. The Licence shall be governed by the laws of England and the conflict of laws and UN Convention on Contracts for the International Sale of Goods, shall not apply. diff --git a/examples/AN00161_using_SPI_slave/Makefile b/examples/AN00161_using_SPI_slave/Makefile deleted file mode 100644 index 7b9a2f5..0000000 --- a/examples/AN00161_using_SPI_slave/Makefile +++ /dev/null @@ -1,35 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = SLICEKIT-L16 -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = AN00161_using_SPI_slave - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -XCC_FLAGS = -O2 -g -report -DDEBUG_PRINT_ENABLE=1 - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/examples/AN00161_using_SPI_slave/README.rst b/examples/AN00161_using_SPI_slave/README.rst deleted file mode 100644 index 71776d0..0000000 --- a/examples/AN00161_using_SPI_slave/README.rst +++ /dev/null @@ -1,44 +0,0 @@ -How to use the SPI library as SPI slave -======================================= - -Summary -------- - -This application note shows how to use the SPI library to make the -xCORE use an SPI bus as SPI slave. The application provides a register -file that can be read and written by the internal application and by -the SPI master using a simple command set. The code is -run in simulation with an SPI master output looped-back onto the SPI -slave input to show the bus functioning. - -Required tools and libraries -............................ - -* xTIMEcomposer Tools - Version 14.0 -* XMOS SPI library - Version 3.0.0 - -Required hardware -................. - -This application note is designed to run in simulation so requires no -XMOS hardware. - -Prerequisites -............. - - - This document assumes familiarity with the XMOS xCORE - architecture, the SPI bus protocol, the XMOS tool chain and the xC - language. Documentation related to these aspects which are not - specific to this application note are linked to in the references appendix. - - - For descriptions of XMOS related terms found in this document - please see the XMOS Glossary [#]_. - - - For the full API listing of the XMOS SPI Device Library please see - the library user guide [#]_. - - .. [#] http://www.xmos.com/published/glossary - - .. [#] http://www.xmos.com/support/libraries/lib_spi - - diff --git a/examples/AN00161_using_SPI_slave/doc/rst/AN00161.rst b/examples/AN00161_using_SPI_slave/doc/rst/AN00161.rst deleted file mode 100644 index f8447de..0000000 --- a/examples/AN00161_using_SPI_slave/doc/rst/AN00161.rst +++ /dev/null @@ -1,382 +0,0 @@ -.. include:: ../../README.rst - -|newpage| - -Overview --------- - -Introduction -............ - -The XMOS SPI library is a library that provides -software defined, industry-standard, SPI (serial peripheral interface) -components that allows you to control an SPI bus via the -xCORE GPIO hardware-response ports. SPI is a four-wire hardware -bi-directional serial interface. - -The SPI bus can be used by multiple tasks within the xCORE device -and (each addressing the same or different slaves) and -is compatible with other slave devices on the same bus. - -The library includes features such as SPI master and SPI slave modes, -supported speeds of up to 100 Mbit, multiple slave device support and -support for all configurations of clock polarity and phase. - -Block diagram -............. - -.. figure:: images/block_diagram.* - :scale: 100% - :align: center - - Block diagram of SPI slave application example - -SPI slave example ------------------- - -The example in this application note uses the XMOS SPI library to -act as SPI slave. It maintains a register file which can be read and -written by the internal application *or* by the master on the SPI bus. -To show the bus functioning the demo application also has a tester -component connected to an SPI master bus which is connected (in -simulation) to the the SPI slave. This allows the generation of -traffic to show the the communication functioning. - -The application consists of five tasks: - - - A task that controls the SPI slave ports - - - A task that implements the register file handling calls from the - SPI slave component and the application - - - An application task that connects to the register file task - - - A task that controls the SPI master ports used for testing - - - A tester task that outputs commands to the SPI master task - -These tasks communicate via the use of xC interfaces. - -The following diagram shows the task and communication structure of -the application. - -.. figure:: images/task_diag.* - - Task diagram of SPI slave example - -The SPI slave task communicates via the ``spi_slave_callback_if`` -which the SPI library defines as a set of callbacks a slave will make -to the application to handle communication occuring on the SPI -bus. - -The application also needs to communicate with the register file task -to get or set register values. To do this we define a custom -communication software interface (``reg_if``). - -|newpage| - -Makefile additions for this example -................................... - -To start using the SPI library, you need to add ``lib_spi`` to your ``Makefile``:: - - USED_MODULES = ... lib_spi - -You can then access the SPI functions in your source code via the -spi.h header file:: - - #include - -The example also uses the XMOS debug printing library -(``lib_logging``). This provides handy debug printing functions:: - - USED_MODULES = ... lib_logging - -Declaring ports -............... - -The SPI library connects to external pins via xCORE ports. In -``main.xc`` these are declared as variables of type ``port`` at the -start of the file: - -.. literalinclude:: main.xc - :start-on: p_sclk - :end-on: clock - -Note that there is also a clock declaration since the slave needs to -use an internal clock as well as ports inside the xCORE device. - -How the ports (e.g. ``XS1_PORT_1I``) relate to external pins will -depend on the exact device being used. See the device datasheet for details. - -This application also has an SPI master interface on different ports: - -.. literalinclude:: main.xc - :start-on: p_test_sclk - :end-on: p_test_mosi - -|newpage| - -The application main() function -............................... - -Below is the source code for the main function of this application, -which is taken from the source file ``main.xc`` - -.. literalinclude:: main.xc - :start-on: int main - -Looking at this in a more detail you can see the following: - - - The par functionality describes running five separate tasks in - parallel; three are for the main application and two are for the - tester. - - - The ``spi_slave`` task controls the application - SPI bus and takes the ports it will use as arguments. - - - The ``reg_file`` task is connected to the ``app`` task and the - ``spi_slave`` task. - - - The ``spi_slave`` task has an argument for the mode is expects - - in this case Mode 0 (see the SPI library user guide for more - details on modes) - - - The ``spi_slave`` task also has an argument - ``SPI_TRANSFER_SIZE_8`` which specifies the size of data chunk it - will use when making callbacks to the application. - - - The ``spi_master`` task controls the test SPI bus and takes - different ports to the SPI slave bus as arguments. For details on - using SPI master see application note AN00160. - - -The reg_file() function -....................... - -The ``reg_file`` function is the main logic of this example. It will -respond to calls from the application and the SPI slave bus whilst -maintaining a set of register values. - -The function is marked as ``[[distributable]]`` which means it only -responds to calls from other tasks. The main reason for this is so -that the ``reg_file`` task itself does not need a logical core of its -own it can use the logical core of the task that calls it. See the -XMOS programming guide for details of distributable tasks. - -The function takes two arguments, the interface connections to the -application task and the SPI slave task: - -.. literalinclude:: main.xc - :start-on: [[distributable]] - :end-on: { - -The ``reg_if`` interface has been defined in ``main.xc`` earlier. It -defines the functions that the app may call in the ``reg_file`` tasks: - -.. literalinclude:: main.xc - :start-on: interface - :end-on: } - -In this case we have two functions - one for reading a register value -and one for writing a register value. - -The ``reg_file`` function first declares its state - an array to hold -register value, a state variable to hold what stage of an SPI -transaction it is in and the currently addressed register by the SPI bus. - -.. literalinclude:: main.xc - :start-on: This array holds - :end-on: addr = 0 - -The state variable is just an integer from the following ``enum`` type -defined earlier in the file: - -.. literalinclude:: main.xc - :start-on: enum - :end-on: } - -The implemented protocol on the SPI bus is as follows: - - * The master will start a transaction (assert slave select) - * It will then send a byte of either a 0 for a write or a - 1 for a read. - * It will then send the address of the register to read/write - * It will then send or receive the value of the register - -|newpage| - -To implement the protocol logic the ``reg_file`` tasks must continually react -to events from the SPI slave tasks keeping track of its state, -updating registers and supplying the correct outputs. This is done via -a ``while (1)`` loop with an xC ``select`` statement inside it. A -``select`` statement will wait and then react to various events or -calls from different tasks - see the XMOS programming guide for more details. - -The following cases in the main loop of the function handle this: - -.. literalinclude:: main.xc - :start-on: while (1) - :end-before: respond to the application - -We can see that the slave will always send the value of the currently -addressed register on every data transfer (this is allowable in the -described protocol). - -When the SPI master supplies some data to the slave then what happens -depends on the current state - either the state variable is updated, -the currently addressed register is updated or a register value is -updated. This state machine will implement the previously described -protocol. - -|newpage| - -The main select also needs to react to request from the -application. The following cases implement this: - -.. literalinclude:: main.xc - :start-on: respond to the application - :end-before: } - -The app() function -.................. - -The ``app`` task represents a sample application tasks that uses the -register file. In this demo, it doesn't do much - it simple sets one -register and repeatedly polls the value of another register and prints -out its value: - -.. literalinclude:: main.xc - :start-on: app( - :end-before: tester - -Note that the ``debug_printf`` function comes from the -``debug_print.h`` header supplied by ``lib_logging``. It is a low -memory debug printing function that will print out messages to the -console in the xTIMEcomposer (either using JTAG or xSCOPE to -communicate to the host via the debug adaptor). - -The tester() function -..................... - -The tester function will send some test data to the SPI master -bus. It does this using the SPI master interface to communicate with -the SPI master task: - -.. literalinclude:: main.xc - :start-on: tester( - :end-before: main - - -|newpage| - - -Setting up the run configuration for the application -.................................................... - -To run the application binary in the simulator, first the application -must be built by pressing the :menuitem:`Build` button in the -xTIMEcomposer. This will create the ``AN00161_using_SPI_slave.xe`` -binary in the ``bin`` folder of the project. The xTIMEcomposer may -have to import the SPI library if you do not already have it in your -workspace; this will occur automatically on build. - -Then a *Run Configuration* needs to be set up. This can be done by -selecting the :menuitem:`Run,Run Configurations..` menu. You can -create a new run configuration by right clicking on the -:menuitem:`xCORE application` group in the left hand pane and -:menuitem:`new`. However, in this example a run configuration has -already been created for you. - -Looking at this run configuration, you can see the simulator has been -selected under :menuitem:`Device Options:`: - -.. image:: images/run_config_sim.png - :width: 70% - :align: center - -|newpage| - -In the :menuitem:`Loopback` tab of the :menuitem:`Simulator` tab of -the run configuration. The -:menuitem:`Enable pin connections` check box has been enabled and four -loopback connections have been added connecting the SPI master ports -to the corresponding SPI slave ports: - -.. image:: images/run_config_loopback.png - :width: 70% - :align: center - -|newpage| - -Running the application -....................... - -By clicking on the :menuitem:`Run` icon (a green arrow) in the Edit -Perspective of the xTIMEcomposer or by clicking the :menuitem:`Run` -button in the run configuration dialog, the program -will run. In the console window you will get this output:: - - APP: Set register 1 to 0xFE - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - SPI MASTER: Read register 0: 0xFE - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - APP: Register 1 is 0x0 - SPI MASTER: Set register 1 to 0xAC - APP: Register 1 is 0xAC - APP: Register 1 is 0xAC - APP: Register 1 is 0xAC - ... - -You can terminate the program by clicking the :menuitem:`Terminate` -button in the Console window (the red square). - -The console shows the debug print output from the application and tester. You -can see that the SPI bus can read registers that the application has -set and the application can read registers that the SPI bus has set. - -|appendix| -|newpage| - -References ----------- - -.. nopoints:: - - * XMOS Tools User Guide - - http://www.xmos.com/published/xtimecomposer-user-guide - - * XMOS xCORE Programming Guide - - http://www.xmos.com/published/xmos-programming-guide - - * XMOS SPI Library - - http://www.xmos.com/support/libraries/lib_spi - -|newpage| - -Full source code listing ------------------------- - -.. literalinclude:: main.xc - :largelisting: - -|newpage| - diff --git a/examples/AN00161_using_SPI_slave/doc/rst/images/Makefile b/examples/AN00161_using_SPI_slave/doc/rst/images/Makefile deleted file mode 100644 index fddcef8..0000000 --- a/examples/AN00161_using_SPI_slave/doc/rst/images/Makefile +++ /dev/null @@ -1,19 +0,0 @@ -ODGS = $(wildcard *.odg) -PDFS = $(ODGS:.odg=.pdf) - -all: $(PDFS) - @echo PDFs created - -_uncropped: - mkdir _uncropped - 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index 48bd809..0000000 Binary files a/examples/AN00161_using_SPI_slave/doc/rst/images/task_diag.odg and /dev/null differ diff --git a/examples/AN00161_using_SPI_slave/doc/rst/images/task_diag.pdf b/examples/AN00161_using_SPI_slave/doc/rst/images/task_diag.pdf deleted file mode 100644 index 8b7937e..0000000 Binary files a/examples/AN00161_using_SPI_slave/doc/rst/images/task_diag.pdf and /dev/null differ diff --git a/examples/AN00161_using_SPI_slave/doc/rst/xdoc.conf b/examples/AN00161_using_SPI_slave/doc/rst/xdoc.conf deleted file mode 100644 index 37460ab..0000000 --- a/examples/AN00161_using_SPI_slave/doc/rst/xdoc.conf +++ /dev/null @@ -1,2 +0,0 @@ -XMOSNEWSTYLE=1 -SOURCE_INCLUDE_DIRS=../../src \ No newline at end of file diff --git a/examples/CMakeLists.txt b/examples/CMakeLists.txt new file mode 100644 index 0000000..325e53a --- /dev/null +++ b/examples/CMakeLists.txt @@ -0,0 +1,7 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +project(lib_spi_examples) + +add_subdirectory(app_spi_master) +add_subdirectory(app_spi_slave) \ No newline at end of file diff --git a/examples/app_spi_master/CMakeLists.txt b/examples/app_spi_master/CMakeLists.txt new file mode 100644 index 0000000..8742cfb --- /dev/null +++ b/examples/app_spi_master/CMakeLists.txt @@ -0,0 +1,40 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) +project(app_spi_master) + +# Sandbox configuration +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) + +# Target, xscope +set(APP_HW_TARGET XCORE-AI-EXPLORER) +set(APP_XSCOPE_SRCS config.xscope) + +# Includes, Dependencies +list(APPEND APP_INCLUDES src) +include(${CMAKE_CURRENT_LIST_DIR}/../deps.cmake) + +# Flags +set(COMPILER_FLAGS_COMMON + -Os + -g + -report + -Wall + -Werror +) + +# Standard `fast` SPI synchronous version +set(APP_COMPILER_FLAGS_SYNC + ${COMPILER_FLAGS_COMMON}) + +# Clock-blockless `slow` SPI synchronous version +set(APP_COMPILER_FLAGS_SYNC_NO_CLKBLK + -DCLKBLK=null + ${COMPILER_FLAGS_COMMON}) + +# SPI Asynchronous version +set(APP_COMPILER_FLAGS_ASYNC + ${COMPILER_FLAGS_COMMON} + -DSPI_USE_ASYNC=1) + + +XMOS_REGISTER_APP() diff --git a/examples/AN00161_using_SPI_slave/config.xscope b/examples/app_spi_master/config.xscope similarity index 100% rename from examples/AN00161_using_SPI_slave/config.xscope rename to examples/app_spi_master/config.xscope diff --git a/examples/app_spi_master/src/main.xc b/examples/app_spi_master/src/main.xc new file mode 100644 index 0000000..d2a419d --- /dev/null +++ b/examples/app_spi_master/src/main.xc @@ -0,0 +1,161 @@ +// Copyright 2015-2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. +#include +#include +#include +#include +#include +#include + +out buffered port:32 p_sclk = WIFI_CLK; +out port p_ss = WIFI_CS_N; +in buffered port:32 p_miso = WIFI_MISO; +out buffered port:32 p_mosi = WIFI_MOSI; +out port p_rstn = WIFI_WUP_RST_N; + +clock clk = on tile[0]: XS1_CLKBLK_1; + +#define RESET_DEASSERT 0x02 +#define POST_RESET_DELAY_MICROSECONDS 1000 +#define SPI_SPEED_KBPS 1000 + +/* This application function sends some traffic as SPI master using + * the synchronous interface. It reads the config register (address 0) + * of the WFM200S using a 16b command and prints the 32b read result */ +void app(client spi_master_if spi) +{ + uint8_t val; + printstrln("Sending SPI traffic"); + + p_rstn <: RESET_DEASSERT; //Take out of reset and wait + delay_microseconds(POST_RESET_DELAY_MICROSECONDS); + + spi.set_ss_port_bit(0, 1); // We are using bit 1 in WIFI_CS_N for device 0 + + spi.begin_transaction(0, SPI_SPEED_KBPS, SPI_MODE_0); + + uint32_t reg_addr = 0; // Read reg 0 CONFIG register + uint32_t read_cmd = 0x8000; + uint32_t num_16b_words = 2; + uint32_t reg_addr_shift = 12; + uint32_t command = read_cmd | num_16b_words | (reg_addr << reg_addr_shift); //Do read command + + val = spi.transfer8(command >> 8);// MSB first + val = spi.transfer8(command & 0xff); + + uint32_t reg; + reg = spi.transfer32(0x00); //Read result + spi.end_transaction(0); + + printhexln(reg >> 16); // Should be 0x5400 + printstrln("Done."); + spi.shutdown(); +} + +/* This application function sends some traffic as SPI master using + * the synchronous interface. It reads the config register (address 0) + * of the WFM200S using a 16b command and prints the 32b read result */ +void async_app(client spi_master_async_if spi) +{ + + printstrln("Sending aynch SPI traffic"); + + p_rstn <: RESET_DEASSERT; //Take out of reset and wait + delay_microseconds(POST_RESET_DELAY_MICROSECONDS); + spi.set_ss_port_bit(0, 1); // We are using bit 1 in WIFI_CS_N for device 0 + + spi.begin_transaction(0, SPI_SPEED_KBPS, SPI_MODE_0); + + // Build command + uint32_t reg_addr = 0; // Read reg 0 CONFIG register + uint32_t read_cmd = 0x8000; + uint32_t num_16b_words = 2; + uint32_t reg_addr_shift = 12; + uint32_t command = read_cmd | num_16b_words | (reg_addr << reg_addr_shift); //Do read command + + uint8_t outbuffer[2]; + outbuffer[0] = (command >> 8) & 0xff; // MSB first + outbuffer[1] = command & 0xff; + + uint8_t * movable inbuf = NULL; // We do not care about the read data for the cmd write + uint8_t * movable outbuf = outbuffer; + + + // This call passes the buffers over to the SPI task, after + // this the application cannot access the buffers until + // the retrieve_transfer_buffers_8 function is called. + + spi.init_transfer_array_8(move(inbuf), + move(outbuf), + 2); + + // A select will wait for an event. In this case the event we are waiting + // for is the transfer_complete() notification event from the SPI task. + select { + case spi.transfer_complete(): + // Once the transfer is complete, we can retrieve the + // buffers back into the inbuf and outbuf pointer variables + spi.retrieve_transfer_buffers_8(inbuf, outbuf); + break; + } + + spi.begin_transaction(0, SPI_SPEED_KBPS, SPI_MODE_0); + + uint32_t inbuffer32[1] = {0}; + uint32_t * movable inbuf32 = inbuffer32; + uint32_t * movable outbuf32 = NULL; // We do not care what is written during reg reads + + spi.init_transfer_array_32(move(inbuf32), + null, + 1); + + select { + case spi.transfer_complete(): + // Once the transfer is complete, we can retrieve the + // buffers back into the inbuf and outbuf pointer variables + spi.retrieve_transfer_buffers_32(inbuf32, + outbuf32); + break; + } + + printhexln(*inbuf32 >> 16); // Should be 0x5400 + printstrln("Done."); + + spi.shutdown(); +} + + +#if SPI_USE_ASYNC +// SPI async main +int main(void) { + interface spi_master_async_if i_spi_async[1]; + par { + on tile[0]: { + par { + async_app(i_spi_async[0]); + spi_master_async(i_spi_async, 1, p_sclk, p_mosi, p_miso, p_ss, 1, clk); + } + } + } + return 0; +} +// end async main + +#else // SYNC + +#ifndef CLKBLK +#define CLKBLK clk +#endif + +// SPI sync main +int main(void) { + interface spi_master_if i_spi[1]; + par { + on tile[0]: app(i_spi[0]); + on tile[0]: spi_master(i_spi, 1, p_sclk, p_mosi, p_miso, p_ss, 1, CLKBLK); + } + return 0; +} +// end sync main + +#endif /*SPI_USE_ASYNC*/ diff --git a/examples/app_spi_slave/CMakeLists.txt b/examples/app_spi_slave/CMakeLists.txt new file mode 100644 index 0000000..0f62b1f --- /dev/null +++ b/examples/app_spi_slave/CMakeLists.txt @@ -0,0 +1,27 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) +project(app_spi_slave) + +# Sandbox configuration +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) + +# Target, xscope +set(APP_HW_TARGET XCORE-AI-EXPLORER) +set(APP_XSCOPE_SRCS config.xscope) + +# Includes, Dependencies +list(APPEND APP_INCLUDES src) +include(${CMAKE_CURRENT_LIST_DIR}/../deps.cmake) + +# Flags +set( + APP_COMPILER_FLAGS + -Os + -g + -report + -Wall + -Werror + -DDEBUG_PRINT_ENABLE=1 +) + +XMOS_REGISTER_APP() diff --git a/examples/AN00160_using_SPI_master/config.xscope b/examples/app_spi_slave/config.xscope similarity index 96% rename from examples/AN00160_using_SPI_master/config.xscope rename to examples/app_spi_slave/config.xscope index bfdf1f8..1540288 100644 --- a/examples/AN00160_using_SPI_master/config.xscope +++ b/examples/app_spi_slave/config.xscope @@ -14,7 +14,7 @@ - + diff --git a/examples/app_spi_slave/simulate_cmd.txt b/examples/app_spi_slave/simulate_cmd.txt new file mode 100644 index 0000000..45283fa --- /dev/null +++ b/examples/app_spi_slave/simulate_cmd.txt @@ -0,0 +1 @@ +xsim --xscope '-offline trace.xmt' bin/app_spi_slave.xe --trace-plugin VcdPlugin.dll '-tile tile[0] -o trace.vcd -xe bin/app_spi_slave.xe -ports -functions -cores -instructions' --plugin LoopbackPort.dll '-port tile[0] XS1_PORT_1I 1 0 -port tile[0] XS1_PORT_1E 1 0 -port tile[0] XS1_PORT_1J 1 0 -port tile[0] XS1_PORT_1F 1 0 -port tile[0] XS1_PORT_1K 1 0 -port tile[0] XS1_PORT_1G 1 0 -port tile[0] XS1_PORT_1L 1 0 -port tile[0] XS1_PORT_1H 1 0' diff --git a/examples/AN00161_using_SPI_slave/src/main.xc b/examples/app_spi_slave/src/main.xc similarity index 82% rename from examples/AN00161_using_SPI_slave/src/main.xc rename to examples/app_spi_slave/src/main.xc index 6931682..068dbee 100644 --- a/examples/AN00161_using_SPI_slave/src/main.xc +++ b/examples/app_spi_slave/src/main.xc @@ -1,11 +1,13 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include -#include #include #include #include #include +#include + +#include "spi.h" /* These ports are used for the SPI slave task */ in port p_sclk = on tile[0]: XS1_PORT_1E; @@ -17,9 +19,12 @@ clock cb = on tile[0]: XS1_CLKBLK_1; /* These ports are used for the SPI master task which is used to test the SPI slave (via simulator loopback). */ out buffered port:32 p_test_sclk = on tile[0]: XS1_PORT_1I; -out port p_test_ss[1] = on tile[0]: {XS1_PORT_1J}; +out port p_test_ss = on tile[0]: XS1_PORT_1J; in buffered port:32 p_test_miso = on tile[0]: XS1_PORT_1K; out buffered port:32 p_test_mosi = on tile[0]: XS1_PORT_1L; +// Clock used specifically for the test SPI master component. +clock cb_test = on tile[0]: XS1_CLKBLK_2; + /* Interface to communicate between the register file tasks and the application. */ @@ -28,7 +33,9 @@ typedef interface reg_if { void set_reg(uint8_t regnum, uint8_t value); } reg_if; -#define NUM_REG 5 +#define SPI_SPEED_KBPS 1000 +#define NUM_REG 5 +#define SPI_SS_DELAY_10NS_TICKS 100 // 1 microsecond enum reg_state_t { WRITE_REG = 0, @@ -127,12 +134,15 @@ void reg_file(server spi_slave_callback_if i_spi, * to the reg_file tasks to get/set registers. */ void app(client reg_if reg) { - reg.set_reg(0, 0xfe); - printstr("APP: Set register 1 to 0xFE\n"); + uint8_t set_reg_data = 0xed; + reg.set_reg(0, set_reg_data); + debug_printf("APP: Set register %u to 0x%x\n", 0, set_reg_data); while (1) { + uint8_t reg_data_read[2]; delay_microseconds(20); - printstr("APP: Register 1 is 0x"); - printhexln(reg.get_reg(1)); + reg_data_read[0] = reg.get_reg(0); + reg_data_read[1] = reg.get_reg(1); + debug_printf("APP: Register %d is 0x%x, Register %d is 0x%x\n", 0, reg_data_read[0], 1, reg_data_read[1]); } } @@ -143,22 +153,24 @@ void app(client reg_if reg) { */ void tester(client spi_master_if spi) { - delay_microseconds(45); + delay_microseconds(50); // Wait for slave to init uint8_t val; - spi.begin_transaction(0, 100, SPI_MODE_0); + spi.begin_transaction(0, SPI_SPEED_KBPS, SPI_MODE_0); spi.transfer8(READ_REG); // READ command spi.transfer8(0); // REGISTER 0 val = spi.transfer8(0); // DATA - spi.end_transaction(100); - printstr("SPI MASTER: Read register 0: 0x"); - printhexln(val); + spi.end_transaction(SPI_SS_DELAY_10NS_TICKS); + debug_printf("SPI MASTER: Read register 0: 0x%x\n", val); - spi.begin_transaction(0, 100, SPI_MODE_0); + spi.begin_transaction(0, SPI_SPEED_KBPS, SPI_MODE_0); spi.transfer8(WRITE_REG); // WRITE command spi.transfer8(1); // REGISTER 1 spi.transfer8(0xac); // DATA - spi.end_transaction(100); + spi.end_transaction(SPI_SS_DELAY_10NS_TICKS); printstr("SPI MASTER: Set register 1 to 0xAC\n"); + + delay_microseconds(100); + _Exit(0); } int main(void) { @@ -177,7 +189,7 @@ int main(void) { on tile[0]: tester(i_spi_master[0]); on tile[0]: spi_master(i_spi_master, 1, p_test_sclk, p_test_mosi, p_test_miso, p_test_ss, - 1, null); + 1, cb_test); } return 0; } diff --git a/examples/deps.cmake b/examples/deps.cmake new file mode 100644 index 0000000..81867d5 --- /dev/null +++ b/examples/deps.cmake @@ -0,0 +1,3 @@ +# Common dependencies for examples +set(APP_DEPENDENT_MODULES "lib_spi" + "lib_logging(3.3.2)") diff --git a/legacy_tests/.gitignore b/legacy_tests/.gitignore deleted file mode 100644 index 095cd5e..0000000 --- a/legacy_tests/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -.venv -Pipfile.lock diff --git a/legacy_tests/lib_spi_master_tester/.cproject b/legacy_tests/lib_spi_master_tester/.cproject deleted file mode 100644 index ed4c25c..0000000 --- a/legacy_tests/lib_spi_master_tester/.cproject +++ /dev/null @@ -1,817 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/legacy_tests/lib_spi_master_tester/.makefile b/legacy_tests/lib_spi_master_tester/.makefile deleted file mode 100644 index 3262365..0000000 --- a/legacy_tests/lib_spi_master_tester/.makefile +++ /dev/null @@ -1,4 +0,0 @@ -all: - @echo "** Module only - only builds as part of application **" -clean: - @echo "** Module only - only builds as part of application **" diff --git a/legacy_tests/lib_spi_master_tester/.project b/legacy_tests/lib_spi_master_tester/.project deleted file mode 100644 index ad9ecb2..0000000 --- a/legacy_tests/lib_spi_master_tester/.project +++ /dev/null @@ -1,47 +0,0 @@ - - - lib_spi_master_tester - - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - com.xmos.cdt.core.BuildMarkersBuilder - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/legacy_tests/lib_spi_master_tester/module_build_info b/legacy_tests/lib_spi_master_tester/module_build_info deleted file mode 100644 index efa7315..0000000 --- a/legacy_tests/lib_spi_master_tester/module_build_info +++ /dev/null @@ -1,17 +0,0 @@ -# You can set flags specifically for your module by using the MODULE_XCC_FLAGS -# variable. So the following -# -# MODULE_XCC_FLAGS = $(XCC_FLAGS) -O3 -# -# specifies that everything in the modules should have the application -# build flags with -O3 appended (so the files will build at -# optimization level -O3). -# -# You can also set MODULE_XCC_C_FLAGS, MODULE_XCC_XC_FLAGS etc.. - -MODULE_XCC_XC_FLAGS = $(XCC_XC_FLAGS) - -# The following specifies the dependencies of the module. When an application -# includes a module it will also include all its dependencies. -# DEPENDENT_MODULES = - diff --git a/legacy_tests/lib_spi_master_tester/module_description b/legacy_tests/lib_spi_master_tester/module_description deleted file mode 100644 index 00a6de4..0000000 --- a/legacy_tests/lib_spi_master_tester/module_description +++ /dev/null @@ -1 +0,0 @@ -One line module description. diff --git a/legacy_tests/master_benchmark.expect b/legacy_tests/master_benchmark.expect deleted file mode 100644 index 79c832d..0000000 --- a/legacy_tests/master_benchmark.expect +++ /dev/null @@ -1,3 +0,0 @@ -SPI Master checker started -.* -.* diff --git a/legacy_tests/requirements.txt b/legacy_tests/requirements.txt deleted file mode 100644 index 4be5e8e..0000000 --- a/legacy_tests/requirements.txt +++ /dev/null @@ -1 +0,0 @@ -# python_version 2.7 diff --git a/legacy_tests/runtests.py b/legacy_tests/runtests.py deleted file mode 100755 index 270f4eb..0000000 --- a/legacy_tests/runtests.py +++ /dev/null @@ -1,48 +0,0 @@ -#!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest -from spi_master_checker import SPIMasterChecker - -if __name__ == "__main__": - xmostest.init() - - xmostest.register_group("lib_spi", - "spi_master_sim_tests", - "spi master simulator tests", - """ -Tests are performed by running the spi library connected to a -simulator model (written as a python plugin to xsim). The simulator -model checks that the signals comply to the spi specification and checks the -protocol speed of the transactions. Tests are run to test the following -features: - - * Transmission of packets - * Reception of packets - -The tests are run with transactions of varying number of bytes and with rx and -tx transactions interleaved. The tests are run at speeds of 10, 100 and 400 -Kbps. -""") - - xmostest.register_group("lib_spi", - "spi_slave_sim_tests", - "spi Slave simulator tests", - """ -Tests are performed by running the spi library connected to a -simulator model (written as a python plugin to xsim). The simulator -model checks that the signals comply to the spi specification and checks the -protocol speed of the transactions. Tests are run to test the following -features: - - * Transmission of packets - * Reception of packets - -The tests are run with transactions of varying number of bytes and with rx and -tx transactions interleaved. The tests are run at speeds of 10, 100 and 400 -Kbps. -""") - - xmostest.runtests() - - xmostest.finish() diff --git a/legacy_tests/slave.expect b/legacy_tests/slave.expect deleted file mode 100644 index 47ba373..0000000 --- a/legacy_tests/slave.expect +++ /dev/null @@ -1 +0,0 @@ -SPI Slave checker started diff --git a/legacy_tests/slave_benchmark.expect b/legacy_tests/slave_benchmark.expect deleted file mode 100644 index 4c3014e..0000000 --- a/legacy_tests/slave_benchmark.expect +++ /dev/null @@ -1,2 +0,0 @@ -SPI Slave checker started -.* diff --git a/legacy_tests/spi_master_async_multi_client/.cproject b/legacy_tests/spi_master_async_multi_client/.cproject deleted file mode 100644 index a52c77f..0000000 --- a/legacy_tests/spi_master_async_multi_client/.cproject +++ /dev/null @@ -1,3385 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Default - all - true - true - true - - - xmake - CONFIG=Default - clean - true - true - true - - - - - diff --git a/legacy_tests/spi_master_async_multi_client/.project b/legacy_tests/spi_master_async_multi_client/.project deleted file mode 100644 index eed8b6e..0000000 --- a/legacy_tests/spi_master_async_multi_client/.project +++ /dev/null @@ -1,47 +0,0 @@ - - - spi_master_async_multi_client - - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.BuildMarkersBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/legacy_tests/spi_master_async_multi_client/.settings/org.eclipse.cdt.core.prefs b/legacy_tests/spi_master_async_multi_client/.settings/org.eclipse.cdt.core.prefs deleted file mode 100644 index 350cef2..0000000 --- a/legacy_tests/spi_master_async_multi_client/.settings/org.eclipse.cdt.core.prefs +++ /dev/null @@ -1,51 +0,0 @@ -eclipse.preferences.version=1 -environment/project/com.xmos.cdt.toolchain.1199496047/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1199496047/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1199496047/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1199496047/append=true -environment/project/com.xmos.cdt.toolchain.1199496047/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1212376291/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1212376291/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1212376291/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1212376291/append=true -environment/project/com.xmos.cdt.toolchain.1212376291/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1278560241/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1278560241/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1278560241/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1278560241/append=true -environment/project/com.xmos.cdt.toolchain.1278560241/appendContributed=true -environment/project/com.xmos.cdt.toolchain.171044913/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.171044913/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.171044913/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.171044913/append=true -environment/project/com.xmos.cdt.toolchain.171044913/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1840686372/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1840686372/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1840686372/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1840686372/append=true -environment/project/com.xmos.cdt.toolchain.1840686372/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1967321160/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1967321160/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1967321160/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1967321160/append=true -environment/project/com.xmos.cdt.toolchain.1967321160/appendContributed=true -environment/project/com.xmos.cdt.toolchain.2145625776/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.2145625776/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.2145625776/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.2145625776/append=true -environment/project/com.xmos.cdt.toolchain.2145625776/appendContributed=true -environment/project/com.xmos.cdt.toolchain.414772137/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.414772137/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.414772137/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.414772137/append=true -environment/project/com.xmos.cdt.toolchain.414772137/appendContributed=true -environment/project/com.xmos.cdt.toolchain.523868563/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.523868563/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.523868563/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.523868563/append=true -environment/project/com.xmos.cdt.toolchain.523868563/appendContributed=true -environment/project/com.xmos.cdt.toolchain.829874614/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.829874614/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.829874614/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.829874614/append=true -environment/project/com.xmos.cdt.toolchain.829874614/appendContributed=true diff --git a/legacy_tests/spi_master_async_multi_client/Makefile b/legacy_tests/spi_master_async_multi_client/Makefile deleted file mode 100644 index dd408f7..0000000 --- a/legacy_tests/spi_master_async_multi_client/Makefile +++ /dev/null @@ -1,42 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = SLICEKIT-A16 -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = spi_master_async_multi_client - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi lib_spi_master_tester - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -COMMON_FLAGS = -O2 -g -Wno-reinterpret-alignment - -XCC_FLAGS_401 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DMOSI_ENABLED=0 -DCOMBINED=1 -XCC_FLAGS_411 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DMOSI_ENABLED=1 -DCOMBINED=1 -XCC_FLAGS_401 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DMOSI_ENABLED=0 -DCOMBINED=1 -XCC_FLAGS_411 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DMOSI_ENABLED=1 -DCOMBINED=1 -XCC_FLAGS_300 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DMOSI_ENABLED=0 -DCOMBINED=0 -XCC_FLAGS_310 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DMOSI_ENABLED=1 -DCOMBINED=0 - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/legacy_tests/spi_master_async_multi_device/.cproject b/legacy_tests/spi_master_async_multi_device/.cproject deleted file mode 100644 index 723082e..0000000 --- a/legacy_tests/spi_master_async_multi_device/.cproject +++ /dev/null @@ -1,3384 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Default - all - true - true - true - - - xmake - CONFIG=Default - clean - true - true - true - - - - diff --git a/legacy_tests/spi_master_async_multi_device/.project b/legacy_tests/spi_master_async_multi_device/.project deleted file mode 100644 index 4deaf24..0000000 --- a/legacy_tests/spi_master_async_multi_device/.project +++ /dev/null @@ -1,47 +0,0 @@ - - - spi_master_async_multi_device - - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - com.xmos.cdt.core.BuildMarkersBuilder - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/legacy_tests/spi_master_async_multi_device/Makefile b/legacy_tests/spi_master_async_multi_device/Makefile deleted file mode 100644 index ba36c44..0000000 --- a/legacy_tests/spi_master_async_multi_device/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = SLICEKIT-A16 -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = spi_master_async_multi_device - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi lib_spi_master_tester - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -COMMON_FLAGS = -O2 -g -Wno-reinterpret-alignment -save-temps - -XCC_FLAGS_20 = $(COMMON_FLAGS) -DBURNT_THREADS=2 -DMOSI_ENABLED=0 -XCC_FLAGS_21 = $(COMMON_FLAGS) -DBURNT_THREADS=2 -DMOSI_ENABLED=1 - -XCC_FLAGS_60 = $(COMMON_FLAGS) -DBURNT_THREADS=6 -DMOSI_ENABLED=0 -XCC_FLAGS_61 = $(COMMON_FLAGS) -DBURNT_THREADS=6 -DMOSI_ENABLED=1 - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/legacy_tests/spi_master_async_rx_tx/.cproject b/legacy_tests/spi_master_async_rx_tx/.cproject deleted file mode 100644 index 3925f17..0000000 --- a/legacy_tests/spi_master_async_rx_tx/.cproject +++ /dev/null @@ -1,13441 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Default - all - true - true - true - - - xmake - CONFIG=Default - clean - true - true - true - - - - - diff --git a/legacy_tests/spi_master_async_rx_tx/.project b/legacy_tests/spi_master_async_rx_tx/.project deleted file mode 100644 index c1ce3b6..0000000 --- a/legacy_tests/spi_master_async_rx_tx/.project +++ /dev/null @@ -1,47 +0,0 @@ - - - spi_master_async_rx_tx - - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - com.xmos.cdt.core.BuildMarkersBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/legacy_tests/spi_master_async_rx_tx/.settings/org.eclipse.cdt.core.prefs b/legacy_tests/spi_master_async_rx_tx/.settings/org.eclipse.cdt.core.prefs deleted file mode 100644 index c8d20c6..0000000 --- a/legacy_tests/spi_master_async_rx_tx/.settings/org.eclipse.cdt.core.prefs +++ /dev/null @@ -1,181 +0,0 @@ -eclipse.preferences.version=1 -environment/project/com.xmos.cdt.toolchain.1010651779/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1010651779/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1010651779/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1010651779/append=true -environment/project/com.xmos.cdt.toolchain.1010651779/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1028334172/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1028334172/XMOS_MODULE_PATH/operation=append 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-environment/project/com.xmos.cdt.toolchain.1071184740/append=true -environment/project/com.xmos.cdt.toolchain.1071184740/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1101745121/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1101745121/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1101745121/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1101745121/append=true -environment/project/com.xmos.cdt.toolchain.1101745121/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1359946757/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1359946757/XMOS_MODULE_PATH/operation=append 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-environment/project/com.xmos.cdt.toolchain.818027705/append=true -environment/project/com.xmos.cdt.toolchain.818027705/appendContributed=true -environment/project/com.xmos.cdt.toolchain.860505498/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.860505498/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.860505498/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.860505498/append=true -environment/project/com.xmos.cdt.toolchain.860505498/appendContributed=true -environment/project/com.xmos.cdt.toolchain.92161155/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.92161155/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.92161155/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.92161155/append=true -environment/project/com.xmos.cdt.toolchain.92161155/appendContributed=true diff --git a/legacy_tests/spi_master_async_rx_tx/Makefile b/legacy_tests/spi_master_async_rx_tx/Makefile deleted file mode 100644 index fe3e714..0000000 --- a/legacy_tests/spi_master_async_rx_tx/Makefile +++ /dev/null @@ -1,55 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = SLICEKIT-A16 -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = spi_master_async_rx_tx - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi lib_spi_master_tester - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -COMMON_FLAGS = -O2 -g -Wno-reinterpret-alignment - -XCC_FLAGS_2010 = $(COMMON_FLAGS) -DBURNT_THREADS=2 -DMOSI_ENABLED=0 -DSPEED_TESTS=1 -DCOMBINED=0 -XCC_FLAGS_2110 = $(COMMON_FLAGS) -DBURNT_THREADS=2 -DMOSI_ENABLED=1 -DSPEED_TESTS=1 -DCOMBINED=0 -XCC_FLAGS_6010 = $(COMMON_FLAGS) -DBURNT_THREADS=6 -DMOSI_ENABLED=0 -DSPEED_TESTS=1 -DCOMBINED=0 -XCC_FLAGS_6110 = $(COMMON_FLAGS) -DBURNT_THREADS=6 -DMOSI_ENABLED=1 -DSPEED_TESTS=1 -DCOMBINED=0 - -XCC_FLAGS_2030 = $(COMMON_FLAGS) -DBURNT_THREADS=2 -DMOSI_ENABLED=0 -DSPEED_TESTS=3 -DCOMBINED=0 -XCC_FLAGS_2130 = $(COMMON_FLAGS) -DBURNT_THREADS=2 -DMOSI_ENABLED=1 -DSPEED_TESTS=3 -DCOMBINED=0 -XCC_FLAGS_6030 = $(COMMON_FLAGS) -DBURNT_THREADS=6 -DMOSI_ENABLED=0 -DSPEED_TESTS=3 -DCOMBINED=0 -XCC_FLAGS_6130 = $(COMMON_FLAGS) -DBURNT_THREADS=6 -DMOSI_ENABLED=1 -DSPEED_TESTS=3 -DCOMBINED=0 - -XCC_FLAGS_3011 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DMOSI_ENABLED=0 -DSPEED_TESTS=1 -DCOMBINED=1 -XCC_FLAGS_3111 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DMOSI_ENABLED=1 -DSPEED_TESTS=1 -DCOMBINED=1 -XCC_FLAGS_7011 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DMOSI_ENABLED=0 -DSPEED_TESTS=1 -DCOMBINED=1 -XCC_FLAGS_7111 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DMOSI_ENABLED=1 -DSPEED_TESTS=1 -DCOMBINED=1 - -XCC_FLAGS_3031 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DMOSI_ENABLED=0 -DSPEED_TESTS=3 -DCOMBINED=1 -XCC_FLAGS_3131 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DMOSI_ENABLED=1 -DSPEED_TESTS=3 -DCOMBINED=1 -XCC_FLAGS_7031 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DMOSI_ENABLED=0 -DSPEED_TESTS=3 -DCOMBINED=1 -XCC_FLAGS_7131 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DMOSI_ENABLED=1 -DSPEED_TESTS=3 -DCOMBINED=1 - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/legacy_tests/spi_master_async_shutdown/Makefile b/legacy_tests/spi_master_async_shutdown/Makefile deleted file mode 100644 index bf0be86..0000000 --- a/legacy_tests/spi_master_async_shutdown/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling - -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = XCORE-200-EXPLORER -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -endif - - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = spi_master_async_shutdown - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi lib_spi_master_tester - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -COMMON_FLAGS = -O2 -g -Wno-reinterpret-alignment - -XCC_FLAGS_0 = $(COMMON_FLAGS) -DCOMBINED=0 -XCC_FLAGS_1 = $(COMMON_FLAGS) -DCOMBINED=1 - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/legacy_tests/spi_master_async_shutdown/src/spi_master_async_shutdown.xc b/legacy_tests/spi_master_async_shutdown/src/spi_master_async_shutdown.xc deleted file mode 100644 index e8233b4..0000000 --- a/legacy_tests/spi_master_async_shutdown/src/spi_master_async_shutdown.xc +++ /dev/null @@ -1,70 +0,0 @@ -// Copyright 2020-2021 XMOS LIMITED. -// This Software is subject to the terms of the XMOS Public Licence: Version 1. -#include -#include -#include -#include -#include -#include "spi.h" -#include "spi_async_tester.h" - -in buffered port:32 p_miso = XS1_PORT_1A; -out port p_ss[1] = {XS1_PORT_1B}; -out buffered port:32 p_sclk = XS1_PORT_1C; -out buffered port:32 p_mosi = XS1_PORT_1D; -clock cb0 = XS1_CLKBLK_1; -clock cb1 = XS1_CLKBLK_2; - -out port setup_strobe_port = XS1_PORT_1E; -out port setup_data_port = XS1_PORT_16B; - -[[combinable]] -void app(client interface spi_master_async_if spi_i, int mosi_enabled, int miso_enabled){ - unsigned inter_frame_gap = 1000; - unsigned device_id = 0; - spi_mode_t mode = SPI_MODE_0; - unsigned speed_in_kbps = 500; - unsigned count = 1; - - broadcast_settings(setup_strobe_port, setup_data_port, - mode, speed_in_kbps, mosi_enabled, miso_enabled, - device_id, inter_frame_gap, count); - - uint8_t tx[1] = {(tx_data, unsigned char[])[0]}; - uint8_t rx[1]; - uint8_t * movable tx_ptr = tx; - uint8_t * movable rx_ptr = rx; - - spi_i.begin_transaction(device_id, speed_in_kbps, mode); - spi_i.init_transfer_array_8(move(rx_ptr), move(tx_ptr), count); - - while(1){ - select { - case spi_i.transfer_complete():{ - spi_i.retrieve_transfer_buffers_8(rx_ptr, tx_ptr); - spi_i.end_transaction(inter_frame_gap); - spi_i.shutdown(); - return; - } - } - } -} - -int main(){ - interface spi_master_async_if i[1]; - for (int j = 0; j < 2; j++) { // go around a couple of times in order to exercise the shutdown - par { -#if COMBINED == 1 - [[combine]] - par { - spi_master_async(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb0, cb1); - app(i[0], 1, 1); - } -#else - spi_master_async(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb0, cb1); - app(i[0], 1, 1); -#endif - } - } - return 0; -} diff --git a/legacy_tests/spi_master_checker.py b/legacy_tests/spi_master_checker.py deleted file mode 100644 index d6f5a96..0000000 --- a/legacy_tests/spi_master_checker.py +++ /dev/null @@ -1,160 +0,0 @@ -# Copyright 2015-2021 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest - -class SPIMasterChecker(xmostest.SimThread): - """" - This simulator thread will act as SPI slave and check any transactions - caused by the master. - """ - def __init__(self, sck_port, mosi_port, miso_port, ss_ports, setup_strobe_port, setup_data_port): - self._miso_port = miso_port - self._mosi_port = mosi_port - self._sck_port = sck_port - self._ss_ports = ss_ports - self._setup_strobe_port = setup_strobe_port - self._setup_data_port = setup_data_port - - def get_setup_data(self, xsi, setup_strobe_port, setup_data_port): - self.wait_for_port_pins_change([setup_strobe_port]) - self.wait_for_port_pins_change([setup_strobe_port]) - return xsi.sample_port_pins(setup_data_port) - - def run(self): - xsi = self.xsi - - sck_value = xsi.sample_port_pins(self._sck_port) - ss_value = [] - - for i in range(len(self._ss_ports)): - ss_value.append(xsi.sample_port_pins(self._ss_ports[i])) - - print "SPI Master checker started" - while True: - #first do the setup rx - strobe_val = xsi.sample_port_pins(self._setup_strobe_port) - if strobe_val == 1: - self.wait_for_port_pins_change([self._setup_strobe_port]) - - expected_cpol = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - expected_cpha = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - expected_frequency_in_khz = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - expected_mosi_enabled = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - expected_miso_enabled = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - expected_device_id = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - expected_interframe_space = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - expected_num_bytes = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - - clock_half_period = 1000000/(expected_frequency_in_khz*2) - - all_ss_deserted = True - for i in range(len(self._ss_ports)): - if (xsi.sample_port_pins(self._ss_ports[i]) == 0): - all_ss_deserted = False - break - - while not all_ss_deserted: - self.wait_for_port_pins_change(self._ss_ports) - all_ss_deserted = True - for i in range(len(self._ss_ports)): - all_ss_deserted = all_ss_deserted and (xsi.sample_port_pins(self._ss_ports[i]) == 1) - - error = False - - active_slave = -1 - - while(active_slave == -1): - self.wait_for_port_pins_change(self._ss_ports) - - for i in range(len(self._ss_ports)): - if xsi.sample_port_pins(self._ss_ports[i]) == 0: - active_slave = i - break - - - last_clock_event_time = xsi.get_time(); - - rx_bit_counter = 0 - tx_bit_counter = 0 - tx_data = [0xfe, 0xf7, 0xfb, 0xef, 0xdf, 0xbf, 0xfd, 0x7f, 0x01, 0x08, 0x04, 0x10, 0x20, 0x04, 0x02, 0x80] - rx_data = [0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x04, 0x80, 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f] - rx_byte = 0 - tx_byte = tx_data[0] - # check the polarity - if xsi.sample_port_pins(self._sck_port) != expected_cpol: - print("ERROR: unexpected clock polarity at the slave select point") - error = True - clock_edge_number = 0 - - #probably not physically possible but good for testing - if expected_cpha == 0: - xsi.drive_port_pins(self._miso_port, (tx_byte>>7)&1) - tx_bit_counter += 1 - tx_byte = tx_byte << 1 - - ss_value = xsi.sample_port_pins(self._ss_ports[active_slave]) - sck_value = xsi.sample_port_pins(self._sck_port) - - while ss_value == 0: - self.wait_for_port_pins_change(self._ss_ports + [self._sck_port]) - - for i in range(len(self._ss_ports)): - if i != active_slave and xsi.sample_port_pins(self._ss_ports[i]) == 0: - error = True - print "Second slave selected during first transaction" - - if (ss_value == xsi.sample_port_pins(self._ss_ports[active_slave]) and (sck_value == xsi.sample_port_pins(self._sck_port))): - continue - - ss_value = xsi.sample_port_pins(self._ss_ports[active_slave]) - sck_value = xsi.sample_port_pins(self._sck_port) - - if ss_value == 0: - clock_event_time = xsi.get_time(); - measured_time_elapsed = clock_event_time - last_clock_event_time - if clock_edge_number > 1 and (measured_time_elapsed*1.05) < clock_half_period : - print("ERROR: Clock half period less than allowed for given SCLK frequency" ) - print("%d %d " % (measured_time_elapsed, clock_half_period)) - error = True - last_clock_event_time =clock_event_time - - #check that the clock edges never go faster than the expected clock rate - if ss_value == 0: - clock_edge_number += 1 - #print clock_edge_number - #the the clock must have transitioned - if sck_value == (expected_cpha ^ expected_cpol): - if expected_miso_enabled == 1: - #drive data out - xsi.drive_port_pins(self._miso_port, (tx_byte>>7)&1) - tx_bit_counter += 1 - tx_byte = tx_byte << 1 - if (tx_bit_counter%8) == 0: - index = tx_bit_counter/8 - if index < 16: - tx_byte = tx_data[tx_bit_counter/8] - else: - tx_byte = 0; - - else: - #clock data in - if expected_mosi_enabled == 1: - rx_byte = rx_byte << 1 - rx_byte += xsi.sample_port_pins(self._mosi_port) - rx_bit_counter = rx_bit_counter + 1 - if((rx_bit_counter%8) == 0): - expected_rx_byte = rx_data[(rx_bit_counter/8) - 1] - #print "slave got {seen} and expected {expect}".format(seen=rx_byte, expect=expected_rx_byte) - if expected_rx_byte != rx_byte: - print "ERROR: slave recieved incorrect data Got:%02x Expected:%02x"%(rx_byte, expected_rx_byte) - error = True - rx_byte = 0 - else: - if clock_edge_number != expected_num_bytes*2*8: - error = True - print "ERROR: incorrect number of clock edges at slave {seen}/{expect}".format(seen=clock_edge_number, expect=expected_num_bytes*2*8) - if error: - print "Fail: CPOL:{cpol} CPHA:{cpha} KHz:{freq} MOSI Enabled:{mosi_enabled} MISO Enabled:{miso_enabled}".format( - cpol=expected_cpol, cpha=expected_cpha, - mosi_enabled = expected_mosi_enabled, miso_enabled = expected_miso_enabled, - freq=expected_frequency_in_khz) diff --git a/legacy_tests/spi_master_sync_benchmark/.cproject b/legacy_tests/spi_master_sync_benchmark/.cproject deleted file mode 100644 index 0a15b19..0000000 --- a/legacy_tests/spi_master_sync_benchmark/.cproject +++ /dev/null @@ -1,10088 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Default - all - true - true - true - - - xmake - CONFIG=Default - clean - true - true - true - - - - diff --git a/legacy_tests/spi_master_sync_benchmark/.project b/legacy_tests/spi_master_sync_benchmark/.project deleted file mode 100644 index b9b73fc..0000000 --- a/legacy_tests/spi_master_sync_benchmark/.project +++ /dev/null @@ -1,47 +0,0 @@ - - - spi_master_sync_benchmark - - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - com.xmos.cdt.core.BuildMarkersBuilder - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/legacy_tests/spi_master_sync_benchmark/Makefile b/legacy_tests/spi_master_sync_benchmark/Makefile deleted file mode 100644 index d84b971..0000000 --- a/legacy_tests/spi_master_sync_benchmark/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = SLICEKIT-A16 -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = spi_master_sync_benchmark - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi lib_spi_master_tester - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -COMMON_FLAGS = -O2 -g -Wno-reinterpret-alignment - -XCC_FLAGS_3010 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_3110 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_3001 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=0 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_3101 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=1 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_3011 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 -XCC_FLAGS_3111 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 - -XCC_FLAGS_7010 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_7110 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_7001 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=0 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_7101 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=1 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_7011 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 -XCC_FLAGS_7111 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/legacy_tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc b/legacy_tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc deleted file mode 100644 index cf79bfb..0000000 --- a/legacy_tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc +++ /dev/null @@ -1,121 +0,0 @@ -// Copyright 2015-2021 XMOS LIMITED. -// This Software is subject to the terms of the XMOS Public Licence: Version 1. -#include -#include -#include -#include -#include "spi.h" - -in buffered port:32 p_miso = XS1_PORT_1A; -out port p_ss[1] = {XS1_PORT_1B}; -out buffered port:32 p_sclk = XS1_PORT_1C; -out buffered port:32 p_mosi = XS1_PORT_1D; -clock cb = XS1_CLKBLK_1; - -out port setup_strobe_port = XS1_PORT_1E; -out port setup_data_port = XS1_PORT_16B; - -static unsigned get_max_byte_speed(client interface spi_master_if i){ - unsigned now, then; - timer t; - t:> then; - i.begin_transaction(0, 100, SPI_MODE_3); - i.transfer8(0xff); - i.end_transaction(100); - t:> now; - unsigned best_time_so_far = now-then; - unsigned min = 0000, max = 6000; - while(1){ - //unsigned test_speed = (min + max)/2; - unsigned test_speed = min + (max-min)/32; - t:> then; - i.begin_transaction(0, test_speed, SPI_MODE_3); - i.transfer8(test_speed); - i.end_transaction(100); - t:> now; - if(now-then < best_time_so_far){ - best_time_so_far = (now-then); - min = test_speed; - } else { - if(max == test_speed) - return test_speed; - max = test_speed; - } - } - return 1000; -} - -static unsigned get_max_word_speed(client interface spi_master_if i){ - unsigned now, then; - timer t; - t:> then; - i.begin_transaction(0, 100, SPI_MODE_3); - i.transfer32(0xff); - i.transfer32(0xff); - i.end_transaction(100); - t:> now; - unsigned best_time_so_far = now-then; - unsigned min = 0000, max = 6000; - while(1){ - //unsigned test_speed = (min + max)/2; - unsigned test_speed = min + (max-min)/32; - t:> then; - i.begin_transaction(0, test_speed, SPI_MODE_3); - i.transfer32(0xff); - i.transfer32(0xff); - i.end_transaction(100); - t:> now; - if(now-then < best_time_so_far){ - best_time_so_far = (now-then); - min = test_speed; - } else { - if(max == test_speed) - return test_speed; - max = test_speed; - } - } - return 1000; -} - -void app(client interface spi_master_if i, int mosi_enabled, int miso_enabled){ - printf("%d\n", get_max_byte_speed(i)); - printf("%d\n", get_max_word_speed(i)); - _Exit(1); -} - -static void load(static const unsigned num_threads){ - switch(num_threads){ - case 3: par {par(int i=0;i<3;i++) while(1);}break; - case 4: par {par(int i=0;i<4;i++) while(1);}break; - case 5: par {par(int i=0;i<5;i++) while(1);}break; - case 6: par {par(int i=0;i<6;i++) while(1);}break; - case 7: par {par(int i=0;i<7;i++) while(1);}break; - } -} -#if MOSI_ENABLED -#define MOSI p_mosi -#else -#define MOSI null -#endif - -#if MISO_ENABLED -#define MISO p_miso -#else -#define MISO null -#endif - -#if CB_ENABLED -#define CB cb -#else -#define CB null -#endif - -int main(){ - interface spi_master_if i[1]; - par { - spi_master(i, 1, p_sclk, MOSI, MISO, p_ss, 1, CB); - app(i[0], MOSI_ENABLED, MISO_ENABLED); - load(BURNT_THREADS); - } - return 0; -} diff --git a/legacy_tests/spi_master_sync_clock_port_sharing/Makefile b/legacy_tests/spi_master_sync_clock_port_sharing/Makefile deleted file mode 100644 index d69943d..0000000 --- a/legacy_tests/spi_master_sync_clock_port_sharing/Makefile +++ /dev/null @@ -1,38 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = XCORE-200-EXPLORER -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = spi_master_sync_clock_port_sharing - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi lib_spi_master_tester - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -COMMON_FLAGS = -O2 -g -Wno-reinterpret-alignment - -XCC_FLAGS_0 = $(COMMON_FLAGS) -DCOMBINED=0 -XCC_FLAGS_1 = $(COMMON_FLAGS) -DCOMBINED=1 - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/legacy_tests/spi_master_sync_multi_client/.cproject b/legacy_tests/spi_master_sync_multi_client/.cproject deleted file mode 100644 index 32ef84f..0000000 --- a/legacy_tests/spi_master_sync_multi_client/.cproject +++ /dev/null @@ -1,24363 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Default - all - true - true - true - - - xmake - CONFIG=Default - clean - true - true - true - - - - diff --git a/legacy_tests/spi_master_sync_multi_client/.project b/legacy_tests/spi_master_sync_multi_client/.project deleted file mode 100644 index 4a0a4b4..0000000 --- a/legacy_tests/spi_master_sync_multi_client/.project +++ /dev/null @@ -1,47 +0,0 @@ - - - spi_master_sync_multi_client - - - - - - com.xmos.cdt.core.BuildMarkersBuilder - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/legacy_tests/spi_master_sync_multi_client/Makefile b/legacy_tests/spi_master_sync_multi_client/Makefile deleted file mode 100644 index 830c92e..0000000 --- a/legacy_tests/spi_master_sync_multi_client/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = SLICEKIT-A16 -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = spi_master_sync_multi_client - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi lib_spi_master_tester - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -COMMON_FLAGS = -O2 -g -Wno-reinterpret-alignment - -XCC_FLAGS_3010 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_3110 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_3001 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=0 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_3101 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=1 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_3011 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 -XCC_FLAGS_3111 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 - -XCC_FLAGS_4010 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_4110 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_4001 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DCB_ENABLED=0 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_4101 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DCB_ENABLED=1 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_4011 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 -XCC_FLAGS_4111 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 - - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/legacy_tests/spi_master_sync_multi_device/.cproject b/legacy_tests/spi_master_sync_multi_device/.cproject deleted file mode 100644 index 6066327..0000000 --- a/legacy_tests/spi_master_sync_multi_device/.cproject +++ /dev/null @@ -1,25172 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Default - all - true - true - true - - - xmake - CONFIG=Default - clean - true - true - true - - - - diff --git a/legacy_tests/spi_master_sync_multi_device/.project b/legacy_tests/spi_master_sync_multi_device/.project deleted file mode 100644 index 4527cde..0000000 --- a/legacy_tests/spi_master_sync_multi_device/.project +++ /dev/null @@ -1,47 +0,0 @@ - - - spi_master_sync_multi_device - - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - com.xmos.cdt.core.BuildMarkersBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/legacy_tests/spi_master_sync_multi_device/Makefile b/legacy_tests/spi_master_sync_multi_device/Makefile deleted file mode 100644 index c5e3933..0000000 --- a/legacy_tests/spi_master_sync_multi_device/Makefile +++ /dev/null @@ -1,70 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = SLICEKIT-A16 -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = spi_master_sync_multi_device - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi lib_spi_master_tester - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -COMMON_FLAGS = -O2 -g -Wno-reinterpret-alignment - -XCC_FLAGS_3010 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_3110 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_3001 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=0 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_3101 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=1 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_3011 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 -XCC_FLAGS_3111 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 - -XCC_FLAGS_4010 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_4110 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_4001 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DCB_ENABLED=0 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_4101 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DCB_ENABLED=1 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_4011 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 -XCC_FLAGS_4111 = $(COMMON_FLAGS) -DBURNT_THREADS=4 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 - -XCC_FLAGS_5010 = $(COMMON_FLAGS) -DBURNT_THREADS=5 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_5110 = $(COMMON_FLAGS) -DBURNT_THREADS=5 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_5001 = $(COMMON_FLAGS) -DBURNT_THREADS=5 -DCB_ENABLED=0 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_5101 = $(COMMON_FLAGS) -DBURNT_THREADS=5 -DCB_ENABLED=1 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_5011 = $(COMMON_FLAGS) -DBURNT_THREADS=5 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 -XCC_FLAGS_5111 = $(COMMON_FLAGS) -DBURNT_THREADS=5 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 - -XCC_FLAGS_6010 = $(COMMON_FLAGS) -DBURNT_THREADS=6 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_6110 = $(COMMON_FLAGS) -DBURNT_THREADS=6 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_6001 = $(COMMON_FLAGS) -DBURNT_THREADS=6 -DCB_ENABLED=0 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_6101 = $(COMMON_FLAGS) -DBURNT_THREADS=6 -DCB_ENABLED=1 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_6011 = $(COMMON_FLAGS) -DBURNT_THREADS=6 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 -XCC_FLAGS_6111 = $(COMMON_FLAGS) -DBURNT_THREADS=6 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 - -XCC_FLAGS_7010 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_7110 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_7001 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=0 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_7101 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=1 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_7011 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 -XCC_FLAGS_7111 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/legacy_tests/spi_master_sync_rx_tx/.cproject b/legacy_tests/spi_master_sync_rx_tx/.cproject deleted file mode 100644 index ee966f1..0000000 --- a/legacy_tests/spi_master_sync_rx_tx/.cproject +++ /dev/null @@ -1,10089 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Default - all - true - true - true - - - xmake - CONFIG=Default - clean - true - true - true - - - - - diff --git a/legacy_tests/spi_master_sync_rx_tx/.project b/legacy_tests/spi_master_sync_rx_tx/.project deleted file mode 100644 index f2f5e56..0000000 --- a/legacy_tests/spi_master_sync_rx_tx/.project +++ /dev/null @@ -1,47 +0,0 @@ - - - spi_master_sync_rx_tx - - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - com.xmos.cdt.core.BuildMarkersBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/legacy_tests/spi_master_sync_rx_tx/.settings/org.eclipse.cdt.core.prefs b/legacy_tests/spi_master_sync_rx_tx/.settings/org.eclipse.cdt.core.prefs deleted file mode 100644 index 5833210..0000000 --- a/legacy_tests/spi_master_sync_rx_tx/.settings/org.eclipse.cdt.core.prefs +++ /dev/null @@ -1,151 +0,0 @@ -eclipse.preferences.version=1 -environment/project/com.xmos.cdt.toolchain.1231577380/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1231577380/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1231577380/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1231577380/append=true -environment/project/com.xmos.cdt.toolchain.1231577380/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1387236138/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1387236138/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1387236138/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1387236138/append=true -environment/project/com.xmos.cdt.toolchain.1387236138/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1393389046/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1393389046/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1393389046/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1393389046/append=true -environment/project/com.xmos.cdt.toolchain.1393389046/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1554768118/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1554768118/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1554768118/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1554768118/append=true -environment/project/com.xmos.cdt.toolchain.1554768118/appendContributed=true -environment/project/com.xmos.cdt.toolchain.157309736/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.157309736/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.157309736/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.157309736/append=true -environment/project/com.xmos.cdt.toolchain.157309736/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1758977626/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1758977626/XMOS_MODULE_PATH/operation=append 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-environment/project/com.xmos.cdt.toolchain.195986837/append=true -environment/project/com.xmos.cdt.toolchain.195986837/appendContributed=true -environment/project/com.xmos.cdt.toolchain.200711552/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.200711552/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.200711552/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.200711552/append=true -environment/project/com.xmos.cdt.toolchain.200711552/appendContributed=true -environment/project/com.xmos.cdt.toolchain.276149167/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.276149167/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.276149167/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.276149167/append=true -environment/project/com.xmos.cdt.toolchain.276149167/appendContributed=true -environment/project/com.xmos.cdt.toolchain.301703194/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.301703194/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.301703194/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.301703194/append=true -environment/project/com.xmos.cdt.toolchain.301703194/appendContributed=true -environment/project/com.xmos.cdt.toolchain.348765327/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.348765327/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.348765327/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.348765327/append=true -environment/project/com.xmos.cdt.toolchain.348765327/appendContributed=true -environment/project/com.xmos.cdt.toolchain.384528648/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.384528648/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.384528648/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.384528648/append=true -environment/project/com.xmos.cdt.toolchain.384528648/appendContributed=true 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-environment/project/com.xmos.cdt.toolchain.429094660/append=true -environment/project/com.xmos.cdt.toolchain.429094660/appendContributed=true -environment/project/com.xmos.cdt.toolchain.447588288/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.447588288/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.447588288/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.447588288/append=true -environment/project/com.xmos.cdt.toolchain.447588288/appendContributed=true -environment/project/com.xmos.cdt.toolchain.463337427/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.463337427/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.463337427/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.463337427/append=true -environment/project/com.xmos.cdt.toolchain.463337427/appendContributed=true -environment/project/com.xmos.cdt.toolchain.467260874/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.467260874/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.467260874/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.467260874/append=true -environment/project/com.xmos.cdt.toolchain.467260874/appendContributed=true -environment/project/com.xmos.cdt.toolchain.490950526/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.490950526/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.490950526/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.490950526/append=true -environment/project/com.xmos.cdt.toolchain.490950526/appendContributed=true -environment/project/com.xmos.cdt.toolchain.516132272/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.516132272/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.516132272/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.516132272/append=true -environment/project/com.xmos.cdt.toolchain.516132272/appendContributed=true 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-environment/project/com.xmos.cdt.toolchain.732275761/append=true -environment/project/com.xmos.cdt.toolchain.732275761/appendContributed=true -environment/project/com.xmos.cdt.toolchain.737049460/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.737049460/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.737049460/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.737049460/append=true -environment/project/com.xmos.cdt.toolchain.737049460/appendContributed=true -environment/project/com.xmos.cdt.toolchain.738746398/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.738746398/XMOS_MODULE_PATH/operation=append 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-environment/project/com.xmos.cdt.toolchain.989279270/append=true -environment/project/com.xmos.cdt.toolchain.989279270/appendContributed=true diff --git a/legacy_tests/spi_master_sync_rx_tx/Makefile b/legacy_tests/spi_master_sync_rx_tx/Makefile deleted file mode 100644 index ce87696..0000000 --- a/legacy_tests/spi_master_sync_rx_tx/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = SLICEKIT-A16 -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = spi_master_sync_rx_tx - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi lib_spi_master_tester - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -COMMON_FLAGS = -O2 -g -Wno-reinterpret-alignment -save-temps - -XCC_FLAGS_3010 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_3110 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_3001 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=0 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_3101 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=1 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_3011 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 -XCC_FLAGS_3111 = $(COMMON_FLAGS) -DBURNT_THREADS=3 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 - -XCC_FLAGS_7010 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_7110 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=0 -XCC_FLAGS_7001 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=0 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_7101 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=1 -DMISO_ENABLED=0 -DMOSI_ENABLED=1 -XCC_FLAGS_7011 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=0 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 -XCC_FLAGS_7111 = $(COMMON_FLAGS) -DBURNT_THREADS=7 -DCB_ENABLED=1 -DMISO_ENABLED=1 -DMOSI_ENABLED=1 - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/legacy_tests/spi_slave_benchmark/.cproject b/legacy_tests/spi_slave_benchmark/.cproject deleted file mode 100644 index 2d4cbd1..0000000 --- a/legacy_tests/spi_slave_benchmark/.cproject +++ /dev/null @@ -1,52897 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Default - all - true - true - true - - - xmake - CONFIG=Default - clean - true - true - true - - - - - diff --git a/legacy_tests/spi_slave_benchmark/.project b/legacy_tests/spi_slave_benchmark/.project deleted file mode 100644 index 6818e6f..0000000 --- a/legacy_tests/spi_slave_benchmark/.project +++ /dev/null @@ -1,47 +0,0 @@ - - - spi_slave_benchmark - - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - com.xmos.cdt.core.BuildMarkersBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/legacy_tests/spi_slave_benchmark/.settings/org.eclipse.cdt.core.prefs b/legacy_tests/spi_slave_benchmark/.settings/org.eclipse.cdt.core.prefs deleted file mode 100644 index e9b0869..0000000 --- a/legacy_tests/spi_slave_benchmark/.settings/org.eclipse.cdt.core.prefs +++ /dev/null @@ -1,321 +0,0 @@ -eclipse.preferences.version=1 -environment/project/com.xmos.cdt.toolchain.1033470973/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1033470973/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1033470973/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1033470973/append=true -environment/project/com.xmos.cdt.toolchain.1033470973/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1049848630/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1049848630/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1049848630/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1049848630/append=true -environment/project/com.xmos.cdt.toolchain.1049848630/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1087889181/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1087889181/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1087889181/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1087889181/append=true -environment/project/com.xmos.cdt.toolchain.1087889181/appendContributed=true -environment/project/com.xmos.cdt.toolchain.110219323/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.110219323/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.110219323/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.110219323/append=true -environment/project/com.xmos.cdt.toolchain.110219323/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1116542288/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1116542288/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1116542288/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1116542288/append=true -environment/project/com.xmos.cdt.toolchain.1116542288/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1119227038/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1119227038/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1119227038/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1119227038/append=true -environment/project/com.xmos.cdt.toolchain.1119227038/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1119664378/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1119664378/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1119664378/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1119664378/append=true -environment/project/com.xmos.cdt.toolchain.1119664378/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1171448777/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1171448777/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1171448777/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1171448777/append=true -environment/project/com.xmos.cdt.toolchain.1171448777/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1226083515/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1226083515/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1226083515/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1226083515/append=true -environment/project/com.xmos.cdt.toolchain.1226083515/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1236831555/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1236831555/XMOS_MODULE_PATH/operation=append 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-environment/project/com.xmos.cdt.toolchain.1309711942/append=true -environment/project/com.xmos.cdt.toolchain.1309711942/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1320692830/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1320692830/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1320692830/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1320692830/append=true -environment/project/com.xmos.cdt.toolchain.1320692830/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1330706362/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1330706362/XMOS_MODULE_PATH/operation=append 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-environment/project/com.xmos.cdt.toolchain.990543979/append=true -environment/project/com.xmos.cdt.toolchain.990543979/appendContributed=true diff --git a/legacy_tests/spi_slave_benchmark/Makefile b/legacy_tests/spi_slave_benchmark/Makefile deleted file mode 100644 index 82c70b3..0000000 --- a/legacy_tests/spi_slave_benchmark/Makefile +++ /dev/null @@ -1,108 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = SLICEKIT-A16 -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = spi_slave_benchmark - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -COMMON_FLAGS = -O2 -g -Wno-reinterpret-alignment -save-temps - -XCC_FLAGS_02108 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02008 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02118 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02018 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02128 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02028 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02138 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02038 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 - -XCC_FLAGS_021032 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_020032 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_021132 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_020132 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_021232 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_020232 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_021332 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_020332 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 - -XCC_FLAGS_06108 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06008 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06118 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06018 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06128 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06028 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06138 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06038 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 - -XCC_FLAGS_061032 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_060032 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_061132 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_060132 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_061232 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_060232 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_061332 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_060332 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 - -XCC_FLAGS_13108 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13008 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13118 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13018 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13128 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13028 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13138 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13038 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 - -XCC_FLAGS_131032 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_130032 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_131132 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_130132 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_131232 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_130232 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_131332 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_130332 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 - -XCC_FLAGS_17108 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17008 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17118 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17018 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17128 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17028 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17138 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17038 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 - -XCC_FLAGS_171032 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_170032 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_171132 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_170132 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_171232 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_170232 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_171332 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_170332 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 - - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/legacy_tests/spi_slave_checker.py b/legacy_tests/spi_slave_checker.py deleted file mode 100644 index 3ee36b2..0000000 --- a/legacy_tests/spi_slave_checker.py +++ /dev/null @@ -1,105 +0,0 @@ -# Copyright 2015-2021 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest - -class SPISlaveChecker(xmostest.SimThread): - """" - This simulator thread will act as SPI slave and check any transactions - caused by the master. - """ - def __init__(self, sck_port, mosi_port, miso_port, ss_port, setup_strobe_port, setup_data_port, setup_resp_port): - self._miso_port = miso_port - self._mosi_port = mosi_port - self._sck_port = sck_port - self._ss_port = ss_port - self._setup_strobe_port = setup_strobe_port - self._setup_data_port = setup_data_port - self._setup_resp_port = setup_resp_port - - def get_setup_data(self, xsi, setup_strobe_port, setup_data_port): - self.wait_for_port_pins_change([setup_strobe_port]) - self.wait_for_port_pins_change([setup_strobe_port]) - return xsi.sample_port_pins(setup_data_port) - - def run(self): - xsi = self.xsi - - sck_value = xsi.sample_port_pins(self._sck_port) - ss_value = xsi.sample_port_pins(self._ss_port) - xsi.drive_port_pins(self._ss_port,1) - - print "SPI Slave checker started" - while True: - #first do the setup rx - strobe_val = xsi.sample_port_pins(self._setup_strobe_port) - if strobe_val == 1: - self.wait_for_port_pins_change([self._setup_strobe_port]) - - expected_cpol = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - xsi.drive_port_pins(self._sck_port, expected_cpol) - expected_cpha = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - expected_miso_enabled = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - expected_num_bits = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - kbps = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - initial_clock_delay = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) - - self.wait_until(xsi.get_time() + 10000) - xsi.drive_port_pins(self._ss_port, 0) - self.wait_until(xsi.get_time() + initial_clock_delay) - tx_data = [0xaa, 0xf7, 0xfb, 0xef, 0xdf, 0xbf, 0xfd, 0x7f, 0x01, 0x08, 0x04, 0x10, 0x20, 0x04, 0x02, 0x80] - rx_data = [0xaa, 0x02, 0x04, 0x08, 0x10, 0x20, 0x04, 0x80, 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f] - rx_byte = 0 - tx_byte = tx_data[0] - - #set the first data on the mosi for the case where there is no clock edge - xsi.drive_port_pins(self._mosi_port, (tx_byte>>7)&1) - - ss_value = xsi.sample_port_pins(self._ss_port) - sck_value = xsi.sample_port_pins(self._sck_port) - - clock_val = (expected_cpol^expected_cpha)&1 - bit_count = 0 - total_bit_count = 0 - byte_count = 0 - - half_clock = 1000000/(2*kbps) - error = 0 - - while total_bit_count < expected_num_bits: - #clock edge and drive data out - xsi.drive_port_pins(self._sck_port, clock_val) - xsi.drive_port_pins(self._mosi_port,(tx_byte>>7)&1) - tx_byte = tx_byte<<1 - self.wait_until(xsi.get_time() + half_clock) - - #clockedge and read data in - xsi.drive_port_pins(self._sck_port, 1-clock_val) - val = xsi.sample_port_pins(self._miso_port) - self.wait_until(xsi.get_time() + half_clock) - rx_byte = (rx_byte<<1) + val - bit_count = bit_count + 1 - total_bit_count = total_bit_count + 1 - if bit_count == 8: - bit_count = 0 - if expected_miso_enabled: - if rx_byte != rx_data[byte_count]: - error = 1 - #print "rx got:%02x expected:%02x %d" % (rx_byte,rx_data[byte_count], byte_count) - rx_byte = 0 - byte_count = byte_count + 1 - if byte_count*8 < expected_num_bits: - tx_byte = tx_data[byte_count] - - #check the final few rx'd bits - if bit_count and expected_miso_enabled: - if rx_byte != rx_data[byte_count]>>(8-bit_count): - error = 1 - #print "sub bit rx got:%02x expected:%02x %d" % (rx_byte,rx_data[byte_count]>>(8-bit_count), byte_count) - self.wait_until(xsi.get_time() + half_clock) - - xsi.drive_port_pins(self._sck_port, expected_cpol) - xsi.drive_port_pins(self._ss_port, 1) - - self.wait_for_port_pins_change([self._setup_strobe_port]) - xsi.drive_port_pins(self._setup_resp_port, error) - self.wait_for_port_pins_change([self._setup_strobe_port]) diff --git a/legacy_tests/spi_slave_rx_tx/.cproject b/legacy_tests/spi_slave_rx_tx/.cproject deleted file mode 100644 index 1424324..0000000 --- a/legacy_tests/spi_slave_rx_tx/.cproject +++ /dev/null @@ -1,52897 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Default - all - true - true - true - - - xmake - CONFIG=Default - clean - true - true - true - - - - - diff --git a/legacy_tests/spi_slave_rx_tx/.project b/legacy_tests/spi_slave_rx_tx/.project deleted file mode 100644 index e9d7d69..0000000 --- a/legacy_tests/spi_slave_rx_tx/.project +++ /dev/null @@ -1,47 +0,0 @@ - - - spi_slave_rx_tx - - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - com.xmos.cdt.core.BuildMarkersBuilder - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/legacy_tests/spi_slave_rx_tx/.settings/org.eclipse.cdt.core.prefs b/legacy_tests/spi_slave_rx_tx/.settings/org.eclipse.cdt.core.prefs deleted file mode 100644 index d355de5..0000000 --- a/legacy_tests/spi_slave_rx_tx/.settings/org.eclipse.cdt.core.prefs +++ /dev/null @@ -1,321 +0,0 @@ -eclipse.preferences.version=1 -environment/project/com.xmos.cdt.toolchain.1015056818/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1015056818/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1015056818/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1015056818/append=true -environment/project/com.xmos.cdt.toolchain.1015056818/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1080753062/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1080753062/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1080753062/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1080753062/append=true -environment/project/com.xmos.cdt.toolchain.1080753062/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1089041030/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1089041030/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1089041030/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1089041030/append=true -environment/project/com.xmos.cdt.toolchain.1089041030/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1130118063/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1130118063/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1130118063/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1130118063/append=true -environment/project/com.xmos.cdt.toolchain.1130118063/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1165201921/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1165201921/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1165201921/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1165201921/append=true -environment/project/com.xmos.cdt.toolchain.1165201921/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1165566074/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1165566074/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1165566074/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1165566074/append=true -environment/project/com.xmos.cdt.toolchain.1165566074/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1195371953/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1195371953/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1195371953/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1195371953/append=true -environment/project/com.xmos.cdt.toolchain.1195371953/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1262012374/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1262012374/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1262012374/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1262012374/append=true -environment/project/com.xmos.cdt.toolchain.1262012374/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1293766331/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1293766331/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1293766331/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1293766331/append=true -environment/project/com.xmos.cdt.toolchain.1293766331/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1308824189/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1308824189/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1308824189/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1308824189/append=true -environment/project/com.xmos.cdt.toolchain.1308824189/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1321565156/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1321565156/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.1321565156/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.1321565156/append=true -environment/project/com.xmos.cdt.toolchain.1321565156/appendContributed=true -environment/project/com.xmos.cdt.toolchain.141915059/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.141915059/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.141915059/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.141915059/append=true -environment/project/com.xmos.cdt.toolchain.141915059/appendContributed=true -environment/project/com.xmos.cdt.toolchain.1441179566/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.1441179566/XMOS_MODULE_PATH/operation=append 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-environment/project/com.xmos.cdt.toolchain.676749111/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.676749111/append=true -environment/project/com.xmos.cdt.toolchain.676749111/appendContributed=true -environment/project/com.xmos.cdt.toolchain.676883664/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.676883664/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.676883664/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.676883664/append=true -environment/project/com.xmos.cdt.toolchain.676883664/appendContributed=true -environment/project/com.xmos.cdt.toolchain.678776223/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.678776223/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.678776223/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.678776223/append=true -environment/project/com.xmos.cdt.toolchain.678776223/appendContributed=true -environment/project/com.xmos.cdt.toolchain.680214508/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.680214508/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.680214508/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.680214508/append=true -environment/project/com.xmos.cdt.toolchain.680214508/appendContributed=true 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-environment/project/com.xmos.cdt.toolchain.750974751/append=true -environment/project/com.xmos.cdt.toolchain.750974751/appendContributed=true -environment/project/com.xmos.cdt.toolchain.77010454/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.77010454/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.77010454/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.77010454/append=true -environment/project/com.xmos.cdt.toolchain.77010454/appendContributed=true -environment/project/com.xmos.cdt.toolchain.779850310/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.779850310/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.779850310/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.779850310/append=true -environment/project/com.xmos.cdt.toolchain.779850310/appendContributed=true -environment/project/com.xmos.cdt.toolchain.798597172/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.798597172/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.798597172/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.798597172/append=true -environment/project/com.xmos.cdt.toolchain.798597172/appendContributed=true -environment/project/com.xmos.cdt.toolchain.863428765/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.863428765/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.863428765/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.863428765/append=true -environment/project/com.xmos.cdt.toolchain.863428765/appendContributed=true -environment/project/com.xmos.cdt.toolchain.912638989/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.912638989/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.912638989/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.912638989/append=true -environment/project/com.xmos.cdt.toolchain.912638989/appendContributed=true -environment/project/com.xmos.cdt.toolchain.932144966/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.932144966/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.932144966/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.932144966/append=true -environment/project/com.xmos.cdt.toolchain.932144966/appendContributed=true -environment/project/com.xmos.cdt.toolchain.969988333/XMOS_MODULE_PATH/delimiter=\: -environment/project/com.xmos.cdt.toolchain.969988333/XMOS_MODULE_PATH/operation=append -environment/project/com.xmos.cdt.toolchain.969988333/XMOS_MODULE_PATH/value=/home/andrew/new_ip_testing/class_d_test\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi\:/home/andrew/sandboxes/swapps/lib_spi/lib_spi_master_tester -environment/project/com.xmos.cdt.toolchain.969988333/append=true -environment/project/com.xmos.cdt.toolchain.969988333/appendContributed=true diff --git a/legacy_tests/spi_slave_rx_tx/Makefile b/legacy_tests/spi_slave_rx_tx/Makefile deleted file mode 100644 index 73ea857..0000000 --- a/legacy_tests/spi_slave_rx_tx/Makefile +++ /dev/null @@ -1,109 +0,0 @@ -# The TARGET variable determines what target system the application is -# compiled for. It either refers to an XN file in the source directories -# or a valid argument for the --target option when compiling - -XCOREAI ?= 0 -ifeq ($(XCOREAI),0) -TARGET = SLICEKIT-A16 -else -# Use `xmake XCOREAI=1` -TARGET = XCORE-AI-EXPLORER -endif - -# The APP_NAME variable determines the name of the final .xe file. It should -# not include the .xe postfix. If left blank the name will default to -# the project name -APP_NAME = spi_slave_rx_tx - -# The USED_MODULES variable lists other module used by the application. -USED_MODULES = lib_spi - -# The flags passed to xcc when building the application -# You can also set the following to override flags for a particular language: -# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS -# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to -# xcc for the final link (mapping) stage. -COMMON_FLAGS = -O2 -g -Wno-reinterpret-alignment -save-temps - -XCC_FLAGS_02108 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02008 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02118 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02018 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02128 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02028 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02138 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_02038 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 - -XCC_FLAGS_021032 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_020032 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_021132 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_020132 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_021232 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_020232 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_021332 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_020332 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=2 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 - -XCC_FLAGS_06108 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06008 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06118 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06018 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06128 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06028 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06138 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_06038 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 - -XCC_FLAGS_061032 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_060032 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_061132 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_060132 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_061232 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_060232 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_061332 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_060332 = $(COMMON_FLAGS) -DCOMBINED=0 -DBURNT_THREADS=6 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 - -XCC_FLAGS_13108 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13008 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13118 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13018 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13128 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13028 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13138 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_13038 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 - -XCC_FLAGS_131032 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_130032 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_131132 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_130132 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_131232 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_130232 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_131332 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_130332 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=3 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 - -XCC_FLAGS_17108 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17008 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17118 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17018 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17128 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17028 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17138 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 -XCC_FLAGS_17038 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_8 - -XCC_FLAGS_171032 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_170032 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_0 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_171132 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_170132 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_1 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_171232 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_170232 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_2 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_171332 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=1 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 -XCC_FLAGS_170332 = $(COMMON_FLAGS) -DCOMBINED=1 -DBURNT_THREADS=7 -DMISO_ENABLED=0 -DSPI_MODE=SPI_MODE_3 -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_32 - - -# The XCORE_ARM_PROJECT variable, if set to 1, configures this -# project to create both xCORE and ARM binaries. -XCORE_ARM_PROJECT = 0 - -# The VERBOSE variable, if set to 1, enables verbose output from the make system. -VERBOSE = 0 - -XMOS_MAKE_PATH ?= ../.. --include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common diff --git a/legacy_tests/spi_slave_rx_tx/config.xscope b/legacy_tests/spi_slave_rx_tx/config.xscope deleted file mode 100644 index 1ba0f11..0000000 --- a/legacy_tests/spi_slave_rx_tx/config.xscope +++ /dev/null @@ -1,3 +0,0 @@ - - - diff --git a/legacy_tests/test_master_async_multi_client.py b/legacy_tests/test_master_async_multi_client.py deleted file mode 100644 index 8714e2c..0000000 --- a/legacy_tests/test_master_async_multi_client.py +++ /dev/null @@ -1,38 +0,0 @@ -#!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest -from spi_master_checker import SPIMasterChecker -import os - - -def do_multi_client_async(burnt_threads, mosi_enable, combine): - resources = xmostest.request_resource("xsim") - - binary = "spi_master_async_multi_client/bin/{burnt}{mosi}{combined}/spi_master_async_multi_client_{burnt}{mosi}{combined}.xe".format(burnt=burnt_threads,mosi=mosi_enable, combined=combine) - - checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", - "tile[0]:XS1_PORT_1D", - "tile[0]:XS1_PORT_1A", - ["tile[0]:XS1_PORT_1B"], - "tile[0]:XS1_PORT_1E", - "tile[0]:XS1_PORT_16B") - - tester = xmostest.ComparisonTester(open('master.expect'), - 'lib_spi', - 'spi_master_sim_tests', - 'multi_client_async_{burnt}{mosi}{combined}'.format(burnt=burnt_threads, mosi=mosi_enable, combined=combine), - regexp=True) - tester.set_min_testlevel('nightly') - xmostest.run_on_simulator(resources['xsim'], binary, - simthreads = [checker], - #simargs=['--vcd-tracing', '-o ./spi_master_async_multi_client/trace.vcd -tile tile[0] -pads -functions'], - simargs=[], - suppress_multidrive_messages = False, - tester = tester) - -def runtest(): - burnt_threads = 3 - for mosi_enabled in [0, 1]: - for combine in [0, 1]: - do_multi_client_async(burnt_threads+combine, mosi_enabled, combine) diff --git a/legacy_tests/test_master_async_multi_device.py b/legacy_tests/test_master_async_multi_device.py deleted file mode 100644 index d817883..0000000 --- a/legacy_tests/test_master_async_multi_device.py +++ /dev/null @@ -1,38 +0,0 @@ -#!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest -from spi_master_checker import SPIMasterChecker -import os - - -def do_multi_device_async(burnt_threads, mosi_enable): - resources = xmostest.request_resource("xsim") - - binary = "spi_master_async_multi_device/bin/{burnt}{mosi}/spi_master_async_multi_device_{burnt}{mosi}.xe".format(burnt=burnt_threads,mosi=mosi_enable) - - checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", - "tile[0]:XS1_PORT_1D", - "tile[0]:XS1_PORT_1A", - ["tile[0]:XS1_PORT_1B", "tile[0]:XS1_PORT_1G"], - "tile[0]:XS1_PORT_1E", - "tile[0]:XS1_PORT_16B") - - tester = xmostest.ComparisonTester(open('master.expect'), - 'lib_spi', - 'spi_master_sim_tests', - 'spi_master_async_multi_device_{burnt}{mosi}'.format(burnt=burnt_threads, mosi=mosi_enable), - regexp=True) - - tester.set_min_testlevel('nightly') - xmostest.run_on_simulator(resources['xsim'], binary, - simthreads = [checker], - #simargs=['--vcd-tracing', '-o ./spi_master_async_multi_device/trace.vcd -tile tile[0] -pads -functions'], - simargs=[], - suppress_multidrive_messages = False, - tester = tester) - -def runtest(): - for burnt_threads in [2, 6]: - for mosi_enabled in [0, 1]: - do_multi_device_async(burnt_threads, mosi_enabled) diff --git a/legacy_tests/test_master_async_rx_tx.py b/legacy_tests/test_master_async_rx_tx.py deleted file mode 100644 index f3b1099..0000000 --- a/legacy_tests/test_master_async_rx_tx.py +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest -from spi_master_checker import SPIMasterChecker -import os - - -def do_rx_tx_async(burnt_threads, mosi_enable, speed_tests, combine, testlevel): - resources = xmostest.request_resource("xsim") - - binary = "spi_master_async_rx_tx/bin/{burnt}{mosi}{speed}{combined}/spi_master_async_rx_tx_{burnt}{mosi}{speed}{combined}.xe".format(burnt=burnt_threads,mosi=mosi_enable, combined=combine, speed=speed_tests) - - - checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", - "tile[0]:XS1_PORT_1D", - "tile[0]:XS1_PORT_1A", - ["tile[0]:XS1_PORT_1B"], - "tile[0]:XS1_PORT_1E", - "tile[0]:XS1_PORT_16B") - - tester = xmostest.ComparisonTester(open('master.expect'), - 'lib_spi', - 'spi_master_sim_tests', - 'spi_master_async_rx_tx_{burnt}{mosi}{speed}{combined}'.format(burnt=burnt_threads,mosi=mosi_enable, combined=combine, speed=speed_tests), - regexp=True) - - tester.set_min_testlevel(testlevel) - xmostest.run_on_simulator(resources['xsim'], binary, - simthreads = [checker], - simargs=[], - timeout=1200, - tester = tester) - -def runtest(): - for mosi_enabled in [0, 1]: - do_rx_tx_async(6 + 1, mosi_enabled, 1, 1, "smoke") - - for burnt_threads in [2, 6]: - for combined in [0, 1]: - for mosi_enabled in [0, 1]: - do_rx_tx_async(burnt_threads + combined, mosi_enabled, 1, combined, "nightly") diff --git a/legacy_tests/test_master_async_shutdown.py b/legacy_tests/test_master_async_shutdown.py deleted file mode 100644 index 090eaef..0000000 --- a/legacy_tests/test_master_async_shutdown.py +++ /dev/null @@ -1,40 +0,0 @@ -#!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest -from spi_master_checker import SPIMasterChecker -import os - - -def do_shutdown_async(combine, testlevel): - resources = xmostest.request_resource("xsim") - - binary = "spi_master_async_shutdown/bin/{combined}/spi_master_async_shutdown_{combined}.xe".format(combined=combine) - - - checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", - "tile[0]:XS1_PORT_1D", - "tile[0]:XS1_PORT_1A", - ["tile[0]:XS1_PORT_1B"], - "tile[0]:XS1_PORT_1E", - "tile[0]:XS1_PORT_16B") - - tester = xmostest.ComparisonTester(open('master.expect'), - 'lib_spi', - 'spi_master_sim_tests', - 'spi_master_async_shutdown_{combined}'.format(combined=combine), - regexp=True) - - tester.set_min_testlevel(testlevel) - xmostest.run_on_simulator(resources['xsim'], binary, - simthreads = [checker], - simargs=[], - timeout=1200, - tester = tester) - -def runtest(): - # do_shutdown_async(1, "smoke") - - # for combined in [0, 1]: - # do_shutdown_async(combined, "nightly") - pass \ No newline at end of file diff --git a/legacy_tests/test_master_sync_benchmark.py b/legacy_tests/test_master_sync_benchmark.py deleted file mode 100644 index d64f928..0000000 --- a/legacy_tests/test_master_sync_benchmark.py +++ /dev/null @@ -1,41 +0,0 @@ -#!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest -from spi_master_checker import SPIMasterChecker -import os - - -def do_benchmark_sync(burnt_threads, cb_enabled, miso_enabled, mosi_enable): - resources = xmostest.request_resource("xsim") - - binary = "spi_master_sync_benchmark/bin/{burnt}{cb}{miso}{mosi}/spi_master_sync_benchmark_{burnt}{cb}{miso}{mosi}.xe".format(burnt=burnt_threads,cb=cb_enabled,miso=miso_enabled,mosi=mosi_enable) - - - checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", - "tile[0]:XS1_PORT_1D", - "tile[0]:XS1_PORT_1A", - ["tile[0]:XS1_PORT_1B"], - "tile[0]:XS1_PORT_1E", - "tile[0]:XS1_PORT_16B") - - tester = xmostest.ComparisonTester(open('master_benchmark.expect'), - 'lib_spi', - 'spi_master_sim_tests', - 'spi_master_sync_benchmark_{burnt}{cb}{miso}{mosi}'.format(burnt=burnt_threads,cb=cb_enabled,miso=miso_enabled,mosi=mosi_enable), - regexp=True) - - tester.set_min_testlevel('nightly') - xmostest.run_on_simulator(resources['xsim'], binary, - simthreads = [checker], - simargs=[], - suppress_multidrive_messages = False, - tester = tester) - -def runtest(): - for burnt_threads in [3, 7]: - for cb_enabled in [0, 1]: - for miso_enabled in [0, 1]: - for mosi_enabled in [0, 1]: - if (miso_enabled==1 or (miso_enabled==1)): - do_benchmark_sync(burnt_threads, cb_enabled, miso_enabled, mosi_enabled) diff --git a/legacy_tests/test_master_sync_clock_port_sharing.py b/legacy_tests/test_master_sync_clock_port_sharing.py deleted file mode 100644 index e14b0bb..0000000 --- a/legacy_tests/test_master_sync_clock_port_sharing.py +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest -from spi_master_checker import SPIMasterChecker -import os - -def do_clock_port_sharing(combine, testlevel): - resources = xmostest.request_resource("xsim") - - binary = "spi_master_sync_clock_port_sharing/bin/{combined}/spi_master_sync_clock_port_sharing_{combined}.xe".format(combined=combine) - - checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", - "tile[0]:XS1_PORT_1D", - "tile[0]:XS1_PORT_1A", - ["tile[0]:XS1_PORT_1B"], - "tile[0]:XS1_PORT_1E", - "tile[0]:XS1_PORT_16B") - - tester = xmostest.ComparisonTester(open('master.expect'), - 'lib_spi', - 'spi_master_sim_tests', - 'spi_master_sync_clock_port_sharing_{combined}'.format(combined=combine), - regexp=True) - - tester.set_min_testlevel(testlevel) - xmostest.run_on_simulator(resources['xsim'], binary, - simthreads = [checker], - simargs=[], - timeout=1200, - tester = tester) - -def runtest(): - do_clock_port_sharing(1, "smoke") - do_clock_port_sharing(0, "nightly") diff --git a/legacy_tests/test_master_sync_multi_client.py b/legacy_tests/test_master_sync_multi_client.py deleted file mode 100644 index 4d8b0ec..0000000 --- a/legacy_tests/test_master_sync_multi_client.py +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest -from spi_master_checker import SPIMasterChecker -import os - - -def do_multi_client_sync(burnt_threads, cb_enabled, miso_enabled, mosi_enable): - resources = xmostest.request_resource("xsim") - - binary = "spi_master_sync_multi_client/bin/{burnt}{cb}{miso}{mosi}/spi_master_sync_multi_client_{burnt}{cb}{miso}{mosi}.xe".format(burnt=burnt_threads,cb=cb_enabled,miso=miso_enabled,mosi=mosi_enable) - - - checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", - "tile[0]:XS1_PORT_1D", - "tile[0]:XS1_PORT_1A", - ["tile[0]:XS1_PORT_1B"], - "tile[0]:XS1_PORT_1E", - "tile[0]:XS1_PORT_16B") - - tester = xmostest.ComparisonTester(open('master.expect'), - 'lib_spi', - 'spi_master_sim_tests', - 'spi_master_sync_multi_client_{burnt}{cb}{miso}{mosi}'.format(burnt=burnt_threads,cb=cb_enabled,miso=miso_enabled,mosi=mosi_enable), - regexp=True) - - tester.set_min_testlevel('nightly') - xmostest.run_on_simulator(resources['xsim'], binary, - simthreads = [checker], - #simargs=['--vcd-tracing', '-o ./spi_master_sync_multi_client/trace.vcd -tile tile[0] -pads -functions'], - simargs=[], - suppress_multidrive_messages = False, - tester = tester) - -def runtest(): - for burnt_threads in [3, 4]: - for cb_enabled in [0, 1]: - for miso_enabled in [0, 1]: - for mosi_enabled in [0, 1]: - if (miso_enabled==1 or (miso_enabled==1)): - do_multi_client_sync(burnt_threads, cb_enabled, miso_enabled, mosi_enabled) diff --git a/legacy_tests/test_master_sync_multi_device.py b/legacy_tests/test_master_sync_multi_device.py deleted file mode 100644 index 4f2ae50..0000000 --- a/legacy_tests/test_master_sync_multi_device.py +++ /dev/null @@ -1,41 +0,0 @@ -#!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest -from spi_master_checker import SPIMasterChecker -import os - - -def do_multi_device_sync(burnt_threads, cb_enabled, miso_enabled, mosi_enable): - resources = xmostest.request_resource("xsim") - - binary = "spi_master_sync_multi_device/bin/{burnt}{cb}{miso}{mosi}/spi_master_sync_multi_device_{burnt}{cb}{miso}{mosi}.xe".format(burnt=burnt_threads,cb=cb_enabled,miso=miso_enabled,mosi=mosi_enable) - - checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", - "tile[0]:XS1_PORT_1D", - "tile[0]:XS1_PORT_1A", - ["tile[0]:XS1_PORT_1B", "tile[0]:XS1_PORT_1G"], - "tile[0]:XS1_PORT_1E", - "tile[0]:XS1_PORT_16B") - - tester = xmostest.ComparisonTester(open('master.expect'), - 'lib_spi', - 'spi_master_sim_tests', - 'spi_master_sync_multi_device_{burnt}{cb}{miso}{mosi}'.format(burnt=burnt_threads,cb=cb_enabled,miso=miso_enabled,mosi=mosi_enable), - regexp=True) - - tester.set_min_testlevel('nightly') - xmostest.run_on_simulator(resources['xsim'], binary, - simthreads = [checker], - #simargs=['--vcd-tracing', '-o ./spi_master_sync_multi_device/trace.vcd -tile tile[0] -pads -functions'], - simargs=[], - suppress_multidrive_messages = False, - tester = tester) - -def runtest(): - for burnt_threads in [3, 7]: - for cb_enabled in [0, 1]: - for miso_enabled in [0, 1]: - for mosi_enabled in [0, 1]: - if (miso_enabled==1 or (miso_enabled==1)): - do_multi_device_sync(burnt_threads, cb_enabled, miso_enabled, mosi_enabled) diff --git a/legacy_tests/test_master_sync_rx_tx.py b/legacy_tests/test_master_sync_rx_tx.py deleted file mode 100644 index 80b03e8..0000000 --- a/legacy_tests/test_master_sync_rx_tx.py +++ /dev/null @@ -1,45 +0,0 @@ -#!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest -from spi_master_checker import SPIMasterChecker -import os - - -def do_rx_tx_sync(burnt_threads, cb_enabled, miso_enabled, mosi_enable, testlevel): - resources = xmostest.request_resource("xsim") - - binary = "spi_master_sync_rx_tx/bin/{burnt}{cb}{miso}{mosi}/spi_master_sync_rx_tx_{burnt}{cb}{miso}{mosi}.xe".format(burnt=burnt_threads,cb=cb_enabled,miso=miso_enabled,mosi=mosi_enable) - - - checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", - "tile[0]:XS1_PORT_1D", - "tile[0]:XS1_PORT_1A", - ["tile[0]:XS1_PORT_1B"], - "tile[0]:XS1_PORT_1E", - "tile[0]:XS1_PORT_16B") - - tester = xmostest.ComparisonTester(open('master.expect'), - 'lib_spi', - 'spi_master_sim_tests', - 'spi_master_sync_rx_tx_{burnt}{cb}{miso}{mosi}'.format(burnt=burnt_threads,cb=cb_enabled,miso=miso_enabled,mosi=mosi_enable), - regexp=True) - - tester.set_min_testlevel(testlevel) - xmostest.run_on_simulator(resources['xsim'], binary, - simthreads = [checker], - simargs=[], - suppress_multidrive_messages = False, - tester = tester) - -def runtest(): - for cb_enabled in [0, 1]: - for miso_enabled in [0, 1]: - for mosi_enabled in [0, 1]: - if (miso_enabled==1 or (miso_enabled==1)): - do_rx_tx_sync(3, cb_enabled, miso_enabled, mosi_enabled, "smoke") - for cb_enabled in [0, 1]: - for miso_enabled in [0, 1]: - for mosi_enabled in [0, 1]: - if (miso_enabled==1 or (miso_enabled==1)): - do_rx_tx_sync(7, cb_enabled, miso_enabled, mosi_enabled, "nightly") diff --git a/legacy_tests/test_slave_benchmark.py b/legacy_tests/test_slave_benchmark.py deleted file mode 100644 index f8fb4bd..0000000 --- a/legacy_tests/test_slave_benchmark.py +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest -from spi_slave_checker import SPISlaveChecker -import os - - -def do_slave_benchmark(combined, burnt_threads, miso_enable, mode, transfer_size): - resources = xmostest.request_resource("xsim") - - binary = "spi_slave_benchmark/bin/{com}{burnt}{miso}{m}{t}/spi_slave_benchmark_{com}{burnt}{miso}{m}{t}.xe".format(com=combined,burnt=burnt_threads,miso=miso_enable,m=mode,t=transfer_size) - - checker = SPISlaveChecker("tile[0]:XS1_PORT_1C", - "tile[0]:XS1_PORT_1D", - "tile[0]:XS1_PORT_1A", - "tile[0]:XS1_PORT_1B", - "tile[0]:XS1_PORT_1E", - "tile[0]:XS1_PORT_16B", - "tile[0]:XS1_PORT_1F") - - tester = xmostest.ComparisonTester(open('slave_benchmark.expect'), - 'lib_spi', - 'spi_slave_sim_tests', - 'spi_slave_benchmark_{com}{burnt}{miso}{m}{t}.xe'.format(com=combined,burnt=burnt_threads,miso=miso_enable,m=mode,t=transfer_size), - regexp=True) - - tester.set_min_testlevel('nightly') - xmostest.run_on_simulator(resources['xsim'], binary, - simthreads = [checker], - #simargs=['--vcd-tracing', '-o ./spi_slave_benchmark/trace.vcd -tile tile[0] -pads -functions -clock-blocks -ports-detailed -instructions'], - simargs=[], - suppress_multidrive_messages = False, - tester = tester) - -def runtest(): - for combined in [0,1]: - for mode in range(0, 4): - for burnt_threads in [2, 6]: - for transfer_size in [8, 32]: - for miso_enable in [0, 1]: - do_slave_benchmark(combined, burnt_threads+combined, miso_enable, mode, transfer_size) diff --git a/legacy_tests/test_slave_rx_tx.py b/legacy_tests/test_slave_rx_tx.py deleted file mode 100644 index 04c0211..0000000 --- a/legacy_tests/test_slave_rx_tx.py +++ /dev/null @@ -1,49 +0,0 @@ -#!/usr/bin/env python -# Copyright 2015-2021 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import xmostest -from spi_slave_checker import SPISlaveChecker -import os - - -def do_slave_rx_tx(combined, burnt_threads, miso_enable, mode, transfer_size, testlevel): - - resources = xmostest.request_resource("xsim") - - binary = "spi_slave_rx_tx/bin/{com}{burnt}{miso}{m}{t}/spi_slave_rx_tx_{com}{burnt}{miso}{m}{t}.xe".format(com=combined,burnt=burnt_threads,miso=miso_enable,m=mode,t=transfer_size) - - checker = SPISlaveChecker("tile[0]:XS1_PORT_1C", - "tile[0]:XS1_PORT_1D", - "tile[0]:XS1_PORT_1A", - "tile[0]:XS1_PORT_1B", - "tile[0]:XS1_PORT_1E", - "tile[0]:XS1_PORT_16B", - "tile[0]:XS1_PORT_1F") - - tester = xmostest.ComparisonTester(open('slave.expect'), - 'lib_spi', - 'spi_slave_sim_tests', - 'rx_tx_slave_{com}{burnt}{miso}{m}{t}.xe'.format(com=combined,burnt=burnt_threads,miso=miso_enable,m=mode,t=transfer_size), - {'combined': combined, 'burnt_threads': burnt_threads, 'miso_enable': miso_enable, 'mode': mode, 'transfer_size': transfer_size}, - regexp=True) - - tester.set_min_testlevel(testlevel) - - xmostest.run_on_simulator(resources['xsim'], binary, - simthreads = [checker], - #simargs=['--vcd-tracing', '-o ./spi_slave_rx_tx/trace.vcd -tile tile[0] -pads -functions -clock-blocks -ports-detailed -instructions'], - simargs=[], - suppress_multidrive_messages = False, - tester = tester) - -def runtest(): - for transfer_size in [8, 32]: - for miso_enable in [0, 1]: - do_slave_rx_tx(1, 2+1, miso_enable, 3, transfer_size, "smoke") - - for combined in [0,1]: - for mode in range(0, 4): - for burnt_threads in [2, 6]: - for transfer_size in [8, 32]: - for miso_enable in [0, 1]: - do_slave_rx_tx(combined, burnt_threads+combined, miso_enable, mode, transfer_size, "nightly") diff --git a/lib_spi/.cproject b/lib_spi/.cproject deleted file mode 100644 index e8f0fb8..0000000 --- a/lib_spi/.cproject +++ /dev/null @@ -1,970 +0,0 @@ - - - - - - - - - - - - - - - - - xmake - -f .makefile - all - true - true - true - - - xmake - -f .makefile - clean - true - true - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/lib_spi/.makefile b/lib_spi/.makefile deleted file mode 100644 index 87b347b..0000000 --- a/lib_spi/.makefile +++ /dev/null @@ -1,8 +0,0 @@ -all: - @echo "** Module only - only builds as part of application **" - - -clean: - @echo "** Module only - only builds as part of application **" - - diff --git a/lib_spi/.project b/lib_spi/.project deleted file mode 100644 index 31270d3..0000000 --- a/lib_spi/.project +++ /dev/null @@ -1,95 +0,0 @@ - - - lib_spi - - - - - - com.xmos.cdt.core.ProjectInfoSyncBuilder - - - - - com.xmos.cdt.core.LegacyProjectCheckerBuilder - - - - - com.xmos.cdt.core.ModulePathBuilder - - - - - com.xmos.cdt.core.BuildMarkersBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?children? - ?name?=outputEntries\|?children?=?name?=entry\\\\|\\|\|| - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.buildArguments - CONFIG=Debug - - - org.eclipse.cdt.make.core.buildCommand - xmake - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - false - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.xmos.cdt.core.XdeProjectNature - - diff --git a/lib_spi/LICENSE.rst b/lib_spi/LICENSE.rst deleted file mode 100644 index ca48f20..0000000 --- a/lib_spi/LICENSE.rst +++ /dev/null @@ -1,84 +0,0 @@ -******************************* -XMOS PUBLIC LICENCE: Version 1 -******************************* - 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The Licence shall be governed by the laws of England and the conflict of laws and UN Convention on Contracts for the International Sale of Goods, shall not apply. diff --git a/lib_spi/api/spi.h b/lib_spi/api/spi.h index e3314f9..2309a99 100644 --- a/lib_spi/api/spi.h +++ b/lib_spi/api/spi.h @@ -1,319 +1,63 @@ -// Copyright 2014-2021 XMOS LIMITED. +// Copyright 2014-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #ifndef _spi_h_ #define _spi_h_ #include #include #include - -/** This type indicates what mode an SPI component should use */ +#include +extern "C" { + #include "../src/spi_fwk.h" +} +// These are needed for DOXYGEN to render properly +#ifndef __DOXYGEN__ +#define static_const_unsigned static const unsigned +#define static_const_size_t static const size_t +#define out_port out port +#define in_port in port +#define static_const_size_t static const size_t +#define static_const_spi_mode_t static const spi_mode_t +#define static_const_spi_transfer_type_t static const spi_transfer_type_t +#define uint32_t_movable_ptr_t uint32_t * movable +#define uint8_t_movable_ptr_t uint8_t * movable +#endif + +/** This type indicates what clocking mode a SPI component should use */ typedef enum spi_mode_t { - SPI_MODE_0, /**< SPI Mode 0 - Polarity = 0, Clock Edge = 1 */ - SPI_MODE_1, /**< SPI Mode 1 - Polarity = 0, Clock Edge = 0 */ - SPI_MODE_2, /**< SPI Mode 2 - Polarity = 1, Clock Edge = 0 */ - SPI_MODE_3, /**< SPI Mode 3 - Polarity = 1, Clock Edge = 1 */ + SPI_MODE_0 = 0, /**< SPI Mode 0 - Polarity = 0, Phase = 0 */ + SPI_MODE_1 = 1, /**< SPI Mode 1 - Polarity = 0, Phase = 1 */ + SPI_MODE_2 = 2, /**< SPI Mode 2 - Polarity = 1, Phase = 0 */ + SPI_MODE_3 = 3, /**< SPI Mode 3 - Polarity = 1, Phase = 1 */ } spi_mode_t; -/** This interface allows clients to interact with SPI master task. */ -typedef interface spi_master_if { - - /** Begin a transaction. - * - * This will start a transaction on the bus. During a transaction, no - * other client to the SPI component can send or receive data. If - * another client is currently using the component then this call - * will block until the bus is released. - * - * \param device_index the index of the slave device to interact with. - * \param speed_in_khz The speed that the SPI bus should run at during - * the transaction (in kHZ). - * \param mode The mode of spi transfers during this transaction. - */ - [[guarded]] - void begin_transaction(unsigned device_index, - unsigned speed_in_khz, spi_mode_t mode); - - /** End a transaction. - * - * This ends a transaction on the bus and releases the component to other - * clients. - * - * \param ss_deassert_time The minimum time in reference clock ticks between - * assertions of the selected slave select. This - * time will be ignored if the next transaction is - * to a different slave select. - */ - void end_transaction(unsigned ss_deassert_time); - - /** Transfer a byte over the spi bus. - * - * This function will transmit and receive 8 bits of data over the SPI - * bus. The data will be transmitted least-significant bit first. - * - * \param data the data to transmit the MOSI port. - * - * \returns the data read in from the MISO port. - */ - uint8_t transfer8(uint8_t data); - - /** Transfer a 32-bit word over the spi bus. - * - * This function will transmit and receive 32 bits of data over the SPI - * bus. The data will be transmitted least-significant bit first. - * - * \param data the data to transmit the MOSI port. - * - * \returns the data read in from the MISO port. - */ - uint32_t transfer32(uint32_t data); -} spi_master_if; - -/** Task that implements the SPI proctocol in master mode that is - connected to a multiple slaves on the bus. - - Each slave must be connected to using the same SPI mode. - - You can access different slave devices over the interface connection - using the device_index parameter of the interface functions. - The task will allocate the device indices in the order of the supplied - array of slave select ports. - - \param i an array of interface connection to the - clients of the task. - \param num_clients the number of clients connected to the task. - \param clk a clock block used by the task. - \param sclk the SPI clock port. - \param mosi the SPI MOSI (master out, slave in) port. - \param miso the SPI MISO (master in, slave out) port. - \param p_ss an array of ports connected to the slave select signals - of the slave. - \param num_slaves The number of slave devices on the bus. - \param clk a clock for the component to use. -*/ -[[distributable]] -void spi_master(server interface spi_master_if i[num_clients], - static const size_t num_clients, - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 ?miso, - out port p_ss[num_slaves], - static const size_t num_slaves, - clock ?clk); - -/** Asynchronous interface to an SPI component. - * - * This interface allows programs to offload SPI bus transfers to another - * task. An asynchronous notification occurs when the transfer is complete. - */ -typedef interface spi_master_async_if { - /** Begin a transaction. - * - * This will start a transaction on the bus. During a transaction, no - * other client to the SPI component can send or receive data. If - * another client is currently using the component then this call - * will block until the bus is released. - * - * \param device_index the index of the slave device to interact with. - * \param speed_in_khz The speed that the SPI bus should run at during - * the transaction (in kHZ) - * \param mode The mode of spi transfers during this transaction - */ - void begin_transaction(unsigned device_index, - unsigned speed_in_khz, spi_mode_t mode); - - /** End a transaction. - * - * This ends a transaction on the bus and releases the component to other - * clients. - * - * \param ss_deassert_time The minimum time in reference clock ticks between - * assertions of the selected slave select. This - * time will be ignored if the next transaction is - * to a different slave select. - */ - void end_transaction(unsigned ss_deassert_time); - - /** Initialize Transfer an array of bytes over the spi bus. - * - * This function will initialize a transmit of 8 bit data - * over the SPI bus. - * - * \param inbuf A *movable* pointer that is moved to the other task - * pointing to the buffer area to fill with data. If this - * parameter is NULL then the incoming data of the transfer - * will be discarded. - * \param outbuf A *movable* pointer that is moved to the other task - * pointing to the buffer area to with data to transmit. - * If this parameter is NULL then the outgoing data of the - * transfer will consist of undefined values. - * \param nbytes The number of bytes to transfer over the bus. - */ - void init_transfer_array_8(uint8_t * movable inbuf, - uint8_t * movable outbuf, - size_t nbytes); - - /** Initialize Transfer an array of bytes over the spi bus. - * - * This function will initialize a transmit of 32 bit data - * over the SPI bus. - * - * \param inbuf A *movable* pointer that is moved to the other task - * pointing to the buffer area to fill with data. If this - * parameter is NULL then the incoming data of the transfer - * will be discarded. - * \param outbuf A *movable* pointer that is moved to the other task - * pointing to the buffer area to with data to transmit. - * If this parameter is NULL then the outgoing data of the - * transfer will consist of undefined values. - * \param nwords The number of words to transfer over the bus. - */ - void init_transfer_array_32(uint32_t * movable inbuf, - uint32_t * movable outbuf, - size_t nwords); - - - /** Transfer completed notification. - * - * This notification occurs when a transfer is completed. - */ - [[notification]] - slave void transfer_complete(void); - - /** Retrieve transfer buffers. - * - * This function should be called after the transfer_complete() notification - * and will return the buffers given to the other task by - * init_transfer_array_8(). - * - * \param inbuf A movable pointer that will be set to the buffer - * pointer that was filled during the transfer. - * \param outbuf A movable pointer that will be set to the buffer - * pointer that was transmitted during the transfer. - */ - [[clears_notification]] - void retrieve_transfer_buffers_8(uint8_t * movable &inbuf, - uint8_t * movable &outbuf); - - - /** Retrieve transfer buffers. - * - * This function should be called after the transfer_complete() notification - * and will return the buffers given to the other task by - * init_transfer_array_32(). - * - * \param inbuf A movable pointer that will be set to the buffer - * pointer that was filled during the transfer. - * \param outbuf A movable pointer that will be set to the buffer - * pointer that was transmitted during the transfer. - */ - [[clears_notification]] - void retrieve_transfer_buffers_32(uint32_t * movable &inbuf, - uint32_t * movable &outbuf); - - /** Shut down the interface server. - */ - void shutdown(void); -} spi_master_async_if; - - -/** SPI master component for asynchronous API. - * - * This component implements SPI and allows a client to connect using the - * asynchronous SPI master interface. - * - * \param i an array of interface connection to the - * clients of the task. - * \param num_clients the number of clients connected to the task. - * \param sclk the SPI clock port. - * \param mosi the SPI MOSI (master out, slave in) port. - * \param miso the SPI MISO (master in, slave out) port. - * \param p_ss an array of ports connected to the slave select signals - * of the slave. - * \param num_slaves The number of slave devices on the bus. - * \param clk0 a clock for the component to use. - * \param clk1 a clock for the component to use. - */ -[[combinable]] -void spi_master_async(server interface spi_master_async_if i[num_clients], - static const size_t num_clients, - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 miso, - out port p_ss[num_slaves], - static const size_t num_slaves, - clock clk0, - clock clk1); - -/**** SLAVE ****/ - -/** This interface allows clients to interact with SPI slave tasks by - * completing callbacks that show how to handle data. - */ -typedef interface spi_slave_callback_if { - - /** This callback will get called when the master de-asserts on the slave - * select line to end a transaction. - */ - void master_ends_transaction(void); - - /** This callback will get called when the master initiates a bus transfer - * or when more data is required during a transaction. - * The application must supply the data to transmit to the master. If - * the spi slave component is set to ``SPI_TRANSFER_SIZE_32`` mode then - * this callback will not be called and master_requires_data32() will - * be called instead. Data is transmitted for the least significant bit - * first. If the master completes the transaction before 8 bits are - * transferred the remaining bits are discarded. - * - * \returns the 8-bit value to transmit. - */ - uint32_t master_requires_data(void); - - /** This callback will get called after a transfer. It will occur after - * every 8 bits transferred if the slave component is set to - * ``SPI_TRANSFER_SIZE_8``. If the component is set to - * ``SPI_TRANSFER_SIZE_32`` then it will occur if the master ends the - * transaction before 32 bits are transferred. - * - * \param datum the data received from the master. - * \param valid_bits the number of valid bits of data received from the master. - */ - void master_supplied_data(uint32_t datum, uint32_t valid_bits); - -} spi_slave_callback_if; - -/** This type specifies the transfer size from the SPI slave component - to the application */ -typedef enum spi_transfer_type_t { - SPI_TRANSFER_SIZE_8, ///< Transfers should by 8-bit. - SPI_TRANSFER_SIZE_32 ///< Transfers should be 32-bit. -} spi_transfer_type_t; - -/** SPI slave component. - * - * This function implements an SPI slave bus. - * - * \param spi_i The interface to connect to the user of the component. - * The component acts as the client and will make callbacks to - * the application. - * \param p_sclk the SPI clock port. - * \param p_mosi the SPI MOSI (master out, slave in) port. - * \param p_miso the SPI MISO (master in, slave out) port. - * \param p_ss the SPI SS (slave select) port. - * \param clk clock to be used by the component. - * \param mode the SPI mode of the bus. - * \param transfer_type the type of transfer the slave will perform: either - * ``SPI_TRANSFER_SIZE_8`` or ``SPI_TRANSFER_SIZE_32``. - */ - [[combinable]] - void spi_slave(client spi_slave_callback_if spi_i, - in port p_sclk, - in buffered port:32 p_mosi, - out buffered port:32 ?p_miso, - in port p_ss, - clock clk, - static const spi_mode_t mode, - static const spi_transfer_type_t transfer_type); +/** This type contains timing settings for SS assert to clock delay and last + * clock to SS de-assert delay. The unit is reference timer ticks which is + * nominally 10 ns. The maximum setting is 65535 which equates to 655 us, + * over which the setting will overflow back to zero */ +typedef struct spi_master_ss_clock_timing_t { + uint32_t cs_to_clk_delay_ticks; + uint32_t clk_to_cs_delay_ticks; +} spi_master_ss_clock_timing_t; + + +/** This type contains timing settings for capturing the MISO pin for SPI master. + * When the SPI clock is above 20MHz it is usually necessary to delay the + * sampling of the MISO pin. These settings can be coarse grained using + * miso_sample_delay setting which increments in SPI half clocks or + * fine grained in units of core clock (eg. 600 MHz -> 1.66 ns) using the + * miso_pad_delay setting. + * + * See the following document for details on xcore.ai port timing: + * https://www.xmos.com/documentation/XM-014231-AN/html/rst/index.html */ +typedef struct spi_master_miso_capture_timing_t { + spi_master_sample_delay_t miso_sample_delay; + uint32_t miso_pad_delay; +} spi_master_miso_capture_timing_t; + + +#include "spi_master_sync.h" +#include "spi_master_async.h" +#include "spi_slave.h" #endif // _spi_h_ diff --git a/lib_spi/api/spi_master_async.h b/lib_spi/api/spi_master_async.h new file mode 100644 index 0000000..51c75ac --- /dev/null +++ b/lib_spi/api/spi_master_async.h @@ -0,0 +1,196 @@ +// Copyright 2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. + + +/** Asynchronous interface to an SPI component. + * + * This interface allows programs to offload SPI bus transfers to another + * task. An asynchronous notification occurs when the transfer is complete. + */ +#ifndef __DOXYGEN__ +typedef interface spi_master_async_if { +#endif + + /** + * @defgroup spi_master_async_if + * Methods for asynchronous SPI master interface. + * @{ + */ + + /** @fn void master_async::begin_transaction(unsigned device_index, + unsigned speed_in_khz, spi_mode_t mode) + * Begin a transaction. + * + * This will start a transaction on the bus. During a transaction, no + * other client to the SPI component can send or receive data. If + * another client is currently using the component then this call + * will block until the bus is released. + * + * \param device_index The index of the slave device to interact with. + * \param speed_in_khz The speed that the SPI bus should run at during + * the transaction (in kHZ). The minimum speed is 100 kHz. + * \param mode The mode of spi transfers during this transaction + */ + void begin_transaction(unsigned device_index, + unsigned speed_in_khz, spi_mode_t mode); + + /** @fn void master_async::end_transaction(unsigned ss_deassert_time) + * End a transaction. + * + * This ends a transaction on the bus and releases the component to other + * clients. + * + * \param ss_deassert_time The minimum time in reference clock ticks between + * assertions of the selected slave select. This + * time will be ignored if the next transaction is + * to a different slave select. + */ + void end_transaction(unsigned ss_deassert_time); + + /** Initialize Transfer an array of bytes over the SPI bus. + * + * This function will initialize a transmit of 8 bit data + * over the SPI bus. + * + * \param inbuf A *movable* pointer that is moved to the other task + * pointing to the buffer area to fill with data. If this + * parameter is NULL then the incoming data of the transfer + * will be discarded. + * \param outbuf A *movable* pointer that is moved to the other task + * pointing to the buffer area to with data to transmit. + * If this parameter is NULL then the outgoing data of the + * transfer will consist of undefined values. + * \param nbytes The number of bytes to transfer over the bus. + */ + void init_transfer_array_8(uint8_t_movable_ptr_t inbuf, + uint8_t_movable_ptr_t outbuf, + size_t nbytes); + + /** Initialize Transfer an array of bytes over the SPI bus. + * + * This function will initialize a transmit of 32 bit data + * over the SPI bus. + * + * \param inbuf A *movable* pointer that is moved to the other task + * pointing to the buffer area to fill with data. If this + * parameter is NULL then the incoming data of the transfer + * will be discarded. + * \param outbuf A *movable* pointer that is moved to the other task + * pointing to the buffer area to with data to transmit. + * If this parameter is NULL then the outgoing data of the + * transfer will consist of undefined values. + * \param nwords The number of words to transfer over the bus. + */ + void init_transfer_array_32(uint32_t_movable_ptr_t inbuf, + uint32_t_movable_ptr_t outbuf, + size_t nwords); + + /** Transfer completed notification. + * + * This notification occurs when a transfer is completed. + */ + [[notification]] + slave void transfer_complete(void); + + /** Retrieve transfer buffers. + * + * This function should be called after the transfer_complete() notification + * and will return the buffers given to the other task by + * init_transfer_array_8(). + * + * \param inbuf A movable pointer that will be set to the buffer + * pointer that was filled during the transfer. + * \param outbuf A movable pointer that will be set to the buffer + * pointer that was transmitted during the transfer. + */ + [[clears_notification]] + void retrieve_transfer_buffers_8(REFERENCE_PARAM(uint8_t_movable_ptr_t, inbuf), + REFERENCE_PARAM(uint8_t_movable_ptr_t, outbuf)); + + + /** Retrieve transfer buffers. + * + * This function should be called after the transfer_complete() notification + * and will return the buffers given to the other task by + * init_transfer_array_32(). + * + * \param inbuf A movable pointer that will be set to the buffer + * pointer that was filled during the transfer. + * \param outbuf A movable pointer that will be set to the buffer + * pointer that was transmitted during the transfer. + */ + [[clears_notification]] + void retrieve_transfer_buffers_32(REFERENCE_PARAM(uint32_t_movable_ptr_t, inbuf), + REFERENCE_PARAM(uint32_t_movable_ptr_t, outbuf)); + + /** Sets the bit of port which is used for slave select (> 1b port type only) + * and only for spi_master. spi_master sets all bits in each port high/low + * + * The default value (if this is not called) is the bit number is equal to + * the device_index (0->0, 1->1 etc.). + * + * \param device_index The index of the device for which the port bit is to be set. + * \param ss_port_bit Which bit number in the port to use for slave select. + */ + void set_ss_port_bit(unsigned device_index, unsigned ss_port_bit); + + /** Configures the timing parameters for MISO capture. At frequencies above 20 MHz + * it is likely that some capture delays will need to be introduced to ensure + * setup and hold times are met. + * + * See the following document for details on xcore.ai port timing: + * https://www.xmos.com/documentation/XM-014231-AN/html/rst/index.html + * + * \param device_index The index of the device for which the MISO timing is to be set. + * \param miso_capture_timing A structure of type spi_master_miso_capture_timing_t with + * the desired settings. + */ + void set_miso_capture_timing(unsigned device_index, spi_master_miso_capture_timing_t miso_capture_timing); + + /** Configures the timing settings for SS assert to clock delay, and last + * clock to SS de-assert delay. The unit is reference timer ticks which is + * nominally 10 ns. The maximum setting is 65535 which equates to 655 us + * over which the setting will overflow back to zero. + * + * \param device_index The index of the device for which the SS timing is to be set. + * \param ss_clock_timing A structure of type spi_master_ss_clock_timing_t with + * the desired settings. + */ + void set_ss_clock_timing(unsigned device_index, spi_master_ss_clock_timing_t ss_clock_timing); + + /** Shut down the SPI master interface server. Must be done after all transactions are complete + * to avoid leaving moveable pointers in the wrong place. + */ + void shutdown(void); + +/**@}*/ // end spi_master_async_if + +#ifndef __DOXYGEN__ +} spi_master_async_if; +#endif + +/** SPI master component for asynchronous API. + * + * This component implements SPI and allows a client to connect using the + * asynchronous SPI master interface. + * + * \param i an array of interface connection to the + * clients of the task. + * \param num_clients the number of clients connected to the task. + * \param sclk the SPI clock port. + * \param mosi the SPI MOSI (master out, slave in) port. + * \param miso the SPI MISO (master in, slave out) port. + * \param p_ss a port of any width which outputs the slave select signals + * \param num_slaves The number of slave devices on the bus. + * \param clk a clock block for the component to use. + */ +[[combinable]] +void spi_master_async( + SERVER_INTERFACE(spi_master_async_if, i[num_clients]), + static_const_size_t num_clients, + out_buffered_port_32_t sclk, + NULLABLE_RESOURCE(out_buffered_port_32_t, mosi), + in_buffered_port_32_t miso, + out_port p_ss, + static_const_size_t num_slaves, + clock clk); diff --git a/lib_spi/api/spi_master_sync.h b/lib_spi/api/spi_master_sync.h new file mode 100644 index 0000000..0fa62ed --- /dev/null +++ b/lib_spi/api/spi_master_sync.h @@ -0,0 +1,167 @@ +// Copyright 2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. + + +/** This interface allows clients to interact with SPI master task. */ +#ifndef __DOXYGEN__ +typedef interface spi_master_if { +#endif + + /** + * @defgroup spi_master_if + * Methods for synchronous SPI master interface. + * @{ + */ + + /** Begin a transaction. + * + * This will start a transaction on the bus. During a transaction, no + * other client to the SPI component can send or receive data. If + * another client is currently using the component then this call + * will block until the bus is released. + * + * \param device_index The index of the slave device to interact with. + * \param speed_in_khz The speed that the SPI bus should run at during + * the transaction (in kHZ). When using the version + * with clockblock, the minimum speed is 100 kHz. + * \param mode The mode of spi transfers during this transaction. + */ + [[guarded]] + void begin_transaction(unsigned device_index, + unsigned speed_in_khz, spi_mode_t mode); + + /** @fn void master_sync::end_transaction(unsigned ss_deassert_time) + * End a transaction. + * + * This ends a transaction on the bus and releases the component to other + * clients. + * + * \param ss_deassert_time The minimum time in reference clock ticks between + * assertions of the selected slave select. This + * time will be ignored if the next transaction is + * to a different slave select. + */ + void end_transaction(unsigned ss_deassert_time); + + /** Transfer a byte over the SPI bus. + * + * This function will transmit and receive 8 bits of data over the SPI + * bus. The data will be transmitted least-significant bit first. + * + * \param data The data to transmit the MOSI port. + * + * \returns The data read in from the MISO port. + */ + uint8_t transfer8(uint8_t data); + + /** Transfer a 32-bit word over the SPI bus. + * + * This function will transmit and receive 32 bits of data over the SPI + * bus. The data will be transmitted least-significant bit first and + * most significant byte first (big endian) + * + * \param data The data to transmit the MOSI port. + * + * \returns The data read in from the MISO port. + */ + uint32_t transfer32(uint32_t data); + + /** Transfer an array of bytes over the SPI interface. + * + * This function will transmit and receive 32 bits of data over the SPI + * bus. The data will be transmitted least-significant bit first in byte + * order in memory. Note that XMOS uses little endian and so 32b data etc. + * may need byteswap() first. + * + * \param data_out Reference to data to transmit the MOSI port. May be null + * if only a read is needed. + * \param data_in Reference to data to receive from the MISO port. May be + * null if only a write is needed. + * \param num_bytes Constant value of the size of the array to be transferred. + * + */ + void transfer_array(NULLABLE_ARRAY_OF(const uint8_t, data_out), NULLABLE_ARRAY_OF(uint8_t, data_in), static_const_size_t num_bytes); + + /** Sets the bit of port which is used for slave select (> 1b port type only) + * and only for spi_master. spi_master sets all bits in each port high/low + * + * The default value (if this is not called) is the bit number is equal to + * the device_index (device 0-> bit 0, device 1-> bit 1 etc.). + * + * \param device_index The index of the device for which the port bit is to be set. + * \param ss_port_bit Which bit number in the port to use for slave select. + */ + void set_ss_port_bit(unsigned device_index, unsigned ss_port_bit); + + /** Configures the timing parameters for MISO capture. At frequencies above 20 MHz + * it is likely that some capture delays will need to be introduced to ensure + * setup and hold times are met. + * These settings only affect the fast SPI master which uses a clock block. + * + * See the following document for details on xcore.ai port timing: + * https://www.xmos.com/documentation/XM-014231-AN/html/rst/index.html + * + * \param device_index The index of the device for which the MISO timing is to be set. + * \param miso_capture_timing A structure of type spi_master_miso_capture_timing_t with + * the desired settings. + */ + void set_miso_capture_timing(unsigned device_index, spi_master_miso_capture_timing_t miso_capture_timing); + + /** Configures the timing settings for SS assert to clock delay, and last + * clock to SS de-assert delay. The unit is reference timer ticks which is + * nominally 10 ns. The maximum setting is 65535 which equates to 655 us + * over which the setting will overflow back to zero. + * These settings only affect the fast SPI master which uses a clock block. + * + * \param device_index The index of the device for which the SS timing is to be set. + * \param ss_clock_timing A structure of type spi_master_ss_clock_timing_t with + * the desired settings. + */ + void set_ss_clock_timing(unsigned device_index, spi_master_ss_clock_timing_t ss_clock_timing); + + /** Shut down the SPI master interface server. + */ + void shutdown(void); + +#ifndef __DOXYGEN__ +} spi_master_if; +#endif + +/**@}*/ // end spi_master_if + +/** Task that implements the SPI proctocol in master mode that is + connected to a multiple slaves on the bus. + + Each slave must be connected to using the same SPI mode. + + You can access different slave devices over the interface connection + using the device_index parameter of the interface functions. + The task will allocate the device indices in the order of the supplied + array of slave select ports. + + \param i An array of interface connection to the + clients of the task. + \param num_clients The number of clients connected to the task. + \param clk a clock block used by the task. + \param sclk The SPI clock port. + \param mosi The SPI MOSI (master out, slave in) port. + \param miso The SPI MISO (master in, slave out) port. + \param p_ss A port connected to the slave select signals + of the slave. Multiple slaves may be supported + by specifying, for example, a 4-bit port. + Please specify mapping of bits to slaves using + i.set_ss_port_bit(). + \param num_slaves The number of slave devices on the bus. + \param clk A clock for the component to use. May be set + to null if low speed operation is acceptable. +*/ +[[distributable]] +void spi_master( + SERVER_INTERFACE(spi_master_if, i[num_clients]), + static_const_size_t num_clients, + out_buffered_port_32_t sclk, + NULLABLE_RESOURCE(out_buffered_port_32_t, mosi), + NULLABLE_RESOURCE(in_buffered_port_32_t, miso), + out_port p_ss, + static_const_size_t num_slaves, + NULLABLE_RESOURCE(clock, clk)); diff --git a/lib_spi/api/spi_slave.h b/lib_spi/api/spi_slave.h new file mode 100644 index 0000000..2a21a77 --- /dev/null +++ b/lib_spi/api/spi_slave.h @@ -0,0 +1,96 @@ +// Copyright 2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. + + +/** This interface allows clients to interact with SPI slave tasks by + * completing callbacks that show how to handle data. + */ +#ifndef __DOXYGEN__ +typedef interface spi_slave_callback_if { +#endif + + /** + * @defgroup spi_slave_callback_if + * Methods for SPI slave interface. + * @{ + */ + + + /** This callback will get called when the master de-asserts on the slave + * select line to end a transaction. + */ + void master_ends_transaction(void); + + /** This callback will get called when the master initiates a bus transfer + * or when more data is required during a transaction. + * The application must supply the data to transmit to the master. + * Data is transmitted with the least significant bit + * first. If the master completes the transaction before 8/32 bits ( + * depending on SPI_TRANSFER_SIZE_8 or SPI_TRANSFER_SIZE_32) are + * transferred and the remaining bits are discarded. + * + * \returns the 8-bit or 32-bit value to transmit. + */ + uint32_t master_requires_data(void); + + /** This callback will get called after a transfer. It will occur after + * every 8 bits transferred if the slave component is set to + * ``SPI_TRANSFER_SIZE_8``. If the component is set to + * ``SPI_TRANSFER_SIZE_32`` then it will occur if the master ends the + * transaction before 32 bits are transferred. + * + * \param datum the data received from the master. + * \param valid_bits the number of valid bits of data received from the master. + */ + void master_supplied_data(uint32_t datum, uint32_t valid_bits); + + /** Request shut down the SPI slave interface client. + */ + [[notification]] + slave void request_shutdown(void); + + /** Acknowledgment that the SPI slave task has been shutdown. + */ + [[clears_notification]] + [[guarded]] + void shutdown_complete(void); + +#ifndef __DOXYGEN__ +} spi_slave_callback_if; +#endif + +/**@}*/ // end: spi_slave_callback_if + + +/** This type specifies the transfer size from the SPI slave component + to the application */ +typedef enum spi_transfer_type_t { + SPI_TRANSFER_SIZE_8, ///< Transfers should be 8-bit. + SPI_TRANSFER_SIZE_32 ///< Transfers should be 32-bit. +} spi_transfer_type_t; + +/** SPI slave component. + * + * This function implements an SPI slave bus. + * + * \param spi_i The interface to connect to the user of the component. + * The component acts as the client and will make callbacks to + * the application. + * \param p_sclk The SPI clock port. + * \param p_mosi The SPI MOSI (master out, slave in) port. + * \param p_miso The SPI MISO (master in, slave out) port. + * \param p_ss The SPI SS (slave select) port. + * \param clk Clock to be used by the component. + * \param mode The SPI mode of the bus. + * \param transfer_type The type of transfer the slave will perform: either + * ``SPI_TRANSFER_SIZE_8`` or ``SPI_TRANSFER_SIZE_32``. + */ + [[combinable]] + void spi_slave(CLIENT_INTERFACE(spi_slave_callback_if, spi_i), + in_port p_sclk, + in_buffered_port_32_t p_mosi, + NULLABLE_RESOURCE(out_buffered_port_32_t, p_miso), + in_port p_ss, + clock clk, + static_const_spi_mode_t mode, + static_const_spi_transfer_type_t transfer_type); diff --git a/lib_spi/doc/rst/images/Makefile b/lib_spi/doc/rst/images/Makefile deleted file mode 100644 index e5306e8..0000000 --- a/lib_spi/doc/rst/images/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -ODGS = $(wildcard *.odg) -PDFS = $(ODGS:.odg=.pdf) - -all: $(PDFS) - @echo PDFs created - -_uncropped: - mkdir _uncropped - -_uncropped/%.pdf: %.odg | _uncropped - soffice -env:UserInstallation=file:///home/$(USER)/.libreoffice-alt --headless --convert-to pdf $< --outdir _uncropped - -%.pdf: _uncropped/%.pdf - pdfcrop $< $@ - -wavedrom: - WaveDromEditor source wavedrom_mode0.js png wavedrom_mode0.png - WaveDromEditor source wavedrom_mode1.js png wavedrom_mode1.png - WaveDromEditor source wavedrom_mode2.js png wavedrom_mode2.png - WaveDromEditor source wavedrom_mode3.js png wavedrom_mode3.png - -clean: - -rm $(PDFS) - -rm _uncropped/*.pdf - -rmdir _uncropped diff --git a/lib_spi/doc/rst/images/spi_master_async_state.dot b/lib_spi/doc/rst/images/spi_master_async_state.dot deleted file mode 100644 index 182edad..0000000 --- a/lib_spi/doc/rst/images/spi_master_async_state.dot +++ /dev/null @@ -1,19 +0,0 @@ -digraph g { - begin_transaction -> init_transfer_array_8 - begin_transaction -> init_transfer_array_32 - - init_transfer_array_8 -> transfer_complete - transfer_complete -> retrieve_transfer_buffers_8 - retrieve_transfer_buffers_8 -> end_transaction - - init_transfer_array_32 -> transfer_complete - transfer_complete -> retrieve_transfer_buffers_32 - retrieve_transfer_buffers_32 -> end_transaction - - retrieve_transfer_buffers_32 -> retrieve_transfer_buffers_32 - retrieve_transfer_buffers_32 -> retrieve_transfer_buffers_8 - retrieve_transfer_buffers_8 -> retrieve_transfer_buffers_32 - retrieve_transfer_buffers_8 -> retrieve_transfer_buffers_8 - - end_transaction -> begin_transaction -} diff --git a/lib_spi/doc/rst/images/spi_master_async_state.pdf b/lib_spi/doc/rst/images/spi_master_async_state.pdf deleted file mode 100644 index 8fd6dfd..0000000 Binary files a/lib_spi/doc/rst/images/spi_master_async_state.pdf and /dev/null differ diff --git a/lib_spi/doc/rst/images/spi_master_connect.odg b/lib_spi/doc/rst/images/spi_master_connect.odg deleted file mode 100644 index 245e2f5..0000000 Binary files a/lib_spi/doc/rst/images/spi_master_connect.odg and /dev/null differ diff --git a/lib_spi/doc/rst/images/spi_master_connect.pdf b/lib_spi/doc/rst/images/spi_master_connect.pdf deleted file mode 100644 index 3d379ef..0000000 Binary files a/lib_spi/doc/rst/images/spi_master_connect.pdf and /dev/null differ diff --git a/lib_spi/doc/rst/images/spi_master_sync_state.dot b/lib_spi/doc/rst/images/spi_master_sync_state.dot deleted file mode 100644 index 0c309a5..0000000 --- a/lib_spi/doc/rst/images/spi_master_sync_state.dot +++ /dev/null @@ -1,14 +0,0 @@ -digraph g { - begin_transaction -> transfer8 - begin_transaction -> transfer32 - - transfer8 -> transfer8 - transfer8 -> transfer32 - transfer32 -> transfer8 - transfer32 -> transfer32 - - transfer32 -> end_transaction - transfer32 -> end_transaction - - end_transaction -> begin_transaction -} diff --git a/lib_spi/doc/rst/images/spi_master_sync_state.pdf b/lib_spi/doc/rst/images/spi_master_sync_state.pdf deleted file mode 100644 index 77e9fbd..0000000 Binary files a/lib_spi/doc/rst/images/spi_master_sync_state.pdf and /dev/null differ diff --git a/lib_spi/doc/rst/images/spi_master_task_diag.pdf b/lib_spi/doc/rst/images/spi_master_task_diag.pdf deleted file mode 100644 index 15d10a5..0000000 Binary files a/lib_spi/doc/rst/images/spi_master_task_diag.pdf and /dev/null differ diff --git a/lib_spi/doc/rst/images/spi_slave_connect.pdf b/lib_spi/doc/rst/images/spi_slave_connect.pdf deleted file mode 100644 index 9fa3eb1..0000000 Binary files a/lib_spi/doc/rst/images/spi_slave_connect.pdf and /dev/null differ diff --git a/lib_spi/doc/rst/images/spi_slave_task_diag.pdf b/lib_spi/doc/rst/images/spi_slave_task_diag.pdf deleted file mode 100644 index 4d0b70f..0000000 Binary files a/lib_spi/doc/rst/images/spi_slave_task_diag.pdf and /dev/null differ diff --git a/lib_spi/doc/rst/images/wavedrom_mode0.js b/lib_spi/doc/rst/images/wavedrom_mode0.js deleted file mode 100644 index 3cee681..0000000 --- a/lib_spi/doc/rst/images/wavedrom_mode0.js +++ /dev/null @@ -1,8 +0,0 @@ -{signal: [ -{name: 'CLK', wave: '0..101010|10....', node: '...B'}, -{name: 'MOSI', wave: 'x..2.2.2.|2.x...', data: ['MSB',,, 'LSB'] }, -{name: 'MISO', wave: 'x..2.2.2.|2.x...', data: ['MSB',,, 'LSB'], node: '...................'}, -{name: 'CS', wave: '10.......|..1..0', node: '.A..........C..D..'}, -{ node: '.a.b........c..d'} ], -edge: [ 'A|a','B|b', 'C|c','D|d','a<->b t1', 'c<->d t2'] -} \ No newline at end of file diff --git a/lib_spi/doc/rst/images/wavedrom_mode0.png b/lib_spi/doc/rst/images/wavedrom_mode0.png deleted file mode 100644 index 30c2bfe..0000000 Binary files a/lib_spi/doc/rst/images/wavedrom_mode0.png and /dev/null differ diff --git a/lib_spi/doc/rst/images/wavedrom_mode1.js b/lib_spi/doc/rst/images/wavedrom_mode1.js deleted file mode 100644 index 4ffa214..0000000 --- a/lib_spi/doc/rst/images/wavedrom_mode1.js +++ /dev/null @@ -1,9 +0,0 @@ -{signal: [ - {name: 'CLK', wave: '0...10101|010...', node: '...B'}, - {name: 'MOSI', wave: 'x..2.2.2.|2.x...', data: ['MSB',,, 'LSB'] }, - {name: 'MISO', wave: 'x..2.2.2.|2.x...', data: ['MSB',,, 'LSB'], node: '...................'}, - {name: 'CS', wave: '10.......|..1..0', node: '.A..........C..D..'}, - { node: '.a.b........c..d'} -], - edge: [ 'A|a','B|b', 'C|c','D|d','a<->b t1', 'c<->d t2'] -} \ No newline at end of file diff --git a/lib_spi/doc/rst/images/wavedrom_mode1.png b/lib_spi/doc/rst/images/wavedrom_mode1.png deleted file mode 100644 index 702b2a8..0000000 Binary files a/lib_spi/doc/rst/images/wavedrom_mode1.png and /dev/null differ diff --git a/lib_spi/doc/rst/images/wavedrom_mode2.js b/lib_spi/doc/rst/images/wavedrom_mode2.js deleted file mode 100644 index 3c8d21f..0000000 --- a/lib_spi/doc/rst/images/wavedrom_mode2.js +++ /dev/null @@ -1,9 +0,0 @@ -{signal: [ - {name: 'CLK', wave: '1...01010|101...', node: '...B'}, - {name: 'MOSI', wave: 'x..2.2.2.|2.x...', data: ['MSB',,, 'LSB'] }, - {name: 'MISO', wave: 'x..2.2.2.|2.x...', data: ['MSB',,, 'LSB'], node: '...................'}, - {name: 'CS', wave: '10.......|..1..0', node: '.A..........C..D..'}, - { node: '.a.b........c..d'} -], - edge: [ 'A|a','B|b', 'C|c','D|d','a<->b t1', 'c<->d t2'] -} \ No newline at end of file diff --git a/lib_spi/doc/rst/images/wavedrom_mode2.png b/lib_spi/doc/rst/images/wavedrom_mode2.png deleted file mode 100644 index 3fb4892..0000000 Binary files a/lib_spi/doc/rst/images/wavedrom_mode2.png and /dev/null differ diff --git a/lib_spi/doc/rst/images/wavedrom_mode3.js b/lib_spi/doc/rst/images/wavedrom_mode3.js deleted file mode 100644 index 59ff12b..0000000 --- a/lib_spi/doc/rst/images/wavedrom_mode3.js +++ /dev/null @@ -1,9 +0,0 @@ -{signal: [ - {name: 'CLK', wave: '1..010101|01..', node: '...B'}, - {name: 'MOSI', wave: 'x..2.2.2.|2.x...', data: ['MSB',,, 'LSB'] }, - {name: 'MISO', wave: 'x..2.2.2.|2.x...', data: ['MSB',,, 'LSB'], node: '...................'}, - {name: 'CS', wave: '10.......|..1..0', node: '.A..........C..D..'}, - { node: '.a.b........c..d'} -], - edge: [ 'A|a','B|b', 'C|c','D|d','a<->b t1', 'c<->d t2'] -} \ No newline at end of file diff --git a/lib_spi/doc/rst/images/wavedrom_mode3.png b/lib_spi/doc/rst/images/wavedrom_mode3.png deleted file mode 100644 index d90c813..0000000 Binary files a/lib_spi/doc/rst/images/wavedrom_mode3.png and /dev/null differ diff --git a/lib_spi/doc/rst/index.rst b/lib_spi/doc/rst/index.rst deleted file mode 100644 index e3b2da6..0000000 --- a/lib_spi/doc/rst/index.rst +++ /dev/null @@ -1,622 +0,0 @@ -.. include:: ../../../README.rst - -.. include:: resource_usage_summary.rst - -External signal description ---------------------------- - -The SPI protocol requires a clock, one or more slave selects -and either one or two data wires. - -.. _spi_wire_table: - -.. list-table:: SPI data wires - :class: vertical-borders horizontal-borders - - * - *SCLK* - - Clock line, driven by the master - * - *MOSI* - - Master Output, Slave Input data line, driven by the master - * - *MISO* - - Master Input, Slave Output data line, driven by the slave - * - *SS* - - Slave select line, driven by the master - -During any transfer of data, the master will assert the *SS* -line and then output a series of transitions on the *SCLK* -wire. During this time, the slave will drive data to be sampled by the -master and the master will drive data to be sampled by the slave. At -the end of the transfer, the *SS* is de-asserted. - -If the slave select line is not driven high then the slave should -ignore any transitions on the other lines. - -SPI modes -......... - -The data sample points for SPI are defined by the clock polarity (CPOL) and clock phase (CPHA) -parameters. SPI clock polarity may be inverted or non-inverted by the CPOL and the CPHA parameter -is used to shift the sampling phase. The following for sections illustrate the MISO and MOSI data lines -relative to the clock. The timings are given by: - -.. list-table:: SPI timings - :class: vertical-borders horizontal-borders - - * - *t1* - - The minimum time from the start of the transaction to data being valid on the data pins. - * - *t2* - - The inter-transmission gap. This is the minimum amount of time that the slave select must be de-asserted. - * - *MAX CLOCK RATE* - - This is the maximum clock rate supported by the configuration. - -The setup and hold timings are inherited from the underlying xCORE -device. For details on these timing please refer to the device datasheet. - -Mode 0 - CPOL: 0 CPHA 1 -~~~~~~~~~~~~~~~~~~~~~~~ - -.. figure:: images/wavedrom_mode0.png - :width: 100% - - Mode 0 - -The master and slave will drive out their first data bit on the first rising edge of the clock and sample on the subsequent falling edge. - -Mode 1 - CPOL: 0 CPHA 0 -~~~~~~~~~~~~~~~~~~~~~~~ - -.. figure:: images/wavedrom_mode1.png - :width: 100% - - Mode 1 - -The master and slave will drive out their first data bit before the first rising edge of the clock then drive on subsequent falling edges. They will sample on rising edges. - -Mode 2 - CPOL: 1 CPHA 0 -~~~~~~~~~~~~~~~~~~~~~~~ - -.. figure:: images/wavedrom_mode2.png - :width: 100% - - Mode 2 - -The master and slave will drive out their first data bit before the first falling edge of the clock then drive on subsequent rising edges. They will sample on falling edges. - -Mode 3 - CPOL: 1 CPHA 1 -~~~~~~~~~~~~~~~~~~~~~~~ - -.. figure:: images/wavedrom_mode3.png - :width: 100% - - Mode 3 - -The master and slave will drive out their first data bit on the first falling edge of the clock and sample on the subsequent rising edge. - -SPI master timing characteristics -................................. - -The application calls functions to begin a transaction (which asserts -the slave select line) and to transfer data. So the minimum time -between these (*t1*) can be controlled by the application. - -The inter-transmission gap (*t2*) is also controlled by the user -application since the function to specify the end of the transaction -(i.e. the de-assertion of the slave select line) has an argument which -is the minimum amount of time before which another transaction can start. - -Synchronous SPI master clock speeds -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The maximum speed that the SPI bus can be driven depends on whether a -clock block is used, the speed of the logical core that the SPI code -is running on and where both the *MISO* and *MOSI* lines are used. The -timings can be seen in :ref:`spi_master_sync_timings`. - -.. _spi_master_sync_timings: - -.. list-table:: SPI master timings (synchronous) - :header-rows: 1 - - * - Clock blocks - - MISO enabled - - MOSI enabled - - Max kbps (62.5 MHz core) - - Max kbps (125 MHz core) - * - 0 - - 1 - - 0 - - 2497 - - 3366 - * - 0 - - 1 - - 1 - - 1765 - - 3366 - * - 1 - - 1 - - 0 - - 2149 - - 2149 - * - 1 - - 1 - - 1 - - 2149 - - 2149 - - -Asynchronous SPI master clock speeds -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The asynchronous SPI master is limited only by the clock divider on the -clock block. This means that for the 100MHz reference clock, -the asynchronous master can output a clock at up to 100MHz - -.. list-table:: SPI master timings (asynchronous) - :header-rows: 1 - - * - Clock blocks - - MISO enabled - - MOSI enabled - - Max kbps (62.5 MHz core) - - Max kbps (125 MHz core) - * - 2 - - x - - x - - 100000 - - 100000 - -|newpage| - -Connecting to the xCORE SPI master -.................................. - -The SPI wires need to be connected to the xCORE device as shown in -:ref:`spi_master_xcore_connect`. The signals can be connected to any -one bit ports on the device provide they do not overlap any other used -ports and are all on the same tile. - -.. _spi_master_xcore_connect: - -.. figure:: images/spi_master_connect.* - :width: 40% - - SPI master connection to the xCORE device - -If only one data direction is required then the *MOSI* or *MISO* line -need not be connected. However, **asynchronous mode is only supported -if the MISO line is connected**. - -The master component of this library supports multiple slaves on unique -slave select wires. This means that a single slave select assertion -cannot be used to communicate with multiple slaves at the same time. - -SPI slave timings -................. - -The logical core running the SPI slave task will wait for the slave -select line to assert and then begin processing the transaction. At -this point it will call the ``master_requires_data`` callback to -application code. The time taken for the application to perform this -call will affect how long the logical core has to resume processing -SPI data. This will affect the minimum allowable time between slave -select changing and data transfer from the master (*t1*). -The user of the library will need to determine this -time based on their application. - -After slave select is de-asserted the SPI slave task will call the -``master_ends_transaction`` callback. The time the application takes -to process this will affect the minimum allowable inter-transmission -gap between transactions (*t2*). The user of the library will also need to -determine this time based on their application. - -If the SPI slave task is combined will other tasks running on the same -logical core then the other task may process an event delaying the -time it takes for the SPI slave task to react to events. This will add -these delays to the minimum times for both *t1* and *t2*. The library -user will need to take these into account in determining the timing -restrictions on the master. - -|newpage| - -Connecting to the xCORE SPI slave -................................. - -The SPI wires need to be connected to the xCORE device as shown in -:ref:`spi_slave_xcore_connect`. The signals can be connected to any -one bit ports on the device provide they do not overlap any other used -ports and are all on the same tile. - -.. _spi_slave_xcore_connect: - -.. figure:: images/spi_slave_connect.* - :width: 40% - - SPI slave connection to the xCORE device - -The slave will only send and receive data when the slave select is -driven high. - -If the *MISO* line is not required then it need not be connected. The -*MOSI* line must always be connected. - -Usage ------ - -SPI master synchronous operation -................................ - -There are two types of interface for SPI master components: -synchronous and asynchronous. - -The synchronous API provides blocking operation. Whenever a client makes a -read or write call the operation will complete before the client can -move on - this will occupy the core that the client code is running on -until the end of the operation. This method is easy to use, has low -resource use and is very suitable for applications such as setup and -configuration of attached peripherals. - -SPI master components are instantiated as parallel tasks that run in a -``par`` statement. For synchronous operation, the application can -connect via an interface connection using the ``spi_master_if`` interface type: - -.. figure:: images/spi_master_task_diag.* - - SPI master task diagram - -For example, the following code instantiates an SPI master component -and connect to it:: - - out buffered port:32 p_miso = XS1_PORT_1A; - out port p_ss[1] = {XS1_PORT_1B}; - out buffered port:22 p_sclk = XS1_PORT_1C; - out buffered port:32 p_mosi = XS1_PORT_1D; - clock clk_spi = XS1_CLKBLK_1; - - int main(void) { - spi_master_if i_spi[1]; - par { - spi_master(i_spi, 1, p_sclk, p_mosi, p_miso , p_ss, 1, clk_spi); - my_application(i_spi[0]); - } - return 0; - } - -Note that the connection is an array of interfaces, so several tasks -can connect to the same component instance. The slave select ports are -also an array since the same SPI data lines can connect to several -devices via different slave lines. - -The final parameter of the ``spi_master`` task is an optional clock -block. If the clock block is supplied then the maximum transfer rate -of the SPI bus is increased (see :ref:`spi_master_sync_timings`). If -``null`` is supplied instead then the performance is less but no clock -block is used. - -The application can use the client end of the interface connection to -perform SPI bus operations e.g.:: - - void my_application(client spi_master_if spi) { - uint8_t val; - printf("Doing one byte transfer. Sending 0x22.\n"); - spi.begin_transaction(0, 100, SPI_MODE_0); - val = spi.transfer8(0x22); - spi.end_transaction(1000); - printf("Read data %d from the bus.\n", val); - } - -Here, ``begin_transaction`` selects the device ``0`` and asserts its -slave select line. The application can then transfer data to and from -the slave device and finish with ``end_transaction``, which de-asserts -the slave select line. - -Operations such as ``spi.transfer8`` will -block until the operation is completed on the bus. -More information on interfaces and tasks can be be found in -the :ref:`XMOS Programming Guide`. By default the -SPI synchronous master mode component does not use any logical cores of its -own. It is a *distributed* task which means it will perform its -function on the logical core of the application task connected to -it (provided the application task is on the same tile). - -Synchronous master usage state machine -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The function calls made on the SPI master interface must follow the -sequence shown by the state machine in :ref:`spi_master_usage_state_machine`. -If this sequence is not followed then the behavior is undefined. - -.. _spi_master_usage_state_machine: - -.. figure:: images/spi_master_sync_state.* - :width: 40% - - SPI master use state machine - -|newpage| - -SPI master asynchronous operation -................................. - -The synchronous API will block your application until the bus -operation is complete. In cases where the application cannot afford to -wait for this long the asynchronous API can be used. - -The asynchronous API offloads operations to another task. Calls are -provide to initiate reads and writes and notifications are provided -when the operation completes. This API requires more management in the -application but can provide much more efficient operation. -It is particularly suitable for applications where the SPI bus is -being used for continuous data transfer. - -Setting up an asynchronous SPI master component is done in the same -manner as the synchronous component:: - - out buffered port:32 p_miso = XS1_PORT_1A; - out port p_ss[1] = {XS1_PORT_1B}; - out buffered port:22 p_sclk = XS1_PORT_1C; - out buffered port:32 p_mosi = XS1_PORT_1D; - - clock cb0 = XS1_CLKBLK_1; - clock cb1 = XS1_CLKBLK_2; - - int main(void) { - spi_master_async_if i_spi[1]; - par { - spi_master_async(i_spi, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb0, cb1); - my_application(i_spi[0]); - } - return 0; - } - -|newpage| - -The application can use the asynchronous API to offload bus -operations to the component. This is done by moving pointers to the -SPI slave task to transfer and then retrieving pointers when the -operation is complete. For example, the following code -repeatedly calculates 100 bytes to send over the bus and handles 100 -bytes coming back from the slave:: - - void my_application(client spi_master_async_if spi) { - uint8_t outdata[100]; - uint8_t indata[100]; - uint8_t * movable buf_in = indata; - uint8_t * movable buf_out = outdata; - - // create and send initial data - fill_buffer_with_data(outdata); - spi.begin_transaction(0, 100, SPI_MODE_0); - spi.init_transfer_array_8(move(buf_in), move(buf_out), 100); - while (1) { - select { - case spi.transfer_complete(): - spi.retrieve_transfer_buffers_8(buf_in, buf_out); - spi.end_transaction(); - - // Handle the data that has come in - handle_incoming_data(buf_in); - // Calculate the next set of data to go - fill_buffer_with_data(buf_out); - - spi.begin_transaction(0, 100, SPI_MODE_0); - spi.init_transfer_array_8(move(buf_in), move(buf_out)); - break; - } - } - } - -The SPI asynchronous task is combinable so can be run on a logical -core with other tasks (including the application task it is connected to). - -|newpage| - -Asynchronous master command buffering -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -In order to provide asynchronous behaviour for multiple clients the asynchronous master -will store up to one ``begin_transaction`` and one ``init_transfer_array_8`` or -``init_transfer_array_32`` from each client. This means that if the -master is busy doing a transfer for client *X*, then client *Y* will -still be able to begin a transaction and send data fully -asynchronously. Consequently, after client *Y* has issued -``init_transfer_array_8`` or ``init_transfer_array_32`` the it will be -able to continue operation whilst waiting for the notification. - -Asynchronous master usage state machine -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The function calls made on the SPI master asynchronous interface must follow the -sequence shown by the state machine in -:ref:`spi_master_usage_state_machine_async`. -If this sequence is not followed then the behavior is undefined. - -.. _spi_master_usage_state_machine_async: - -.. figure:: images/spi_master_async_state.* - :width: 60% - - SPI master use state machine (asynchronous) - -Master inter-transaction gap -............................ - -For both synchronous and asynchronous modes the ``end_transaction`` requires a -slave select deassert time. This parameter will provide a minimum deassert time between -two transaction on the same slave select. In the case where a ``begin_transaction`` -asserting the slave select would violate the previous ``end_transaction`` then the -``begin_transaction`` will block until the slave select deassert time has been -satisfied. - -|newpage| - -Slave usage -........... - -SPI slave components are instantiated as parallel tasks that run in a -``par`` statement. The application can connect via an interface -connection. - -.. figure:: images/spi_slave_task_diag.pdf - - SPI slave task diagram - -For example, the following code instantiates an SPI slave component -and connect to it:: - - out buffered port:32 p_miso = XS1_PORT_1E; - in port p_ss = XS1_PORT_1F; - in port p_sclk = XS1_PORT_1G; - in buffered port:32 p_mosi = XS1_PORT_1H; - clock cb = XS1_CLKBLK_1; - - int main(void) { - interface spi_slave_callback_if i_spi; - par { - spi_slave(i_spi, p_sclk, p_mosi, p_miso, p_ss, cb, SPI_MODE_0, - SPI_TRANSFER_SIZE_8); - my_application(i_spi); - } - return 0; - } - -When a slave component is instantiated the mode and transfer size -needs to be specified. - -|newpage| - -The slave component acts as the client of the interface -connection. This means it can "callback" to the application to respond -to requests from the bus master. For example, the following code -snippet shows part of an application that responds to SPI transactions -where the first word is a command to read or write command and -subsequent transfers either provide or consume data:: - - while (1) { - uint32_t command = 0; - size_t index = 0; - select { - case spi.master_requires_data() -> uint32_t data: - if (command == 0) { - // Not got the command yet. This will be the - // first word of the transaction. - data = 0; - } else if (command == READ_COMMAND) { - data = get_read_data_item(index); - index++; - } else { - data = 0; - } - break; - case spi.master_supplied_data(uint32_t data, uint32_t valid_bits): - if (command == 0) { - command = data; - } else if (command == WRITE_COMMAND) { - handle_write_data_item(data, index); - index++; - } - break; - case spi.master_ends_transaction(): - // The master has de-asserted slave select. - command = 0; - index = 0; - break; - } - } - -Note that the time taken to handle the callbacks will determine the -timing requirements of the SPI slave. See application note AN00161 for -more details on different ways of working with the SPI slave component. - -Disabling data lines -.................... - -The *MOSI* and *MISO* parameters of the ``spi_master`` task are -optional. So in the top-level ``par`` statement the function can be -called with ``null`` instead of a port e.g.:: - - spi_master(i_spi, 1, p_sclk, null, p_miso , p_ss, 1, clk_spi); - -Similarly, the *MOSI* parameter of the ``spi_master_async`` task is -optional (but the *MISO* port must be provided). - -The ``spi_slave`` task has an optional *MISO* parameter (but the -*MOSI* port must be supplied). - -Master API ----------- - -All SPI master functions can be accessed via the ``spi.h`` header:: - - #include - -You will also have to add ``lib_spi`` to the -``USED_MODULES`` field of your application Makefile. - -Supporting types -................ - -The following type is used to configure the SPI components. - -.. doxygenenum:: spi_mode_t - -|newpage| - -Creating an SPI master instance -............................... - -.. doxygenfunction:: spi_master - -|newpage| - -.. doxygenfunction:: spi_master_async - -|newpage| - -SPI master interface -..................... - -.. doxygeninterface:: spi_master_if - -|newpage| - -SPI master asynchronous interface -................................. - -.. doxygeninterface:: spi_master_async_if - -Slave API ---------- - -All SPI slave functions can be accessed via the ``spi.h`` header:: - - #include - -You will also have to add ``lib_spi`` to the -``USED_MODULES`` field of your application Makefile. - -Creating an SPI slave instance -.............................. - -.. doxygenfunction:: spi_slave - -|newpage| - -.. doxygenenum:: spi_transfer_type_t - -|newpage| - -The SPI slave interface API -........................... - -.. doxygeninterface:: spi_slave_callback_if - -|newpage| - -|appendix| - -Known Issues ------------- - -There are no known issues with this library. - -.. include:: ../../../CHANGELOG.rst diff --git a/lib_spi/doc/rst/resource_usage_summary.rst b/lib_spi/doc/rst/resource_usage_summary.rst deleted file mode 100644 index 168b99b..0000000 --- a/lib_spi/doc/rst/resource_usage_summary.rst +++ /dev/null @@ -1,37 +0,0 @@ -Typical Resource Usage -...................... - -.. resusage:: - - * - configuration: Master (synchronous, zero clock blocks) - - globals: out buffered port:32 p_sclk = XS1_PORT_1A; out buffered port:32 p_mosi = XS1_PORT_1B; in buffered port:32 p_miso = XS1_PORT_1C; out port p_ss[1] = {XS1_PORT_1D}; - - locals: interface spi_master_if i[1]; - - fn: spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, null); - - pins: 4 - - ports: 4 (1-bit) - * - configuration: Master (synchronous, one clock block) - - globals: out buffered port:32 p_sclk = XS1_PORT_1A; out buffered port:32 p_mosi = XS1_PORT_1B; in buffered port:32 p_miso = XS1_PORT_1C; out port p_ss[1] = {XS1_PORT_1D};clock cb = XS1_CLKBLK_1; - - locals: interface spi_master_if i[1]; - - fn: spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb); - - pins: 4 - - ports: 4 (1-bit) - * - configuration: Master (asynchronous) - - globals: out buffered port:32 p_sclk = XS1_PORT_1A; out buffered port:32 p_mosi = XS1_PORT_1B; in buffered port:32 p_miso = XS1_PORT_1C; out port p_ss[1] = {XS1_PORT_1D};clock cb0 = XS1_CLKBLK_1; clock cb1 = XS1_CLKBLK_2; - - locals: interface spi_master_async_if i[1]; - - fn: spi_master_async(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb0, cb1); - - pins: 4 - - ports: 4 (1-bit) - * - configuration: Slave (32 bit transfer mode) - - globals: in port p_sclk = XS1_PORT_1A; in buffered port:32 p_mosi = XS1_PORT_1B; out buffered port:32 p_miso = XS1_PORT_1C; in port p_ss = XS1_PORT_1D;clock cb = XS1_CLKBLK_1; - - locals: interface spi_slave_callback_if i; - - fn: spi_slave(i, p_sclk, p_mosi, p_miso, p_ss, cb, SPI_MODE_0, SPI_TRANSFER_SIZE_32); - - pins: 4 - - ports: 4 (1-bit) - * - configuration: Slave (8 bit transfer mode) - - globals: in port p_sclk = XS1_PORT_1A; in buffered port:32 p_mosi = XS1_PORT_1B; out buffered port:32 p_miso = XS1_PORT_1C; in port p_ss = XS1_PORT_1D;clock cb = XS1_CLKBLK_1; - - locals: interface spi_slave_callback_if i; - - fn: spi_slave(i, p_sclk, p_mosi, p_miso, p_ss, cb, SPI_MODE_0, SPI_TRANSFER_SIZE_8); - - pins: 4 - - ports: 4 (1-bit) - -The number of pins is reduced if either of the data lines are not required. diff --git a/lib_spi/doc/rst/xdoc.conf b/lib_spi/doc/rst/xdoc.conf deleted file mode 100644 index 2cef5f5..0000000 --- a/lib_spi/doc/rst/xdoc.conf +++ /dev/null @@ -1,2 +0,0 @@ -XMOSNEWSTYLE = 1 -DOXYGEN_DIRS=../../api \ No newline at end of file diff --git a/lib_spi/lib_build_info.cmake b/lib_spi/lib_build_info.cmake new file mode 100644 index 0000000..6649354 --- /dev/null +++ b/lib_spi/lib_build_info.cmake @@ -0,0 +1,6 @@ +set(LIB_NAME lib_spi) +set(LIB_VERSION 4.0.0) +set(LIB_INCLUDES api) +set(LIB_DEPENDENT_MODULES "") +set(LIB_COMPILER_FLAGS_spi_master_async.xc -Wno-reinterpret-alignment) +XMOS_REGISTER_MODULE() diff --git a/lib_spi/module_build_info b/lib_spi/module_build_info index 86a1141..933bf31 100644 --- a/lib_spi/module_build_info +++ b/lib_spi/module_build_info @@ -1,3 +1,3 @@ -VERSION = 3.3.0 +VERSION = 4.0.0 -XCC_FLAGS_spi_async.xc = $(XCC_FLAGS) -Wno-reinterpret-alignment +XCC_FLAGS_spi_master_async.xc = $(XCC_FLAGS) -Wno-reinterpret-alignment \ No newline at end of file diff --git a/lib_spi/src/spi_async.xc b/lib_spi/src/spi_async.xc deleted file mode 100644 index 14abce2..0000000 --- a/lib_spi/src/spi_async.xc +++ /dev/null @@ -1,403 +0,0 @@ -// Copyright 2015-2021 XMOS LIMITED. -// This Software is subject to the terms of the XMOS Public Licence: Version 1. -#include -#include -#include -#include - -#include "spi.h" - -typedef struct { - unsigned client_id; - unsigned device_index; - unsigned speed_in_khz; - spi_mode_t mode; - size_t buffer_nbytes; - unsigned buffer_transfer_width; - uint32_t * movable buffer_tx; - uint32_t * movable buffer_rx; - -} transaction_request; -#define NBYTES_UNASSIGNED (-1) - -static void transfer8_async( - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 miso, - uint8_t data){ - - if(!isnull(mosi)) { - clearbuf(mosi); - mosi <: (bitrev(data)>>24); - } - - clearbuf(miso); //TODO remove- if possible - - partout(sclk, 16, 0xaaaa); -} - -static void transfer32_async( - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 miso, - uint32_t data){ - - if(!isnull(mosi)) { - clearbuf(mosi); - mosi <: bitrev(data); - } - - clearbuf(miso); //TODO remove - if possible - - //output 64 bits of clock - sclk <: 0xaaaaaaaa; - sclk <: 0xaaaaaaaa; -} - -static void setup_new_transaction( - out buffered port:32 sclk, - out port p_ss[], - clock cb0, - spi_mode_t mode, - unsigned new_device_index, - unsigned speed_in_khz, - unsigned ¤tly_selected_device){ - //xassert(device_index < num_slaves); - switch(mode){ - case SPI_MODE_0: - set_port_inv(sclk); - partout(sclk,1,1); - break; - case SPI_MODE_1: - set_port_no_inv(sclk); - partout(sclk,1,0); - break; - case SPI_MODE_2: - set_port_inv(sclk); - partout(sclk,1,0); - break; - case SPI_MODE_3: - set_port_no_inv(sclk); - partout(sclk,1,1); - break; - } - sync(sclk); - - //Wait for the chip deassert time if need be - if(new_device_index == currently_selected_device) - sync(p_ss[currently_selected_device]); - - //Set the clock divider - stop_clock(cb0); - unsigned d = (XS1_TIMER_KHZ + 4*speed_in_khz - 1)/(4*speed_in_khz); - configure_clock_ref(cb0, d); - start_clock(cb0); - - //Do a slave select - currently_selected_device = new_device_index; - p_ss[currently_selected_device] <: 0; - sync(p_ss[currently_selected_device]); -} - -static void init_init_transfer_array_8( - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 miso, - spi_mode_t active_mode, - clock cb1, - uint8_t data - ){ - if(!isnull(mosi)) - asm volatile ("settw res[%0], %1"::"r"(mosi), "r"(8)); - asm volatile ("settw res[%0], %1"::"r"(miso), "r"(8)); - - if((active_mode == SPI_MODE_1 || active_mode == SPI_MODE_2) && (!isnull(mosi))){ - unsigned b = data>>7; - asm volatile ("setclk res[%0], %1"::"r"(mosi), "r"(XS1_CLKBLK_REF)); - partout(mosi, 1, b); - asm volatile ("setclk res[%0], %1"::"r"(mosi), "r"(cb1)); - data = data<<1; //This is shifted up as the MSB is already on this pin - } - transfer8_async(sclk, mosi, miso, data); -} - -static void first_transfer_array_32( - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 miso, - spi_mode_t active_mode, - clock cb1, - uint32_t data){ - - if(!isnull(mosi)) - asm volatile ("settw res[%0], %1"::"r"(mosi), "r"(32)); - asm volatile ("settw res[%0], %1"::"r"(miso), "r"(32)); - - if((active_mode == SPI_MODE_1 || active_mode == SPI_MODE_2) && (!isnull(mosi))){ - unsigned b = bitrev(data); - asm volatile ("setclk res[%0], %1"::"r"(mosi), "r"(XS1_CLKBLK_REF)); - partout(mosi, 1, b); - asm volatile ("setclk res[%0], %1"::"r"(mosi), "r"(cb1)); - data = data<<1; //This is shifted up as the MSB is already on this pin - } - transfer32_async(sclk, mosi, miso, data); -} - -[[combinable]] -void spi_master_async(server interface spi_master_async_if i[num_clients], - static const size_t num_clients, - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 miso, - out port p_ss[num_slaves], - static const size_t num_slaves, - clock cb0, - clock cb1){ - - //These buffer are for the transaction requests - transaction_request tr_buffer[8]; ///FIXME num_clients - unsigned tr_tail = 0; - unsigned tr_fill = 0; - - //These buffers are for the active transaction - uint32_t * movable buffer_tx; - uint32_t * movable buffer_rx; - size_t buffer_nbytes; - unsigned current_index; - unsigned buffer_transfer_width; - - //These variables are for the active transaction state - unsigned active_device; - unsigned active_client; - unsigned active_mode; - int currently_performing_a_transaction = 0; - - for(unsigned i=0;i 0xffff) - delay_ticks(ss_deassert_time&0xffff0000); - time += ss_deassert_time; - p_ss[active_device] @ time <: 1; - - if(tr_fill > 0){ - //begin a new transaction - the tail of the list is the next one to go - unsigned index = tr_tail%num_clients; - unsigned new_device_index = tr_buffer[index].device_index; - unsigned speed_in_khz = tr_buffer[index].speed_in_khz; - spi_mode_t mode = tr_buffer[index].mode; - - active_client = tr_buffer[index].client_id; - - tr_fill--; - tr_tail++; - - setup_new_transaction(sclk, p_ss, cb0, mode, new_device_index, - speed_in_khz, active_device); - active_device = new_device_index; - active_mode = mode; - - buffer_nbytes = tr_buffer[index].buffer_nbytes; - - if(buffer_nbytes != NBYTES_UNASSIGNED){ - buffer_tx = move(tr_buffer[index].buffer_tx); - buffer_rx = move(tr_buffer[index].buffer_rx); - buffer_transfer_width = tr_buffer[index].buffer_transfer_width; - if(buffer_transfer_width == 8){ - init_init_transfer_array_8(sclk, mosi, miso, active_mode, cb1, ((uint8_t*movable)buffer_tx)[0]); - } else { - first_transfer_array_32(sclk, mosi, miso, active_mode, cb1, buffer_tx[0]); - } - current_index = 0; - } - } else { - currently_performing_a_transaction = 0; - } - break; - } - case i[int x].init_transfer_array_8(uint8_t * movable inbuf, - uint8_t * movable outbuf, size_t nbytes) :{ - - if(x != active_client){ - unsigned index; - for(unsigned j=0;j uint32_t data :{ - //put the data into the correct array and send the next data if need be - if(buffer_transfer_width == 8){ - data = bitrev(data<<24); - ((uint8_t*movable)buffer_rx)[current_index] = (uint8_t)data; - current_index++; - if((current_index*sizeof(uint8_t)) == buffer_nbytes){ - i[active_client].transfer_complete(); - } else { - transfer8_async(sclk, mosi, miso, - ((uint8_t*movable)buffer_tx)[current_index]); - } - } else { - data = bitrev(data); - buffer_rx[current_index] = data; - current_index++; - if((current_index*sizeof(uint32_t)) == buffer_nbytes){ - i[active_client].transfer_complete(); - } else { - transfer32_async(sclk, mosi, miso, buffer_tx[current_index]); - } - } - break; - } - case i[int x].retrieve_transfer_buffers_8(uint8_t * movable &inbuf, - uint8_t * movable &outbuf):{ - inbuf = (uint8_t*movable)move(buffer_rx); - outbuf = (uint8_t*movable)move(buffer_tx); - break; - } - - case i[int x].retrieve_transfer_buffers_32(uint32_t * movable &inbuf, - uint32_t * movable &outbuf):{ - inbuf = move(buffer_rx); - outbuf = move(buffer_tx); - break; - } - - case i[int x].shutdown(void): - move(buffer_rx); - move(buffer_tx); - set_port_use_on(sclk); - if(!isnull(mosi)) set_port_use_on(mosi); - if(!isnull(miso)) set_port_use_on(miso); - return; - } - } - -} diff --git a/lib_spi/src/spi_fwk.h b/lib_spi/src/spi_fwk.h new file mode 100644 index 0000000..45b6e68 --- /dev/null +++ b/lib_spi/src/spi_fwk.h @@ -0,0 +1,284 @@ +// Copyright 2021-2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. +#pragma once + +/** \file + * \brief API for SPI I/O + */ + +/** + * The minimum number of reference clock ticks that should + * be specified for any SPI master delay value. This value + * is carefully tuned so that the SETPT can be followed by + * the OUT in time so that we avoid this from the XS3 architecture manual: + * + * For a transfer initiated by a SETPT instruction, the direction will be input + * unless an output is executed before the time specified by the SETPT instruction. + * This means the SS port may go high impedance briefly which is undesirable. */ +#define SPI_MASTER_MINIMUM_DELAY (PLATFORM_REFERENCE_MHZ * 80 / PLATFORM_NODE_0_SYSTEM_FREQUENCY_MHZ) + +/* Default delay from clock to SS, SS de-assert to SS assert and SS to clock */ +#define SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS 20 // 200 nanoseconds + + +#include /* for size_t */ +#include +#include /* for byterev() */ +#include +#include +#ifndef __XC__ +#include +#include +#include +#include +#include +// Copy from xs1.h because this doesn't get included for non __XC__ files +/**Tests whether a time input from a timer is considered to come after + * another time input from a timer. The comparison is the same as that + * performed by the function timerafter(). + * \param A The first time to compare. + * \param B The second time to compare. + * \return Whether the first time is after the second. + */ +#define timeafter(A, B) ((int)((B) - (A)) < 0) +#else /* __XC__ defined */ +/* When using XC, ensure we don't define as resource types to avoid issues with automatics */ +#define xclock_t unsigned +#define port_t unsigned +#endif + +/* The SETC constant for pad delay is missing from xs2a_user.h */ +#define SPI_IO_SETC_PAD_DELAY(n) (0x7007 | ((n) << 3)) + +/* These appear to be missing from the public API of lib_xcore */ +#define SPI_IO_RESOURCE_SETCI(res, c) asm volatile( "setc res[%0], %1" :: "r" (res), "n" (c)) +#define SPI_IO_RESOURCE_SETC(res, r) asm volatile( "setc res[%0], %1" :: "r" (res), "r" (r)) + +/* is setpsc available in lib_xcore or anywhere else..??? */ +#ifndef __XC__ +__attribute__((always_inline)) +inline void spi_io_port_outpw( + resource_t __p, + uint32_t __w, + uint32_t __bpw) +{ + asm volatile("outpw res[%0], %1, %2" : : "r" (__p), "r" (__w), "r" (__bpw)); +} +#endif + +/** + * \addtogroup hil_spi_master hil_spi_master + * + * The public API for using the HIL SPI master. + * @{ + */ + +/** + * Enum type representing the different options + * for the SPI master sample delay. + */ +typedef enum { + spi_master_sample_delay_1_2 = 0, /**< Samples 1/2 clock cycle after output from device */ + spi_master_sample_delay_3_4 = 1, /**< Samples 3/4 clock cycle after output from device */ + spi_master_sample_delay_1_0 = 2, /**< Samples 1 clock cycle after output from device */ + spi_master_sample_delay_5_4 = 3, /**< Samples 1 and 1/4 clock cycle after output from device */ + spi_master_sample_delay_3_2 = 4, /**< Samples 1 and 1/2 clock cycle after output from device */ +} spi_master_sample_delay_t; + +/** + * Enum type used to set which of the two clock sources SCLK is derived from. + */ +typedef enum { + spi_master_source_clock_ref = 0, /**< SCLK is derived from the 100 MHz reference clock */ + spi_master_source_clock_xcore /**< SCLK is derived from the core clock */ +} spi_master_source_clock_t; + +/** + * Struct to hold a SPI master context. + * + * The members in this struct should not be accessed directly. + */ +typedef struct { + xclock_t clock_block; + port_t cs_port; + port_t sclk_port; + port_t mosi_port; + port_t miso_port; + uint32_t current_device; + int delay_before_transfer; +} spi_master_t; + +/** + * Struct type representing a SPI device connected to a SPI master + * interface. + * + * The members in this struct should not be accessed directly. + */ +typedef struct { + spi_master_t *spi_master_ctx; + spi_master_source_clock_t source_clock; + uint32_t clock_divisor; + spi_master_sample_delay_t miso_sample_delay; + uint32_t miso_pad_delay; + uint32_t miso_initial_trigger_delay; + uint32_t cs_assert_val; + uint32_t clock_delay; + uint32_t clock_bits; + uint32_t cs_to_clk_delay_ticks; + uint32_t clk_to_cs_delay_ticks; + uint32_t cs_to_cs_delay_ticks; +} spi_master_device_t; + +/** + * Initializes a SPI master I/O interface. + * + * Note: To guarantee timing in all situations, the SPI I/O interface + * implicitly sets the fast mode and high priority status register bits + * for the duration of SPI operations. This may reduce the MIPS of other + * threads based on overall system setup. + * + * \param spi The spi_master_t context to initialize. + * \param clock_block The clock block to use for the SPI master interface. + * \param cs_port The SPI interface's chip select port. This may be a multi-bit port. + * \param sclk_port The SPI interface's SCLK port. Must be a 1-bit port. + * \param mosi_port The SPI interface's MOSI port. Must be a 1-bit port. + * \param miso_port The SPI interface's MISO port. Must be a 1-bit port. + */ +void spi_master_init( + spi_master_t *spi, + xclock_t clock_block, + port_t cs_port, + port_t sclk_port, + port_t mosi_port, + port_t miso_port); + +/** + * Initialize a SPI device. Multiple SPI devices may be initialized per SPI interface. + * Each must be on a unique pin of the interface's chip select port. + * + * \param dev The context representing the device to initialize. + * \param spi The context representing the SPI master interface that the device is connected to. + * \param cs_pin The bit number of the chip select port that is connected to the device's chip select pin. + * \param cpol The clock polarity required by the device. + * \param cpha The clock phase required by the device. + * \param source_clock The source clock to derive SCLK from. See spi_master_source_clock_t. + * \param clock_divisor The value to divide the source clock by. + * The frequency of SCLK will be set to: + * - (F_src) / (4 * clock_divisor) when clock_divisor > 0 + * - (F_src) / (2) when clock_divisor = 0 + * Where F_src is the frequency of the source clock. + * \param miso_sample_delay When to sample MISO. See spi_master_sample_delay_t. + * \param miso_pad_delay The number of core clock cycles to delay sampling the MISO pad during + * a transaction. This allows for more fine grained adjustment + * of sampling time. The value may be between 0 and 5. + * \param cs_to_clk_delay_ticks The minimum number of reference clock ticks between assertion of chip select + * and the first clock edge. + * \param clk_to_cs_delay_ticks The minimum number of reference clock ticks between the last clock edge and + * de-assertion of chip select. + * \param cs_to_cs_delay_ticks The minimum number of reference clock ticks between transactions, which is between + * de-assertion of chip select and the end of one transaction, and its re-assertion at + * the beginning of the next. + */ +void spi_master_device_init( + spi_master_device_t *dev, + spi_master_t *spi, + uint32_t cs_pin, + int cpol, + int cpha, + spi_master_source_clock_t source_clock, + uint32_t clock_divisor, + spi_master_sample_delay_t miso_sample_delay, + uint32_t miso_pad_delay, + uint32_t cs_to_clk_delay_ticks, + uint32_t clk_to_cs_delay_ticks, + uint32_t cs_to_cs_delay_ticks); + +/** + * Starts a SPI transaction with the specified SPI device. This leaves chip select asserted. + * + * \param dev The SPI device with which to start a transaction. + */ +void spi_master_start_transaction( + spi_master_device_t *dev); + +/** + * Transfers data to/from the specified SPI device. This may be called + * multiple times during a single transaction. + * + * \param dev The SPI device with which to transfer data. + * \param data_out Buffer containing the data to send to the device. + * May be NULL if no data needs to be sent. + * \param data_in Buffer to save the data received from the device. + * May be NULL if the data received is not needed. + * \param len The length in bytes of the data to transfer. Both + * buffers must be at least this large if not NULL. + */ +void spi_master_transfer( + spi_master_device_t *dev, + uint8_t *data_out, + uint8_t *data_in, + size_t len); + +#ifndef __XC__ + +/** + * Implements a blocking (busy wait) delay for a number of ref ticks + * + * \param delay_ticks The number of reference clock ticks to delay. + */ +static inline void blocking_wait_ticks(uint32_t delay_ticks){ + uint32_t wait_time = get_reference_time(); + wait_time += delay_ticks; + while(!timeafter(get_reference_time(), wait_time)); +} + +/** + * Enforces a minimum delay between the time this is called and + * the next transfer. It must be called during a transaction. + * It returns immediately. + * + * \param dev The active SPI device. + * \param delay_ticks The number of reference clock ticks to delay. + */ +static inline void spi_master_delay_before_next_transfer( + spi_master_device_t *dev, + uint32_t delay_ticks) +{ + spi_master_t *spi = dev->spi_master_ctx; + + spi->delay_before_transfer = 1; + + port_clear_trigger_time(spi->cs_port); + + /* Assert CS now */ + port_out(spi->cs_port, dev->cs_assert_val); + port_sync(spi->cs_port); + + /* + * Assert CS again, scheduled for earliest time the + * next transfer is allowed to start. + */ + if (delay_ticks >= SPI_MASTER_MINIMUM_DELAY) { + port_out_at_time(spi->cs_port, port_get_trigger_time(spi->cs_port) + delay_ticks, dev->cs_assert_val); + } else { + blocking_wait_ticks(dev->clk_to_cs_delay_ticks); + } +} +#endif +/** + * Ends a SPI transaction with the specified SPI device. This leaves chip select de-asserted. + * + * \param dev The SPI device with which to end a transaction. + */ +void spi_master_end_transaction( + spi_master_device_t *dev); + +/** + * De-initializes the specified SPI master interface. This disables the + * ports and clock block. + * + * \param spi The spi_master_t context to de-initialize. + */ +void spi_master_deinit( + spi_master_t *spi); + diff --git a/lib_spi/src/spi_master.c b/lib_spi/src/spi_master.c new file mode 100644 index 0000000..81ef8a4 --- /dev/null +++ b/lib_spi/src/spi_master.c @@ -0,0 +1,311 @@ +// Copyright 2021-2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. +#include +#include +#include "spi_fwk.h" +#include + + +void spi_master_start_transaction( + spi_master_device_t *dev) +{ + spi_master_t *spi = dev->spi_master_ctx; + + if (dev->cs_assert_val != spi->current_device) { + spi->current_device = dev->cs_assert_val; + + if (dev->source_clock == spi_master_source_clock_ref) { + clock_set_source_clk_ref(spi->clock_block); + } else { + clock_set_source_clk_xcore(spi->clock_block); + } + clock_set_divide(spi->clock_block, dev->clock_divisor); + + if (spi->miso_port != 0) { + if ((dev->miso_sample_delay & 1) == 0) { + port_set_sample_falling_edge(spi->miso_port); + } else { + port_set_sample_rising_edge(spi->miso_port); + } + SPI_IO_RESOURCE_SETC(spi->miso_port, SPI_IO_SETC_PAD_DELAY(dev->miso_pad_delay)); + } + + /* Output the clock idle value */ + clock_start(spi->clock_block); + spi_io_port_outpw(spi->sclk_port, dev->clock_bits >> 1, 1); + port_sync(spi->sclk_port); + clock_stop(spi->clock_block); + + /* + * This transaction is with a different chip + * than last time, so there is no need to wait + * for the minimum CS to CS time. + */ + port_clear_trigger_time(spi->cs_port); + } else { + /* + * This ensures that the CS_high to CS_low + * minimum time is met. + */ + port_sync(spi->cs_port); + } + + /* + * The first transfer will sync on CS before starting to + * ensure the minimum CS to data time is met. + */ + spi_master_delay_before_next_transfer(dev, dev->cs_to_clk_delay_ticks); +} + +__attribute__((always_inline)) +inline uint32_t load_data_out( + const uint8_t *data_out, + const int len) +{ + uint32_t tmp; + uint32_t word_out; + + tmp = (uint32_t)data_out[0] << 8; + if (len > 1) { + tmp |= data_out[1]; + } + word_out = tmp; + asm volatile("zip %0, %1, 0" :"+r"(tmp), "+r"(word_out)); + return bitrev(word_out); +} + +__attribute__((always_inline)) +inline void save_data_in( + uint8_t *data_in, + uint32_t word_in, + size_t bytes) +{ + uint32_t tmp; + + word_in = bitrev(word_in); + asm volatile("unzip %0, %1, 0" :"+r"(tmp), "+r"(word_in)); + if (bytes == 1) { + data_in[0] = word_in; + } else { + data_in[1] = word_in; + data_in[0] = (word_in >> 8) & 0xFF; + } +} + +void spi_master_transfer( + spi_master_device_t *dev, + uint8_t *data_out, + uint8_t *data_in, + size_t len) +{ + const uint32_t start_time = 1; + spi_master_t *spi = dev->spi_master_ctx; + uint32_t word_count; + uint32_t remainder; + uint32_t tw; + uint32_t word; + const int do_output = data_out != NULL && spi->mosi_port != 0; + const int do_input = data_in != NULL && spi->miso_port != 0; + + if (len == 0) { + return; + } + + word_count = len / sizeof(uint16_t); + remainder = len & sizeof(uint16_t) - 1; /* get the byte remainder */ + + if (spi->delay_before_transfer) { + /* Ensure the delay time is met */ + port_sync(spi->cs_port); + spi->delay_before_transfer = 0; + } else { + port_clear_trigger_time(spi->cs_port); + } + + port_set_trigger_time(spi->sclk_port, start_time + dev->clock_delay); + + if (do_output) { + port_set_trigger_time(spi->mosi_port, start_time); + } + + tw = len == 1 ? 16 : 32; + + spi_io_port_outpw(spi->sclk_port, dev->clock_bits, tw); + + if (do_output) { + spi_io_port_outpw(spi->mosi_port, load_data_out(data_out, len), tw); + data_out += 2; + } + if (do_input) { + port_set_trigger_time(spi->miso_port, start_time + (tw - 2) + dev->miso_initial_trigger_delay); + } + + clock_start(spi->clock_block); + + if (word_count > 0) { + while (word_count-- != 1) { + port_out(spi->sclk_port, dev->clock_bits); + + if (do_output) { + word = load_data_out(data_out, 2); + port_out(spi->mosi_port, word); + } + if (do_input) { + word = port_in(spi->miso_port); + save_data_in(data_in, word, 2); + } + data_out += 2; + data_in += 2; + } + + if (remainder > 0) { + spi_io_port_outpw(spi->sclk_port, dev->clock_bits, 16); + + if (do_output) { + word = load_data_out(data_out, 1); + spi_io_port_outpw(spi->mosi_port, word, 16); + } + if (do_input) { + word = port_in(spi->miso_port); + port_set_shift_count(spi->miso_port, 16); + save_data_in(data_in, word, 2); + data_in += 2; + } + } + } + + if (do_input) { + word = port_in(spi->miso_port); + save_data_in(data_in, word, remainder); + } + + port_sync(spi->sclk_port); + clock_stop(spi->clock_block); + + /* Assert CS again now */ + port_out(spi->cs_port, dev->cs_assert_val); + port_sync(spi->cs_port); + + /* + * And assert CS again, scheduled for earliest time CS + * is allowed to deassert. + */ + if (dev->clk_to_cs_delay_ticks >= SPI_MASTER_MINIMUM_DELAY) { + // Use port time + port_out_at_time(spi->cs_port, port_get_trigger_time(spi->cs_port) + dev->clk_to_cs_delay_ticks, dev->cs_assert_val); + } else { + blocking_wait_ticks(dev->clk_to_cs_delay_ticks); + } +} + +void spi_master_end_transaction( + spi_master_device_t *dev) +{ + const uint32_t cs_deassert_val = 0xFFFFFFFF; + spi_master_t *spi = dev->spi_master_ctx; + + port_sync(spi->cs_port); + + port_out(spi->cs_port, cs_deassert_val); + port_sync(spi->cs_port); + + /* + * Deassert CS again, scheduled for earliest time CS + * is allowed to be re-asserted. The next transaction + * will sync on CS before starting to ensure the minimum + * CS to CS time is met. + */ + if (dev->cs_to_cs_delay_ticks >= SPI_MASTER_MINIMUM_DELAY) { + port_out_at_time(spi->cs_port, port_get_trigger_time(spi->cs_port) + dev->cs_to_cs_delay_ticks, cs_deassert_val); + } else { + blocking_wait_ticks(dev->clk_to_cs_delay_ticks); + } +} + +void spi_master_deinit( + spi_master_t *spi) +{ + port_disable(spi->cs_port); + if (spi->mosi_port != 0) { + port_disable(spi->mosi_port); + } + if (spi->miso_port != 0) { + port_disable(spi->miso_port); + } + port_disable(spi->sclk_port); + clock_disable(spi->clock_block); +} + +void spi_master_device_init( + spi_master_device_t *dev, + spi_master_t *spi, + uint32_t cs_pin, + int cpol, + int cpha, + spi_master_source_clock_t source_clock, + uint32_t clock_divisor, + spi_master_sample_delay_t miso_sample_delay, + uint32_t miso_pad_delay, + uint32_t cs_to_clk_delay_ticks, + uint32_t clk_to_cs_delay_ticks, + uint32_t cs_to_cs_delay_ticks) +{ + dev->spi_master_ctx = spi; + + dev->source_clock = source_clock; + dev->clock_divisor = clock_divisor; + dev->miso_sample_delay = miso_sample_delay; + + dev->miso_initial_trigger_delay = (miso_sample_delay + 1) >> 1; + dev->miso_pad_delay = miso_pad_delay; + + dev->cs_assert_val = 0xFFFFFFFF & ~(1 << cs_pin); + dev->clock_delay = cpha ? 0 : 1; + dev->clock_bits = cpol ? 0xAAAAAAAA : 0x55555555; + + dev->cs_to_clk_delay_ticks = cs_to_clk_delay_ticks; + dev->clk_to_cs_delay_ticks = clk_to_cs_delay_ticks; + dev->cs_to_cs_delay_ticks = cs_to_cs_delay_ticks; +} + +void spi_master_init( + spi_master_t *spi, + xclock_t clock_block, + port_t cs_port, + port_t sclk_port, + port_t mosi_port, + port_t miso_port) +{ + /* Setup the clock block */ + spi->clock_block = clock_block; + clock_enable(spi->clock_block); + + /* Setup the chip select port */ + spi->cs_port = cs_port; + port_enable(spi->cs_port); + port_set_clock(spi->cs_port, XS1_CLKBLK_REF); + port_out(spi->cs_port, 0xFFFFFFFF); + port_sync(spi->cs_port); + spi->current_device = 0xFFFFFFFF; + + /* Setup the SCLK port */ + spi->sclk_port = sclk_port; + port_start_buffered(spi->sclk_port, 32); + port_set_clock(spi->sclk_port, spi->clock_block); + + /* Setup the MOSI port */ + spi->mosi_port = mosi_port; + if (mosi_port != 0) { + port_start_buffered(spi->mosi_port, 32); + port_set_clock(spi->mosi_port, spi->clock_block); + port_clear_buffer(spi->mosi_port); + } + + /* Setup the MISO port */ + spi->miso_port = miso_port; + if (miso_port != 0) { + port_start_buffered(spi->miso_port, 32); + port_set_clock(spi->miso_port, spi->clock_block); + port_clear_buffer(spi->miso_port); + } +} diff --git a/lib_spi/src/spi_master_async.xc b/lib_spi/src/spi_master_async.xc new file mode 100644 index 0000000..6cc6055 --- /dev/null +++ b/lib_spi/src/spi_master_async.xc @@ -0,0 +1,380 @@ +// Copyright 2015-2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. +#include +#include +#include +#include + +#include +#include "spi.h" +#include "spi_master_shared.h" + + +typedef struct { + unsigned client_id; + unsigned device_index; + unsigned speed_in_khz; + spi_mode_t mode; + size_t buffer_nbytes; + unsigned buffer_transfer_width; + uint32_t * movable buffer_tx; + uint32_t * movable buffer_rx; + +} transaction_request; + +#define NBYTES_UNASSIGNED 0xffffffff // Can be made using mkmsk quickly + + +[[combinable]] +void spi_master_async(server interface spi_master_async_if i[num_clients], + static const size_t num_clients, + out buffered port:32 sclk, + out buffered port:32 ?mosi, + in buffered port:32 miso, + out port p_ss, + static const size_t num_slaves, + clock cb){ + + //These buffer are for the transaction requests + transaction_request tr_buffer[num_clients]; + unsigned tr_tail = 0; + unsigned tr_fill = 0; + + //These buffers are for the active transaction + uint32_t * movable buffer_tx; + uint32_t * movable buffer_rx; + size_t buffer_nbytes; + unsigned buffer_current_index; + unsigned buffer_transfer_width; + + //These variables are for the active transaction state + unsigned active_device; + unsigned active_client; + unsigned active_mode; + int currently_performing_a_transaction = 0; + + //Setup fwk SPI master and device instance + spi_master_t spi_master; + spi_master_device_t spi_dev[num_slaves]; + spi_master_ss_clock_timing_t device_ss_clock_timing[num_slaves]; // Initialised below + spi_master_miso_capture_timing_t device_miso_capture_timing[num_slaves] = {{0}};// Default no delay + + unsafe{ + spi_master_init(&spi_master, (xclock_t)cb, (port_t)p_ss, (port_t)sclk, (port_t)mosi, (port_t)miso); + for(size_t i = 0; i < num_slaves; i++){ + device_ss_clock_timing[i].cs_to_clk_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; + device_ss_clock_timing[i].clk_to_cs_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; + spi_dev[i].cs_to_cs_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; + device_miso_capture_timing[i].miso_pad_delay = spi_master_sample_delay_1_2; // Half a SPI clock + device_miso_capture_timing[i].miso_sample_delay = 0; // Default no delay + } + } + + // By default use the port bit which is the number of the slave (slave 0 uses port bit 0 etc.) + uint8_t ss_port_bit[num_slaves]; + for(size_t i = 0; i < num_slaves; i++){ + ss_port_bit[i] = i; + } + + // Initial SS bit pattern - deselected + p_ss <: 0xffffffff; + + // TMP MISO vals + uint8_t read8; + uint32_t read32; + + // Use as way of implementing a default case. Setting the default_case_time to the current time makes an event happen immediately + // This is used for subsequent SPI transfers after the first during a transaction + timer tmr; + int default_case_time; + int default_case_enabled = 0; + + while(1){ + select { + case i[int x].begin_transaction(unsigned device_index, unsigned speed_in_khz, spi_mode_t mode):{ + //if doing a transaction then buffer this one + if(currently_performing_a_transaction){ + //Note, the tr_fill should never exceed num_clients if the calling protocol is respected + unsigned index = (tr_tail + tr_fill)%num_clients; + tr_buffer[index].device_index = device_index; + tr_buffer[index].speed_in_khz = speed_in_khz; + tr_buffer[index].mode = mode; + tr_buffer[index].client_id = x; + tr_buffer[index].buffer_nbytes = NBYTES_UNASSIGNED; + tr_fill++; + break; + } + + active_client = x; + active_device = device_index; + active_mode = mode; + + // Calculate clock divider and SPI mode vs CPOL/CPHA + spi_master_source_clock_t source_clock; + unsigned divider; + spi_master_determine_clock_settings(&source_clock, ÷r, speed_in_khz); + + unsigned cpol = mode >> 1; + unsigned cpha = mode & 0x1; + + spi_master_device_init(&spi_dev[active_device], &spi_master, + ss_port_bit[active_device], + cpol, cpha, + source_clock, + divider, + device_miso_capture_timing[active_device].miso_sample_delay, + device_miso_capture_timing[active_device].miso_pad_delay, + device_ss_clock_timing[active_device].clk_to_cs_delay_ticks, + device_ss_clock_timing[active_device].cs_to_clk_delay_ticks, + spi_dev[active_device].cs_to_cs_delay_ticks); // Write same value back + + spi_master_start_transaction(&spi_dev[active_device]); + + buffer_current_index = 0; + currently_performing_a_transaction = 1; + + break; + } + + case i[int x].init_transfer_array_8(uint8_t * movable inbuf, + uint8_t * movable outbuf, + size_t nbytes) :{ + if(x != active_client){ + // Just buffer it + size_t index; + for(size_t j=0;j default_case_time; + default_case_enabled = 1; + } + } + break; + } + + case i[int x].init_transfer_array_32(uint32_t * movable inbuf, + uint32_t * movable outbuf, + size_t nwords):{ + if(x != active_client){ + // Just buffer it + size_t index; + for(size_t j=0;j default_case_time; + default_case_enabled = 1; + } + } + break; + } + + // This case handles the input from the last transfer + case default_case_enabled => tmr when timerafter(default_case_time) :> int _:{ + //put the data into the correct array and send the next data if needs be + if(buffer_transfer_width == 8){ + uint32_t data = (uint32_t)read8; + if(buffer_rx != NULL){ + ((uint8_t*movable)buffer_rx)[buffer_current_index] = (uint8_t)data; + } + buffer_current_index++; + if((buffer_current_index*sizeof(uint8_t)) == buffer_nbytes){ + default_case_enabled = 0; + buffer_current_index = 0; + i[active_client].transfer_complete(); + } else { + spi_master_transfer(&spi_dev[active_device], &((uint8_t*movable)buffer_tx)[buffer_current_index], &read8, 1); + tmr :> default_case_time; + default_case_enabled = 1; + } + } else { + uint32_t data = byterev(read32); + if(buffer_rx != NULL){ + buffer_rx[buffer_current_index] = data; + } + buffer_current_index++; + if((buffer_current_index*sizeof(uint32_t)) == buffer_nbytes){ + default_case_enabled = 0; + buffer_current_index = 0; + i[active_client].transfer_complete(); + } else { + uint32_t mosi_data = byterev(buffer_tx[buffer_current_index]); + spi_master_transfer(&spi_dev[active_device], (uint8_t *)&mosi_data, (uint8_t*)&read32, 4); + tmr :> default_case_time; + default_case_enabled = 1; + } + } + break; + } + + //Note, end transaction can only be called from the active_client + case i[int x].end_transaction(unsigned ss_deassert_time):{ + //An end_transaction can only be completed after all transfers + //have been completed + + spi_dev[active_device].cs_to_cs_delay_ticks = ss_deassert_time; + spi_master_end_transaction(&spi_dev[active_device]); + + if(tr_fill > 0){ + //begin a new transaction - the tail of the list is the next one to go + unsigned index = tr_tail%num_clients; + unsigned new_device_index = tr_buffer[index].device_index; + unsigned speed_in_khz = tr_buffer[index].speed_in_khz; + spi_mode_t mode = tr_buffer[index].mode; + + active_client = tr_buffer[index].client_id; + + tr_fill--; + tr_tail++; + + // Put in generic start transaction stuff (Functionise?) + // Calculate clock divider and SPI mode vs CPOL/CPHA + spi_master_source_clock_t source_clock; + unsigned divider; + spi_master_determine_clock_settings(&source_clock, ÷r, speed_in_khz); + unsigned cpol = mode >> 1; + unsigned cpha = mode & 0x1; + + spi_master_device_init(&spi_dev[new_device_index], &spi_master, + ss_port_bit[new_device_index], + cpol, cpha, + source_clock, + divider, + device_miso_capture_timing[new_device_index].miso_sample_delay, + device_miso_capture_timing[new_device_index].miso_pad_delay, + device_ss_clock_timing[new_device_index].clk_to_cs_delay_ticks, + device_ss_clock_timing[new_device_index].cs_to_clk_delay_ticks, + spi_dev[new_device_index].cs_to_cs_delay_ticks); // Write same value back + + spi_master_start_transaction(&spi_dev[new_device_index]); + + active_device = new_device_index; + active_mode = mode; + + buffer_nbytes = tr_buffer[index].buffer_nbytes; + + if(buffer_nbytes != NBYTES_UNASSIGNED){ + buffer_tx = move(tr_buffer[index].buffer_tx); + buffer_rx = move(tr_buffer[index].buffer_rx); + buffer_transfer_width = tr_buffer[index].buffer_transfer_width; + if(buffer_transfer_width == 8){ + uint8_t mosi_data; + if(buffer_tx != NULL){ + mosi_data = ((uint8_t*movable)buffer_tx)[0]; + } + spi_master_transfer(&spi_dev[active_device], &mosi_data, &read8, 1); + tmr :> default_case_time; + default_case_enabled = 1; + } else { + uint32_t mosi_data; + if(buffer_tx != NULL){ + mosi_data = byterev(buffer_tx[0]); + } + spi_master_transfer(&spi_dev[active_device], (uint8_t *)&mosi_data, (uint8_t*)&read32, 4); + tmr :> default_case_time; + default_case_enabled = 1; + } + buffer_current_index = 0; + } + } else { + currently_performing_a_transaction = 0; + } + break; + } + + case i[int x].retrieve_transfer_buffers_8(uint8_t * movable &inbuf, uint8_t * movable &outbuf):{ + inbuf = (uint8_t*movable)move(buffer_rx); + outbuf = (uint8_t*movable)move(buffer_tx); + break; + } + + case i[int x].retrieve_transfer_buffers_32(uint32_t * movable &inbuf, uint32_t * movable &outbuf):{ + inbuf = move(buffer_rx); + outbuf = move(buffer_tx); + break; + } + + case i[int x].set_ss_port_bit(unsigned device_index, unsigned port_bit):{ + if(device_index > num_slaves){ + printstrln("Invalid port bit - must be less than num_slaves"); + } + ss_port_bit[device_index] = port_bit; + + break; + } + + case i[int x].set_miso_capture_timing(unsigned device_index, spi_master_miso_capture_timing_t miso_capture_timing):{ + device_miso_capture_timing[x] = miso_capture_timing; + break; + } + + case i[int x].set_ss_clock_timing(unsigned device_index, spi_master_ss_clock_timing_t ss_clock_timing):{ + device_ss_clock_timing[x] = ss_clock_timing; + break; + } + + case i[int x].shutdown(void): + move(buffer_rx); + move(buffer_tx); + // When using XC, then we need to enable/init so ports are still on + p_ss <: 0xffffffff; + // These just reset the ports and clk + if (!isnull(mosi)) { + set_port_use_on(mosi); + } + set_port_use_on(miso); + set_port_use_on(sclk); + set_clock_on(cb); + return; + } + } + +} diff --git a/lib_spi/src/spi_master_shared.h b/lib_spi/src/spi_master_shared.h new file mode 100644 index 0000000..98aec9d --- /dev/null +++ b/lib_spi/src/spi_master_shared.h @@ -0,0 +1,33 @@ +// Copyright 2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. +#include +#include +#include + +#include "spi.h" +extern "C"{ + #include "spi_fwk.h" +} + +// Clockblock-less SPI transfer functions. These are slow (max around 1 Mbps) but are suitable for control transfer +// When clockblock resources are scarce +uint8_t transfer8_sync_zero_clkblk( + out buffered port:32 sclk, + out buffered port:32 ?mosi, + in buffered port:32 ?miso, + uint8_t data, const unsigned period, + unsigned cpol, unsigned cpha); + +uint32_t transfer32_sync_zero_clkblk( + out buffered port:32 sclk, + out buffered port:32 ?mosi, + in buffered port:32 ?miso, + uint32_t data, const unsigned period, + const unsigned cpol, const unsigned cpha); + +// Optional function to determine the actual set speed for particular clock settings. +unsigned spi_master_get_actual_clock_rate(spi_master_source_clock_t source_clock, unsigned divider); + +// Find the best clock divider and source to hit the target rate. Note this will always round down to the next slowest available rate +// effectively using a ceil type function +void spi_master_determine_clock_settings(spi_master_source_clock_t *source_clock, unsigned *divider, unsigned speed_in_khz); \ No newline at end of file diff --git a/lib_spi/src/spi_master_shared.xc b/lib_spi/src/spi_master_shared.xc new file mode 100644 index 0000000..5901a55 --- /dev/null +++ b/lib_spi/src/spi_master_shared.xc @@ -0,0 +1,123 @@ +// Copyright 2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. +#include +#include +#include + +#include +#include +#include + +#include "spi.h" +extern "C"{ + #include "spi_fwk.h" +} + + +#pragma unsafe arrays +uint8_t transfer8_sync_zero_clkblk( + out buffered port:32 sclk, + out buffered port:32 ?mosi, + in buffered port:32 ?miso, + uint8_t data, const unsigned period, + unsigned cpol, unsigned cpha){ + unsigned time, d, c = 0xaaaa>>(cpol ^ cpha); + time = partout_timestamped(sclk, 1, cpol); + time += 40; + + for(unsigned i=0;i<8;i++){ + partout_timed(sclk, 1, c, time); + c>>=1; + + if(!isnull(mosi)){ + partout_timed(mosi, 1, data>>7, time); + data<<=1; + } + time += period / 2; + + partout_timed(sclk, 1, c, time); + c>>=1; + if(!isnull(miso)){ + unsigned t; + miso @ time - 1 :> t; + d = (d<<1) + (t&1); + } + time += (period + 1)/2; + } + partout_timed(sclk, 1, cpol, time); + sync(sclk); + return d; +} + +#pragma unsafe arrays +uint32_t transfer32_sync_zero_clkblk( + out buffered port:32 sclk, + out buffered port:32 ?mosi, + in buffered port:32 ?miso, + uint32_t data, const unsigned period, + const unsigned cpol, const unsigned cpha){ + unsigned time; + uint32_t d; + time = partout_timestamped(sclk, 1, cpol); + time += 100; + + //bitrev the data + for(unsigned j=0;j<2;j++){ + unsigned c = 0xaaaaaaaa>>(cpol ^ cpha); + for(unsigned i=0;i<16;i++){ + partout_timed(sclk, 1, c, time); + if(!isnull(mosi)){ + partout_timed(mosi, 1, data>>31, time); + data<<=1; + } + c>>=1; + time += period / 2; + partout_timed(sclk, 1, c, time); + c>>=1; + if(!isnull(miso)){ + unsigned t; + miso @ time - 1 :> t; + d = (d<<1) + (t&1); + } + time += (period + 1)/2; + } + time += 80; + } + partout_timed(sclk, 1, cpol, time); + sync(sclk); + return d; +} + + +// Optional function to determine the actual set speed for particular clock settings. +unsigned spi_master_get_actual_clock_rate(spi_master_source_clock_t source_clock, unsigned divider){ + unsigned actual_speed_khz = ((source_clock == spi_master_source_clock_ref) ? PLATFORM_REFERENCE_MHZ : PLATFORM_NODE_0_SYSTEM_FREQUENCY_MHZ) * 1000 + / 2 + / (divider == 0 ? 1 : ((divider) * 2)); + + return actual_speed_khz; +} + + +// Find the best clock divider and source to hit the target rate. Note this will always round down to the next slowest available rate +// effectively using a ceil type function +void spi_master_determine_clock_settings(spi_master_source_clock_t *source_clock, unsigned *divider, unsigned speed_in_khz){ + // Clock blocks divide at / (2 * div) for div > 0 or / 1 where div == 0. Maximum clock block division is 255 * 2 = 510 + // Due to SPI needing to output each bit twice (to allow control over clock edges) the overal SPI clock rate is / 2 further + // to the divider. + // Steps get very granular as div -> 1 so use ref clock below 2MHz and core clock above 2MHz + // The minimum SPI clock speed is therefore 100e6 / (255 * 2 * 2) = 98kHz on the ref clock + // The minimum SPI clock speed at 800MHz core clock (typical highest) is 800e6 / (255 * 2 * 2) = 784kHz + if(speed_in_khz > 2000){ + *source_clock = spi_master_source_clock_xcore; + *divider = (PLATFORM_NODE_0_SYSTEM_FREQUENCY_MHZ * 1000 + 4 * speed_in_khz - 1)/(4 * speed_in_khz); + } else { + *source_clock = spi_master_source_clock_ref; + *divider = (PLATFORM_REFERENCE_MHZ * 1000 + 4 * speed_in_khz - 1)/(4 * speed_in_khz); + } + + // Avoid overflow of the 8b divider reg. + if(*divider > 255){ + *divider = 255; + } +} diff --git a/lib_spi/src/spi_master_sync.xc b/lib_spi/src/spi_master_sync.xc new file mode 100644 index 0000000..1e0479b --- /dev/null +++ b/lib_spi/src/spi_master_sync.xc @@ -0,0 +1,239 @@ +// Copyright 2015-2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. +#include +#include +#include +#include +#include +#include +#include + +#include "spi.h" +#include "spi_master_shared.h" + + +#pragma unsafe arrays +[[distributable]] +void spi_master(server interface spi_master_if i[num_clients], + static const size_t num_clients, + out buffered port:32 p_sclk, + out buffered port:32 ?p_mosi, + in buffered port:32 ?p_miso, + out port p_ss, // Note only one SS port supported - individual bits in port may be used for different devices however + static const size_t num_slaves, + clock ?cb){ + + // For clock-block based fast SPI + spi_master_t spi_master; + spi_master_device_t spi_dev[num_slaves]; + spi_master_ss_clock_timing_t device_ss_clock_timing[num_slaves]; // Initialised below + spi_master_miso_capture_timing_t device_miso_capture_timing[num_slaves] = {{0}}; + unsigned current_device; + + // For clock-blockless slow SPI + unsigned clkblkless_period_ticks; + + // For all SPI types + unsigned cpol = 0; + unsigned cpha = 0; + + if(!isnull(cb)){ + unsafe{ + spi_master_init(&spi_master, (xclock_t)cb, (port_t)p_ss, (port_t)p_sclk, (port_t)p_mosi, (port_t)p_miso); + // Set default timings + for(int i = 0; i < num_slaves; i++){ + device_ss_clock_timing[i].cs_to_clk_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; + device_ss_clock_timing[i].clk_to_cs_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; + spi_dev[i].cs_to_cs_delay_ticks = SPI_MASTER_DEFAULT_SS_CLOCK_DELAY_TICKS; + device_miso_capture_timing[i].miso_pad_delay = spi_master_sample_delay_1_2; // Half a SPI clock + device_miso_capture_timing[i].miso_sample_delay = 0; // Default no delay + } + } + } else { + unsafe{ + set_port_clock(p_ss, (clock)XS1_CLKBLK_REF); + set_port_clock(p_sclk, (clock)XS1_CLKBLK_REF); + if(!isnull(p_miso)){ + set_port_clock(p_miso, (clock)XS1_CLKBLK_REF); + } + if(!isnull(p_mosi)){ + set_port_clock(p_mosi, (clock)XS1_CLKBLK_REF); + } + } + // Initial SS bit pattern - deselected + p_ss <: 0xffffffff; + sync(p_ss); + + } + + int accepting_new_transactions = 1; + + // By default use the port bit which is the number of the slave (slave 0 uses port bit 0 etc.) + uint8_t ss_port_bit[num_slaves]; + for(int i = 0; i < num_slaves; i++){ + ss_port_bit[i] = i; + } + + + while(1){ + select { + case accepting_new_transactions => i[int x].begin_transaction(unsigned device_index, + unsigned speed_in_khz, spi_mode_t mode):{ + accepting_new_transactions = 0; + current_device = device_index; + + // Grab mode bits + cpol = mode >> 1; + cpha = mode & 0x1; + + // Fast SPI state + spi_master_source_clock_t source_clock; + unsigned divider; + + if(isnull(cb)){ + // Set the expected clock idle state on the clock port + partout(p_sclk, 1, cpol); + sync(p_sclk); + + unsigned ss_port_val = ~(1 << ss_port_bit[current_device]); + p_ss <: ss_port_val; + clkblkless_period_ticks = (XS1_TIMER_KHZ + speed_in_khz - 1) / speed_in_khz; // round up (rounds speed down) + } else { + spi_master_determine_clock_settings(&source_clock, ÷r, speed_in_khz); + +#if SPI_DEBUG_REPORT_ACTUAL_SPEED + unsigned actual_speed_khz = spi_master_get_actual_clock_rate(source_clock, divider); + printf("Actual speed_in_khz: %u div(%u) clock: (%s) %uMHz\n", + actual_speed_khz, + divider, + ((source_clock == spi_master_source_clock_ref) ? "ref" : "core"), + ((source_clock == spi_master_source_clock_ref) ? PLATFORM_REFERENCE_MHZ : PLATFORM_NODE_0_SYSTEM_FREQUENCY_MHZ)); +#endif + + spi_master_device_init(&spi_dev[current_device], &spi_master, + ss_port_bit[current_device], + cpol, cpha, + source_clock, + divider, + device_miso_capture_timing[current_device].miso_sample_delay, + device_miso_capture_timing[current_device].miso_pad_delay, + device_ss_clock_timing[current_device].clk_to_cs_delay_ticks, + device_ss_clock_timing[current_device].cs_to_clk_delay_ticks, + spi_dev[current_device].cs_to_cs_delay_ticks); // Write same value back + + spi_master_start_transaction(&spi_dev[current_device]); + } + + break; + } + + case i[int x].end_transaction(unsigned ss_deassert_time):{ + if(isnull(cb)){ + p_ss <: 0xffffffff; + delay_ticks(ss_deassert_time); + } else { + spi_dev[current_device].cs_to_cs_delay_ticks = ss_deassert_time; + spi_master_end_transaction(&spi_dev[current_device]); + } + + // Unlock the transaction + accepting_new_transactions = 1; + + break; + } + + case i[int x].transfer8(uint8_t data)-> uint8_t r :{ + if(isnull(cb)){ + r = transfer8_sync_zero_clkblk(p_sclk, p_mosi, p_miso, data, clkblkless_period_ticks, cpol, cpha); + } else { + spi_master_transfer(&spi_dev[current_device], (uint8_t *)&data, &r, 1); + } + + break; + } + + case i[int x].transfer32(uint32_t data) -> uint32_t r:{ + if(isnull(cb)){ + r = transfer32_sync_zero_clkblk(p_sclk, p_mosi, p_miso, data, clkblkless_period_ticks, cpol, cpha); + } else { + // For 32b words, we need to swap to big endian (standard for SPI) from little endian (XMOS) + // This means we transmit the MSByte first + data = byterev(data); + uint32_t read_val; + spi_master_transfer(&spi_dev[current_device], (uint8_t *)&data, (uint8_t *)&read_val, 4); + r = byterev(read_val); + } + + break; + } + + case i[int x].transfer_array(NULLABLE_ARRAY_OF(const uint8_t, data_out), NULLABLE_ARRAY_OF(uint8_t, data_in), static const size_t num_bytes):{ + if(isnull(cb)){ + for(int n = 0; n < num_bytes; n++){ + uint8_t send; + if(!isnull(p_mosi)){ + send = data_out[n]; + } + uint8_t recv = transfer8_sync_zero_clkblk(p_sclk, p_mosi, p_miso, send, clkblkless_period_ticks, cpol, cpha); + if(!isnull(p_miso)){ + data_in[n] = recv; + } + } + } else { + // Remote references not allowed in XC so need to memcpy + uint8_t data[num_bytes]; + if(!isnull(data_out)){ + memcpy(data, data_out, num_bytes); + } + unsafe{ + // Do in-place transfer + uint8_t * unsafe data_alias = data; + spi_master_transfer(&spi_dev[current_device], data, data_alias, num_bytes); + } + if(!isnull(data_in)){ + memcpy(data_in, data, num_bytes); + } + } + + break; + } + + case i[int x].set_ss_port_bit(unsigned device_index, unsigned port_bit):{ + if(device_index > num_slaves){ + printstrln("Invalid port bit - must be less than num_slaves"); + } + ss_port_bit[device_index] = port_bit; + + break; + } + + case i[int x].set_miso_capture_timing(unsigned device_index, spi_master_miso_capture_timing_t miso_capture_timing):{ + device_miso_capture_timing[x] = miso_capture_timing; + break; + } + + case i[int x].set_ss_clock_timing(unsigned device_index, spi_master_ss_clock_timing_t ss_clock_timing):{ + device_ss_clock_timing[x] = ss_clock_timing; + break; + } + + case i[int x].shutdown(void):{ + p_ss <: 0xffffffff; + // If using XC, then we need to enable/init which is how XC does it + if (!isnull(p_mosi)) { + set_port_use_on(p_mosi); + } + if (!isnull(p_miso)) { + set_port_use_on(p_miso); + } + set_port_use_on(p_sclk); + if(!isnull(cb)){ + set_clock_on(cb); + } + + return; + } + } + } + +} diff --git a/lib_spi/src/spi_slave.xc b/lib_spi/src/spi_slave.xc index 896f468..c045cd8 100644 --- a/lib_spi/src/spi_slave.xc +++ b/lib_spi/src/spi_slave.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include @@ -19,124 +19,151 @@ void spi_slave(client spi_slave_callback_if spi_i, static const spi_mode_t mode, static const spi_transfer_type_t transfer_type){ - //first setup the ports - - set_port_inv(ss); - - stop_clock(clk); - set_clock_src(clk, sclk); - - if(!isnull(miso)) - configure_out_port_strobed_slave(miso, ss, clk, 0); - configure_in_port_strobed_slave(mosi, ss, clk); - - start_clock(clk); - - switch(mode){ - case SPI_MODE_0: - case SPI_MODE_2: - set_port_inv(sclk); - break; - case SPI_MODE_1: - case SPI_MODE_3: - set_port_no_inv(sclk); - break; - } - sync(sclk); - - int ss_val; - - //set the transfer width - if(transfer_type == SPI_TRANSFER_SIZE_8){ - if(!isnull(miso)) - asm volatile ("settw res[%0], %1"::"r"(miso), "r"(8)); - asm volatile ("settw res[%0], %1"::"r"(mosi), "r"(8)); - } - - uint32_t buffer; - - ss when pinseq(!ASSERTED) :> ss_val; - while(1){ - select { - case ss when pinsneq(ss_val) :> ss_val:{ - - if(!isnull(miso)) - clearbuf(miso); - - if(ss_val != ASSERTED){ - unsigned remaining_bits = endin(mosi); - uint32_t data; - mosi :> data; - if(remaining_bits){ //FIXME can this be more then tw? - data = bitrev(data); - if(transfer_type == SPI_TRANSFER_SIZE_8) - data >>= (32-8); - spi_i.master_supplied_data(data, remaining_bits); - } - clearbuf(mosi); - spi_i.master_ends_transaction(); - break; - } - if(!isnull(miso)){ - uint32_t data = spi_i.master_requires_data(); - - if(transfer_type == SPI_TRANSFER_SIZE_8){ - data = (bitrev(data)>>24); - if((mode == SPI_MODE_1) || (mode == SPI_MODE_2)){ - asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(XS1_CLKBLK_REF)); - partout(miso, 1, data); - asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(clk)); - data = data>>1; - partout(miso, 7, data); - } else { - partout(miso, 8, data); - } + //first setup the ports + + set_port_inv(ss); + + stop_clock(clk); + set_clock_src(clk, sclk); + + configure_in_port_strobed_slave(mosi, ss, clk); + if(!isnull(miso)){ + set_port_use_on(miso); // Set to Hi-Z (input) and reset port + asm volatile ("setc res[%0], %1"::"r"(miso), "r"(XS1_SETC_BUF_BUFFERS)); // Switch to buffered mode + } + + // note do NOT configure MISO yet. We will leave this as an input so Hi-Z + + start_clock(clk); + + switch(mode){ + case SPI_MODE_1: + case SPI_MODE_2: + set_port_inv(sclk); + break; + case SPI_MODE_0: + case SPI_MODE_3: + set_port_no_inv(sclk); + break; + } + sync(sclk); + + int ss_val; + uint32_t buffer; + + // Wait for de-assert + ss when pinseq(!ASSERTED) :> ss_val; + + while(1){ + select { + case ss when pinsneq(ss_val) :> ss_val:{ + if(!isnull(miso)){ + clearbuf(miso); + } + + if(ss_val != ASSERTED){ + // Make MISO go Hi-Z if SS not asserted. It will switch + // to output again on the next out or partout + if(!isnull(miso)){ + set_port_use_on(miso); // Set to Hi-Z and reset + asm volatile ("setc res[%0], %1"::"r"(miso), "r"(XS1_SETC_BUF_BUFFERS)); // Switch to buffered mode + } + unsigned remaining_bits = endin(mosi); + uint32_t data; + // Make MISO go Hi-Z if SS not asserted. It will switch + // to output again on the next out or partout + mosi :> data; + if(remaining_bits){ //FIXME can this be more then tw? + data = bitrev(data); + if(transfer_type == SPI_TRANSFER_SIZE_8) + data >>= (32-8); + spi_i.master_supplied_data(data, remaining_bits); + } + clearbuf(mosi); + spi_i.master_ends_transaction(); + break; + } + + // ss_val == ASSERTED + if(!isnull(miso)){ + uint32_t data = spi_i.master_requires_data(); + // Note port is only configured as buffered input at the moment + + if(transfer_type == SPI_TRANSFER_SIZE_8){ + data = (bitrev(data)>>24); + // Send data before clock. Use ref clock to allow port to output in absence of SPI clock + if((mode == SPI_MODE_0) || (mode == SPI_MODE_2)){ + asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(XS1_CLKBLK_REF)); + partout(miso, 1, data); + asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(clk)); + data = data>>1; + partout(miso, 7, data); + } else { + asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(clk)); // Attach to SPI clock + partout(miso, 8, data); + } } else { - data = bitrev(data); - if((mode == SPI_MODE_1) || (mode == SPI_MODE_2)){ - asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(XS1_CLKBLK_REF)); - partout(miso, 1, data); - asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(clk)); - data = data>>1; - partout(miso, 31, data); - } else { - miso <: data; - } - } - buffer = spi_i.master_requires_data(); - - if(transfer_type == SPI_TRANSFER_SIZE_8){ - buffer = (bitrev(buffer)>>24); - } else { - buffer = bitrev(buffer); - } - } - clearbuf(mosi); - break; - } - - case mosi :> int i:{ - if(transfer_type == SPI_TRANSFER_SIZE_8){ - if(!isnull(miso)){ - //clearbuf(miso);//FIXME this is not correct - do something better - partout(miso, 8, buffer); - buffer = spi_i.master_requires_data(); - buffer = (bitrev(buffer)>>24); - } - spi_i.master_supplied_data(bitrev(i)>>24, 8); - - } else { - if(!isnull(miso)){ - //clearbuf(miso);//FIXME this is not correct - do something better - miso <: buffer; - buffer = spi_i.master_requires_data(); - buffer = bitrev(buffer); - } - spi_i.master_supplied_data(bitrev(i), 32); - } - break; - } - - } - } - } + data = bitrev(data); + // Send data before clock. Use ref clock to allow port to output in absence of SPI clock + if((mode == SPI_MODE_0) || (mode == SPI_MODE_2)){ + asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(XS1_CLKBLK_REF)); + partout(miso, 1, data); + asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(clk)); + data = data>>1; + partout(miso, 31, data); + } else { + asm volatile ("setclk res[%0], %1"::"r"(miso), "r"(clk)); // Attach to SPI clock + miso <: data; + } + } + buffer = spi_i.master_requires_data(); + + if(transfer_type == SPI_TRANSFER_SIZE_8){ + buffer = (bitrev(buffer)>>24); + } else { + buffer = bitrev(buffer); + } + } // !isnull(miso) + clearbuf(mosi); + if(transfer_type == SPI_TRANSFER_SIZE_8){ + asm volatile ("settw res[%0], %1"::"r"(mosi), "r"(8)); // Transfer width + } + break; + } // case ss + + case mosi :> int i:{ + if(transfer_type == SPI_TRANSFER_SIZE_8){ + if(!isnull(miso)){ + //clearbuf(miso);//FIXME this is not correct - do something better + partout(miso, 8, buffer); + buffer = spi_i.master_requires_data(); + buffer = (bitrev(buffer)>>24); + } + spi_i.master_supplied_data(bitrev(i)>>24, 8); + } else { + if(!isnull(miso)){ + //clearbuf(miso);//FIXME this is not correct - do something better + miso <: buffer; + buffer = spi_i.master_requires_data(); + buffer = bitrev(buffer); + } + spi_i.master_supplied_data(bitrev(i), 32); + } + break; + } // case mosi + + case spi_i.request_shutdown():{ + set_port_use_on(mosi); + if (!isnull(miso)) { + set_port_use_on(miso); + } + set_port_use_on(sclk); + set_port_use_on(ss); + set_clock_on(clk); + spi_i.shutdown_complete(); + return; + break; + } + } // select + } // while(1) +} diff --git a/lib_spi/src/spi_sync.xc b/lib_spi/src/spi_sync.xc deleted file mode 100644 index e1c7577..0000000 --- a/lib_spi/src/spi_sync.xc +++ /dev/null @@ -1,347 +0,0 @@ -// Copyright 2015-2021 XMOS LIMITED. -// This Software is subject to the terms of the XMOS Public Licence: Version 1. -#include -#include -#include -#include - -#include "spi.h" - -static const uint16_t ziptable[256] = { 0x0000, 0xc000, 0x3000, 0xf000, 0x0c00, - 0xcc00, 0x3c00, 0xfc00, 0x0300, 0xc300, 0x3300, 0xf300, 0x0f00, 0xcf00, - 0x3f00, 0xff00, 0x00c0, 0xc0c0, 0x30c0, 0xf0c0, 0x0cc0, 0xccc0, 0x3cc0, - 0xfcc0, 0x03c0, 0xc3c0, 0x33c0, 0xf3c0, 0x0fc0, 0xcfc0, 0x3fc0, 0xffc0, - 0x0030, 0xc030, 0x3030, 0xf030, 0x0c30, 0xcc30, 0x3c30, 0xfc30, 0x0330, - 0xc330, 0x3330, 0xf330, 0x0f30, 0xcf30, 0x3f30, 0xff30, 0x00f0, 0xc0f0, - 0x30f0, 0xf0f0, 0x0cf0, 0xccf0, 0x3cf0, 0xfcf0, 0x03f0, 0xc3f0, 0x33f0, - 0xf3f0, 0x0ff0, 0xcff0, 0x3ff0, 0xfff0, 0x000c, 0xc00c, 0x300c, 0xf00c, - 0x0c0c, 0xcc0c, 0x3c0c, 0xfc0c, 0x030c, 0xc30c, 0x330c, 0xf30c, 0x0f0c, - 0xcf0c, 0x3f0c, 0xff0c, 0x00cc, 0xc0cc, 0x30cc, 0xf0cc, 0x0ccc, 0xcccc, - 0x3ccc, 0xfccc, 0x03cc, 0xc3cc, 0x33cc, 0xf3cc, 0x0fcc, 0xcfcc, 0x3fcc, - 0xffcc, 0x003c, 0xc03c, 0x303c, 0xf03c, 0x0c3c, 0xcc3c, 0x3c3c, 0xfc3c, - 0x033c, 0xc33c, 0x333c, 0xf33c, 0x0f3c, 0xcf3c, 0x3f3c, 0xff3c, 0x00fc, - 0xc0fc, 0x30fc, 0xf0fc, 0x0cfc, 0xccfc, 0x3cfc, 0xfcfc, 0x03fc, 0xc3fc, - 0x33fc, 0xf3fc, 0x0ffc, 0xcffc, 0x3ffc, 0xfffc, 0x0003, 0xc003, 0x3003, - 0xf003, 0x0c03, 0xcc03, 0x3c03, 0xfc03, 0x0303, 0xc303, 0x3303, 0xf303, - 0x0f03, 0xcf03, 0x3f03, 0xff03, 0x00c3, 0xc0c3, 0x30c3, 0xf0c3, 0x0cc3, - 0xccc3, 0x3cc3, 0xfcc3, 0x03c3, 0xc3c3, 0x33c3, 0xf3c3, 0x0fc3, 0xcfc3, - 0x3fc3, 0xffc3, 0x0033, 0xc033, 0x3033, 0xf033, 0x0c33, 0xcc33, 0x3c33, - 0xfc33, 0x0333, 0xc333, 0x3333, 0xf333, 0x0f33, 0xcf33, 0x3f33, 0xff33, - 0x00f3, 0xc0f3, 0x30f3, 0xf0f3, 0x0cf3, 0xccf3, 0x3cf3, 0xfcf3, 0x03f3, - 0xc3f3, 0x33f3, 0xf3f3, 0x0ff3, 0xcff3, 0x3ff3, 0xfff3, 0x000f, 0xc00f, - 0x300f, 0xf00f, 0x0c0f, 0xcc0f, 0x3c0f, 0xfc0f, 0x030f, 0xc30f, 0x330f, - 0xf30f, 0x0f0f, 0xcf0f, 0x3f0f, 0xff0f, 0x00cf, 0xc0cf, 0x30cf, 0xf0cf, - 0x0ccf, 0xcccf, 0x3ccf, 0xfccf, 0x03cf, 0xc3cf, 0x33cf, 0xf3cf, 0x0fcf, - 0xcfcf, 0x3fcf, 0xffcf, 0x003f, 0xc03f, 0x303f, 0xf03f, 0x0c3f, 0xcc3f, - 0x3c3f, 0xfc3f, 0x033f, 0xc33f, 0x333f, 0xf33f, 0x0f3f, 0xcf3f, 0x3f3f, - 0xff3f, 0x00ff, 0xc0ff, 0x30ff, 0xf0ff, 0x0cff, 0xccff, 0x3cff, 0xfcff, - 0x03ff, 0xc3ff, 0x33ff, 0xf3ff, 0x0fff, 0xcfff, 0x3fff, 0xffff -}; - -static const uint8_t unshuffle[256] = { - 0x00, 0x10, 0x01, 0x11, 0x20, 0x30, 0x21, 0x31, - 0x02, 0x12, 0x03, 0x13, 0x22, 0x32, 0x23, 0x33, - 0x40, 0x50, 0x41, 0x51, 0x60, 0x70, 0x61, 0x71, - 0x42, 0x52, 0x43, 0x53, 0x62, 0x72, 0x63, 0x73, - 0x04, 0x14, 0x05, 0x15, 0x24, 0x34, 0x25, 0x35, - 0x06, 0x16, 0x07, 0x17, 0x26, 0x36, 0x27, 0x37, - 0x44, 0x54, 0x45, 0x55, 0x64, 0x74, 0x65, 0x75, - 0x46, 0x56, 0x47, 0x57, 0x66, 0x76, 0x67, 0x77, - 0x80, 0x90, 0x81, 0x91, 0xa0, 0xb0, 0xa1, 0xb1, - 0x82, 0x92, 0x83, 0x93, 0xa2, 0xb2, 0xa3, 0xb3, - 0xc0, 0xd0, 0xc1, 0xd1, 0xe0, 0xf0, 0xe1, 0xf1, - 0xc2, 0xd2, 0xc3, 0xd3, 0xe2, 0xf2, 0xe3, 0xf3, - 0x84, 0x94, 0x85, 0x95, 0xa4, 0xb4, 0xa5, 0xb5, - 0x86, 0x96, 0x87, 0x97, 0xa6, 0xb6, 0xa7, 0xb7, - 0xc4, 0xd4, 0xc5, 0xd5, 0xe4, 0xf4, 0xe5, 0xf5, - 0xc6, 0xd6, 0xc7, 0xd7, 0xe6, 0xf6, 0xe7, 0xf7, - 0x08, 0x18, 0x09, 0x19, 0x28, 0x38, 0x29, 0x39, - 0x0a, 0x1a, 0x0b, 0x1b, 0x2a, 0x3a, 0x2b, 0x3b, - 0x48, 0x58, 0x49, 0x59, 0x68, 0x78, 0x69, 0x79, - 0x4a, 0x5a, 0x4b, 0x5b, 0x6a, 0x7a, 0x6b, 0x7b, - 0x0c, 0x1c, 0x0d, 0x1d, 0x2c, 0x3c, 0x2d, 0x3d, - 0x0e, 0x1e, 0x0f, 0x1f, 0x2e, 0x3e, 0x2f, 0x3f, - 0x4c, 0x5c, 0x4d, 0x5d, 0x6c, 0x7c, 0x6d, 0x7d, - 0x4e, 0x5e, 0x4f, 0x5f, 0x6e, 0x7e, 0x6f, 0x7f, - 0x88, 0x98, 0x89, 0x99, 0xa8, 0xb8, 0xa9, 0xb9, - 0x8a, 0x9a, 0x8b, 0x9b, 0xaa, 0xba, 0xab, 0xbb, - 0xc8, 0xd8, 0xc9, 0xd9, 0xe8, 0xf8, 0xe9, 0xf9, - 0xca, 0xda, 0xcb, 0xdb, 0xea, 0xfa, 0xeb, 0xfb, - 0x8c, 0x9c, 0x8d, 0x9d, 0xac, 0xbc, 0xad, 0xbd, - 0x8e, 0x9e, 0x8f, 0x9f, 0xae, 0xbe, 0xaf, 0xbf, - 0xcc, 0xdc, 0xcd, 0xdd, 0xec, 0xfc, 0xed, 0xfd, - 0xce, 0xde, 0xcf, 0xdf, 0xee, 0xfe, 0xef, 0xff -}; - - - -#pragma unsafe arrays -static uint8_t transfer8_sync_zero_clkblk( - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 ?miso, - uint8_t data, const unsigned period, - unsigned cpol, unsigned cpha){ - unsigned time, d, c = 0xaaaa>>(cpol ^ cpha); - time = partout_timestamped(sclk, 1, cpol); - time += 40; - - for(unsigned i=0;i<8;i++){ - partout_timed(sclk, 1, c, time); - c>>=1; - //sclk @ time <:>> c; - - if(!isnull(mosi)){ - partout_timed(mosi, 1, data>>7, time); - data<<=1; - } - time += period / 2; - - partout_timed(sclk, 1, c, time); - c>>=1; - if(!isnull(miso)){ - unsigned t; - miso @ time - 1 :> t; - d = (d<<1) + (t&1); - } - time += (period + 1)/2; - } - partout_timed(sclk, 1, cpol, time); - sync(sclk); - return d; -} - -#pragma unsafe arrays -static uint32_t transfer32_sync_zero_clkblk( - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 ?miso, - uint32_t data, const unsigned period, - const unsigned cpol, const unsigned cpha){ - unsigned time; - uint32_t d; - time = partout_timestamped(sclk, 1, cpol); - time += 100; - - //bitrev the data - for(unsigned j=0;j<2;j++){ - unsigned c = 0xaaaaaaaa>>(cpol ^ cpha); - for(unsigned i=0;i<16;i++){ - partout_timed(sclk, 1, c, time); - if(!isnull(mosi)){ - partout_timed(mosi, 1, data>>31, time); - data<<=1; - } - c>>=1; - time += period / 2; - partout_timed(sclk, 1, c, time); - c>>=1; - if(!isnull(miso)){ - unsigned t; - miso @ time - 1 :> t; - d = (d<<1) + (t&1); - } - time += (period + 1)/2; - } - time += 80; - } - partout_timed(sclk, 1, cpol, time); - sync(sclk); - return d; -} - -#pragma unsafe arrays -static unsigned zip8(uint8_t a){ - return ziptable[a]; -} - -#pragma unsafe arrays -static void zip32(uint32_t a, uint32_t &x, uint32_t &y){ - //This can be improved - y = zip8(a&0xff); - a=a>>8; - y = (y << 16)| (zip8(a&0xff)); - a=a>>8; - x = zip8(a&0xff); - a=a>>8; - x = (x << 16)| (zip8(a&0xff)); -} - -#pragma unsafe arrays -static uint8_t unzip_16(unsigned d){ - d = d & 0x55aa; - d = d | (d>>8); - return bitrev(unshuffle[d&0xff])>>24; -} - -#pragma unsafe arrays -static uint16_t unzip_32(unsigned d){ - return unzip_16(d&0xffff) |(unzip_16(d>>16)<<8); -} - -static unsigned make_8bit_clock(unsigned cpol, unsigned cpha){ - return (0xaaaa >> (cpha)) ^ - cpol; -} -static uint8_t transfer8_sync_one_clkblk( - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 ?miso, - uint8_t data, - unsigned cpol, unsigned cpha){ - unsigned double_clock = make_8bit_clock(cpol, cpha); - uint16_t double_data = zip8(data); - unsigned t = partout_timestamped(sclk, 1, cpol); - t+=80; - partout_timed(sclk, 17, double_clock, t); - if(!isnull(mosi))partout_timed(mosi, 16, double_data, t); - if(!isnull(miso)) miso @ t + 31 :> double_data; - return unzip_16(double_data); -} - -static uint32_t transfer32_sync_one_clkblk( - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 ?miso, - uint32_t data, - unsigned cpol, unsigned cpha){ - - unsigned t; - unsigned double_clock = 0xaaaaaaaa>>(cpol ^ cpha); - - uint32_t double_data_0; - uint32_t double_data_1; - zip32(data, double_data_0, double_data_1); - t = partout_timestamped(sclk, 1, cpol); - t+=80; - sclk @ t <: double_clock; - if(!isnull(mosi))mosi @ t<: double_data_0; - sclk <: double_clock; - if(!isnull(mosi))mosi <: double_data_1; - if(!isnull(miso))miso @ t + 31:> double_data_0; - if(!isnull(miso))miso :> double_data_1; - - return byterev(unzip_32(double_data_0) | (unzip_32(double_data_1)<<16)); -} - -static void get_mode_bits(spi_mode_t mode, unsigned &cpol, unsigned &cpha){ - switch(mode){ - case SPI_MODE_0:cpol = 0; cpha= 1; break; - case SPI_MODE_1:cpol = 0; cpha= 0; break; - case SPI_MODE_2:cpol = 1; cpha= 0; break; - case SPI_MODE_3:cpol = 1; cpha= 1; break; - } -} - -///////////////////////////////////////////////////////////////////////////////////////////////////// -#pragma unsafe arrays -[[distributable]] -void spi_master(server interface spi_master_if i[num_clients], - static const size_t num_clients, - out buffered port:32 sclk, - out buffered port:32 ?mosi, - in buffered port:32 ?miso, - out port p_ss[num_slaves], - static const size_t num_slaves, - clock ?cb){ - - for(unsigned i=0;i i[int x].begin_transaction(unsigned device_index, - unsigned speed_in_khz, spi_mode_t mode):{ - //Get the mode bits from the spi_mode - get_mode_bits(mode, cpol, cpha); - - //xassert(device_index < num_slaves); - if (!isnull(cb)){ - set_port_use_on(sclk); - configure_out_port(sclk, cb, 0); - } - - sync(sclk); - //Wait for the chip deassert time if need be - if(device_index == selected_device) - sync(p_ss[selected_device]); - - //Set the expected clock idle state on the clock port - partout(sclk, 1, cpol); - sync(sclk); - - if(isnull(cb)){ - //Calculate the clock period from the speed_in_khz - period = (XS1_TIMER_KHZ + speed_in_khz - 1)/speed_in_khz;//round up - } else { - //Set the clock divider - stop_clock(cb); - unsigned d = (XS1_TIMER_KHZ + 4*speed_in_khz - 1)/(4*speed_in_khz);//FIXME this has to round up too - configure_clock_ref(cb, d); - start_clock(cb); - } - - //Lock the begin transaction - accepting_new_transactions = 0; - - //Do a slave select - selected_device = device_index; - p_ss[selected_device] <: 0; - break; - } - case i[int x].end_transaction(unsigned ss_deassert_time):{ - //Unlock the transaction - accepting_new_transactions = 1; - - unsigned time; - partout(sclk, 1, cpol); - sync(sclk); - p_ss[selected_device] <: 1 @ time; - - //TODO should this be allowed? (0.6ms max without it) - if(ss_deassert_time > 0xffff) - delay_ticks(ss_deassert_time&0xffff0000); - - time += ss_deassert_time; - - p_ss[selected_device] @ time <: 1; - break; - } - case i[int x].transfer8(uint8_t data)-> uint8_t r :{ - if(isnull(cb)) { - r = transfer8_sync_zero_clkblk(sclk, mosi, miso, data, period, cpol, cpha); - } else { - r = transfer8_sync_one_clkblk(sclk, mosi, miso, data, cpol, cpha); - } - break; - } - case i[int x].transfer32(uint32_t data) -> uint32_t r:{ - if(isnull(cb)) { - r = transfer32_sync_zero_clkblk(sclk, mosi, miso, data, period, cpol, cpha); - } else { - r = transfer32_sync_one_clkblk(sclk, mosi, miso, data, cpol, cpha); - } - break; - } - } - } - -} - diff --git a/lib_spi/wscript b/lib_spi/wscript deleted file mode 100644 index 2177865..0000000 --- a/lib_spi/wscript +++ /dev/null @@ -1,6 +0,0 @@ -def use_module(bld): - bld.env['XCC_FLAGS_spi_async.xc'] = bld.env.XCC_FLAGS + [ - '-Wno-reinterpret-alignment' - ] - source = bld.path.ant_glob('src/*.xc') - bld.module(source=source, includes=['api'], version='3.3.0') diff --git a/python/reset_xtags.py b/python/reset_xtags.py deleted file mode 100644 index 62e0f3b..0000000 --- a/python/reset_xtags.py +++ /dev/null @@ -1,31 +0,0 @@ -# Copyright 2020-2021 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -""" This script is used to reset one or more targets using xtagctl -""" -import traceback -import xtagctl -import sys - -if __name__ == "__main__": - if len(sys.argv) > 1: - num_xtags = int(sys.argv[1]) - else: - num_xtags = 1 - - targets = ["XCORE-AI-EXPLORER"] * num_xtags - print(f"XTAGCTL acquiring targets: {targets}") - with xtagctl.acquire(*targets, timeout=10) as adapter_ids: - if type(adapter_ids) is str: - adapter_id_list = [adapter_ids] - else: - adapter_id_list = adapter_ids - print(adapter_id_list) - - for adapter_id in adapter_id_list: - print(f"acquiring adapter_id: {adapter_id}") - try: - xtagctl.reset_adapter(adapter_id) - print("Successfully reset XTAG") - except xtagctl.XtagctlException: - print("WARNING: Could not reset xtag!") - traceback.print_exc() diff --git a/python/setup.py b/python/setup.py deleted file mode 100644 index c169625..0000000 --- a/python/setup.py +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright 2020-2021 XMOS LIMITED. -# This Software is subject to the terms of the XMOS Public Licence: Version 1. -import setuptools - -# Another repository might depend on python code defined in this one. The -# procedure to set up a suitable python environment for that repository may -# pip-install this one as editable using this setup.py file. To minimise the -# chance of version conflicts while ensuring a minimal degree of conformity, -# the 3rd-party modules listed here require the same major version and at -# least the same minor version as specified in the requirements.txt file. -# The same modules should appear in the requirements.txt file as given below. -setuptools.setup( - name='lib_spi', - packages=setuptools.find_packages(), - install_requires=[ - 'flake8~=3.8', - ], - dependency_links=[ - ], -) diff --git a/settings.yml b/settings.yml new file mode 100644 index 0000000..e9f5f3c --- /dev/null +++ b/settings.yml @@ -0,0 +1,27 @@ +# This file relates to internal XMOS infrastructure and should be ignored by external users +--- +lib_name: lib_spi +project: '{{lib_name}}' +title: '{{lib_name}}: SPI Library' +version: 4.0.0 + +documentation: + exclude_patterns_path: doc/exclude_patterns.inc + root_doc: doc/rst/lib_spi.rst + linkcheck_ignore_regex: [''] + latex_toc_depth: 3 + latex_secnum_depth: 3 + cognidox_part_number: XM-006232-UG + doxygen_projects: + lib_spi: + doxyfile_path: doc/Doxyfile.inc + pdfs: + doc/rst/lib_spi.rst: + pdf_title: '{{title}}' + pdf_filename: '{{lib_name}}_v{{version}}' + README.rst: + pdf_title: '{{title}} (README)' + pdf_filename: '{{lib_name}}_v{{version}}_readme' + pdf_short: yes +software: + cognidox_part_number: XM-007474-SM diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt new file mode 100644 index 0000000..b663fe6 --- /dev/null +++ b/tests/CMakeLists.txt @@ -0,0 +1,17 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) +project(lib_spi_tests) + +add_subdirectory(spi_master_sync_benchmark) +add_subdirectory(spi_master_sync_rx_tx) +add_subdirectory(spi_master_sync_multi_device) +add_subdirectory(spi_master_sync_multi_client) +add_subdirectory(spi_master_sync_clock_port_sharing) +add_subdirectory(spi_master_sync_shutdown) +add_subdirectory(spi_slave_benchmark) +add_subdirectory(spi_slave_rx_tx) +add_subdirectory(spi_slave_shutdown) +add_subdirectory(spi_master_async_rx_tx) +add_subdirectory(spi_master_async_multi_client) +add_subdirectory(spi_master_async_multi_device) +add_subdirectory(spi_master_async_shutdown) diff --git a/tests/conftest.py b/tests/conftest.py new file mode 100644 index 0000000..142e77e --- /dev/null +++ b/tests/conftest.py @@ -0,0 +1,27 @@ +# Copyright 2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +import pytest + +# from https://github.com/pytest-dev/pytest/issues/3730#issuecomment-567142496 +def pytest_configure(config): + config.addinivalue_line( + "markers", "uncollect_if(*, func): function to unselect tests from parametrization" + ) + +def pytest_collection_modifyitems(config, items): + removed = [] + kept = [] + for item in items: + m = item.get_closest_marker('uncollect_if') + if m: + func = m.kwargs['func'] + if func(**item.callspec.params): + removed.append(item) + continue + kept.append(item) + if removed: + config.hook.pytest_deselected(items=removed) + items[:] = kept + +def pytest_addoption(parser): + parser.addoption("--testlevel") diff --git a/tests/expected/master_multi_device.expect b/tests/expected/master_multi_device.expect new file mode 100644 index 0000000..b960bc0 --- /dev/null +++ b/tests/expected/master_multi_device.expect @@ -0,0 +1,5 @@ +SPI Master checker started +Transfers to device 0 complete +Transfers to device 1 complete +Transfers to device 0 complete +Transfers to device 1 complete diff --git a/legacy_tests/master.expect b/tests/expected/master_sync.expect similarity index 58% rename from legacy_tests/master.expect rename to tests/expected/master_sync.expect index 1bd90db..8903669 100644 --- a/legacy_tests/master.expect +++ b/tests/expected/master_sync.expect @@ -1 +1,2 @@ SPI Master checker started +Transfers complete diff --git a/tests/expected/slave.expect b/tests/expected/slave.expect new file mode 100644 index 0000000..0154375 --- /dev/null +++ b/tests/expected/slave.expect @@ -0,0 +1,36 @@ +SPI Slave checker started +Send initial settings +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 128 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 1 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 2 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 3 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 4 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 5 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 6 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 7 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 8 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 9 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 10 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 11 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 12 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 13 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 14 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 15 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 16 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 17 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 18 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 19 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 20 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 21 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 22 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 23 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 24 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 25 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 26 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 27 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 28 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 29 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 30 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 31 kbps \d+ init delay \d+ +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 32 kbps \d+ init delay \d+ +Test completed diff --git a/tests/expected/slave_intertransaction.expect b/tests/expected/slave_intertransaction.expect new file mode 100644 index 0000000..c03ef1c --- /dev/null +++ b/tests/expected/slave_intertransaction.expect @@ -0,0 +1,5 @@ +SPI Slave checker started +Send initial settings +Got Settings:cpol [0-1]{1} cpha [0-1]{1} miso [0-1]{1} num_bits 128 kbps \d+ init delay \d+ +Delay is \d+.\d+ ns +(Request exit on success|Request exit on error){1} diff --git a/tests/helpers.py b/tests/helpers.py new file mode 100644 index 0000000..7d17ff6 --- /dev/null +++ b/tests/helpers.py @@ -0,0 +1,132 @@ +# Copyright 2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +import os +import random +import sys +import Pyxsim as px +import pytest +import json +import csv +import threading +import itertools +from filelock import FileLock +from itertools import zip_longest + +# Thread safe create a folder +def create_if_needed(folder): + lock_path = f"{folder}.lock" + # xdist can cause race conditions so use a lock + with FileLock(lock_path): + if not os.path.exists(folder): + os.makedirs(folder) + return folder + +# Read a JSON and get the test configs and IDs. Pass the JSON files +def generate_tests_from_json(test_params_json): + with open(test_params_json) as f: + params = json.load(f) + + # Prepare keys and values + keys = [] + values = [] + + for key, val_or_dict_list in params.items(): + if isinstance(val_or_dict_list[0], dict): + # Instead of keeping the key, we flatten the dicts inside the list + combined_keys = list(val_or_dict_list[0].keys()) # "COMBINED", "BURNT_THREADS" + # Save separate keys for later flattening + keys.extend(combined_keys) + # Convert list of dicts to list of tuples (flattened for combinations) + values.append([tuple(d[k] for k in combined_keys) for d in val_or_dict_list]) + else: + keys.append(key) + values.append(val_or_dict_list) + + # Generate combinations + combinations = itertools.product(*values) + + # Build final output + test_config_ids = [] + test_configs = [] + for combo in combinations: + test_config_id = {} + + key_idx = 0 + for val in combo: + if isinstance(val, tuple): # This only happens for THREAD_PROFILES + for subval in val: + key = keys[key_idx] + test_config_id[key] = subval + key_idx += 1 + else: + key = keys[key_idx] + test_config_id[key] = val + key_idx += 1 + + test_config = list(test_config_id.values()) + test_config_id = ", ".join(f"{k}={v}" for k, v in test_config_id.items()) + # print(test_config, test_config_id) + test_configs.append(test_config) + test_config_ids.append(test_config_id) + + return test_configs, test_config_ids + + +# Create a global lock +csv_write_lock = threading.Lock() +def write_csv_row(filepath, row): + """ + Thread-safe write to a CSV file. + + Args: + filepath (str): Path to the CSV file. + row (dict): A dictionary representing a single CSV row. + """ + with csv_write_lock: + file_exists = False + try: + with open(filepath, 'r', newline='') as f: + file_exists = True + except FileNotFoundError: + pass + + with open(filepath, 'a', newline='') as f: + writer = csv.DictWriter(f, fieldnames=row.keys()) + if not file_exists: + writer.writeheader() + writer.writerow(row) + +def sort_csv_table(file_path): + with csv_write_lock: + try: + with open(file_path, newline='') as f: + reader = csv.DictReader(f) + rows = list(reader) + fieldnames = reader.fieldnames + + # Sort rows by all columns lexicographically (as a tuple of values) + rows.sort(key=lambda row: tuple(row[col] for col in fieldnames)) + + with open(file_path, 'w', newline='') as f: + writer = csv.DictWriter(f, fieldnames=fieldnames) + writer.writeheader() + writer.writerows(rows) + + except FileNotFoundError: + assert 0, f"No CSV table {file_path} to sort" + + +# Print the comparison in human friendly format +def print_expected_vs_output(expected, capfd): + out, err = capfd.readouterr() + output = out.split('\n')[:-1] # Need to trim last line + + with capfd.disabled(): + if err: + print(f"Exceptions encountered: {err}") # Show any exceptions + print(f"\n{'***EXPECTED***':<40}***ACTUAL***") + for e, o in zip_longest(expected, output, fillvalue = ''): + print(f"{str(e):<40}{str(o)}") + + return output + \ No newline at end of file diff --git a/requirements.txt b/tests/requirements.txt similarity index 89% rename from requirements.txt rename to tests/requirements.txt index 99e7dd7..4effb9b 100644 --- a/requirements.txt +++ b/tests/requirements.txt @@ -1,4 +1,5 @@ -# python_version 3.7.6 +# python_version 3.12.1 +# pip_version 24.* # # The parse_version_from_requirements() function in the installPipfile.groovy # file of the Jenkins Shared Library uses the python_version comment to set @@ -17,7 +18,9 @@ # pip-install this one as editable using this repository's setup.py file. The # same modules should appear in the setup.py list as given below. -flake8==3.8.3 +pytest==8.3.3 +pytest-xdist==3.6.1 +filelock==3.18.0 # Development dependencies # @@ -31,4 +34,5 @@ flake8==3.8.3 # If this repository uses the setup functionality (e.g., script entry points) # of its own setup.py file, then this list must include an entry for that # setup.py file, e.g., '-e .' or '-e ./python' (without the quotes). --e ./python + +-e git+ssh://git@github.com/xmos/test_support.git@v2.0.0#egg=test_support diff --git a/tests/spi_master_async_multi_client/CMakeLists.txt b/tests/spi_master_async_multi_client/CMakeLists.txt new file mode 100644 index 0000000..c3b4500 --- /dev/null +++ b/tests/spi_master_async_multi_client/CMakeLists.txt @@ -0,0 +1,64 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +# Get JSON lists +file(READ ${CMAKE_CURRENT_LIST_DIR}/test_params.json params_json) + +# Get individual fields from params_json +string(JSON arch_list GET ${params_json} arch) +string(JSON thread_profile_list GET ${params_json} THREAD_PROFILES) +string(JSON mosi_enabled_list GET ${params_json} MOSI_ENABLED) + +string(JSON arch_list_len LENGTH ${arch_list}) +string(JSON thread_profile_list_len LENGTH ${thread_profile_list}) +string(JSON mosi_enabled_list_len LENGTH ${mosi_enabled_list}) + + +# Subtract one off each of the lengths because RANGE includes last element +math(EXPR arch_list_len "${arch_list_len} - 1") +math(EXPR thread_profile_list_len "${thread_profile_list_len} - 1") +math(EXPR mosi_enabled_list_len "${mosi_enabled_list_len} - 1") + + +set(APP_PCA_ENABLE ON) +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) +include(${CMAKE_CURRENT_LIST_DIR}/../../examples/deps.cmake) + + +foreach(i RANGE 0 ${arch_list_len}) + string(JSON arch GET ${arch_list} ${i}) + if(arch STREQUAL "xs3") + set(target "XK-EVK-XU316") + elseif(arch STREQUAL "xs2") + set(target "XCORE-200-EXPLORER") + endif() + foreach(j RANGE 0 ${thread_profile_list_len}) + string(JSON thread_profile GET ${thread_profile_list} ${j}) + string(JSON COMBINED GET ${thread_profile} COMBINED) + string(JSON BURNT_THREADS GET ${thread_profile} BURNT_THREADS) + + foreach(l RANGE 0 ${mosi_enabled_list_len}) + string(JSON mosi_enabled GET ${mosi_enabled_list} ${l}) + + set(config ${COMBINED}_${BURNT_THREADS}_${mosi_enabled}_${arch}) + message(STATUS "building config ${config}") + + project(spi_master_async_multi_client) + set(APP_HW_TARGET ${target}) + + set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} + -DBURNT_THREADS=${BURNT_THREADS} + -DCOMBINED=${COMBINED} + -DMOSI_ENABLED=${mosi_enabled} + -O2 + -g + -Wno-reinterpret-alignment) + set(APP_INCLUDES src ../spi_master_tester_common) + + XMOS_REGISTER_APP() + + unset(APP_COMPILER_FLAGS_${config}) + unset(CONFIG_COMPILER_FLAGS) + endforeach() + endforeach() +endforeach() diff --git a/legacy_tests/spi_master_async_multi_client/config.xscope b/tests/spi_master_async_multi_client/config.xscope similarity index 100% rename from legacy_tests/spi_master_async_multi_client/config.xscope rename to tests/spi_master_async_multi_client/config.xscope diff --git a/legacy_tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc b/tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc similarity index 55% rename from legacy_tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc rename to tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc index d3c170e..e553fde 100644 --- a/legacy_tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc +++ b/tests/spi_master_async_multi_client/src/spi_master_async_multi_client.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include @@ -6,57 +6,84 @@ #include #include #include "spi.h" -#include "spi_async_tester.h" in buffered port:32 p_miso = XS1_PORT_1A; -out port p_ss[1] = {XS1_PORT_1B}; +out port p_ss = XS1_PORT_1B; out buffered port:32 p_sclk = XS1_PORT_1C; out buffered port:32 p_mosi = XS1_PORT_1D; -clock cb0 = XS1_CLKBLK_1; -clock cb1 = XS1_CLKBLK_2; +clock cb = XS1_CLKBLK_1; out port setup_strobe_port = XS1_PORT_1E; out port setup_data_port = XS1_PORT_16B; +void delay_after_print(void){ + delay_microseconds(1000); +} + void app(client interface spi_master_async_if i, int mosi_enabled, - int miso_enabled, chanend c, unsigned speed){ + int miso_enabled, streaming chanend c, unsigned speed){ set_core_fast_mode_on(); - uint32_t tx[1]; - uint32_t rx[1]; + uint32_t tx[8] = {0xed, 0xc0ffee, 0x0000000f, 0x000000f0, 0x00000f00, 0x0000f000, 0x000f0000, 0x00f00000}; + uint32_t rx[8] = {0x0}; uint32_t * movable tx_ptr = tx; uint32_t * movable rx_ptr = rx; while(1){ - i.begin_transaction(0, speed, SPI_MODE_3); - i.init_transfer_array_32(move(rx_ptr), move(tx_ptr), 1); + c <: 0; + i.begin_transaction(0, speed, SPI_MODE_0); + c <: 1; + i.init_transfer_array_32(move(rx_ptr), move(tx_ptr), sizeof(tx)/sizeof(tx[0])); + c <: 2; select { case i.transfer_complete():{ break; } } + c <: 3; i.retrieve_transfer_buffers_32(rx_ptr, tx_ptr); + + if(MOSI_ENABLED && (tx_ptr[0] != rx_ptr[0] || tx_ptr[1] != rx_ptr[1])){ + printf("Loopback didn't work!\n"); + printf("Tx: 0x%x 0x%x, Rx: 0x%x 0x%x\n", tx_ptr[0], tx_ptr[1], rx_ptr[0], rx_ptr[1]); + _Exit(1); + } else { + // printf("Loopback PASS\n"); + } + c <: 4; i.end_transaction(100); - c <: 1; + c <: 5; + + int holdoff_ticks = (10000 - speed) * 10; + delay_ticks(holdoff_ticks); //Ensure one client doesn't hog the test } } #define CLIENTS 3 [[combinable]] -void watcher(chanend c[CLIENTS]){ +void watcher(streaming chanend c[CLIENTS]){ int seen[CLIENTS] = {0}; set_core_fast_mode_on(); //TODO maybe put a timeout in here while(1){ select{ - case c[int i] :> int:{ - seen[i] = 1; + case c[int i] :> int token:{ + timer t; + int time; + t :> time; + // printf("Got %d from client: %d @ %d\n",token, i, time); + + if(token == 5){ + seen[i] = 1; + } int any_not_seen = 0; for(unsigned j=0;j #include @@ -10,16 +10,16 @@ #define NUM_SS 2 in buffered port:32 p_miso = XS1_PORT_1A; -out port p_ss[2] = {XS1_PORT_1B, XS1_PORT_1G}; +out port p_ss = XS1_PORT_4A; out buffered port:32 p_sclk = XS1_PORT_1C; out buffered port:32 p_mosi = XS1_PORT_1D; -clock cb0 = XS1_CLKBLK_1; -clock cb1 = XS1_CLKBLK_2; +clock cb = XS1_CLKBLK_1; out port setup_strobe_port = XS1_PORT_1E; out port setup_data_port = XS1_PORT_16B; -#define KBPS 50000 +#define KBPS 10000 + static int test_transfer8(client interface spi_master_async_if i, out port setup_strobe_port, out port setup_data_port, @@ -69,8 +69,6 @@ static int test_transfer8(client interface spi_master_async_if i, } if(error) printf("ERROR: master got the wrong data\n"); - if(VERBOSE) - printf("Transfer complete, error:%d\n", error); return error; } @@ -166,6 +164,8 @@ void app(client interface spi_master_async_if i, unsigned num_ss, test_transfer8 (i, setup_strobe_port, setup_data_port, 0, ifg, mode, KBPS, mosi_enabled, miso_enabled, NUMBER_OF_TEST_BYTES); + printf("Transfers complete\n"); + _Exit(0); } @@ -188,7 +188,7 @@ static void load(static const unsigned num_threads){ int main(){ interface spi_master_async_if i[1]; par { - spi_master_async(i, 1, p_sclk, MOSI, p_miso, p_ss, 2, cb0, cb1); + spi_master_async(i, 1, p_sclk, MOSI, p_miso, p_ss, 2, cb); app(i[0], NUM_SS, MOSI_ENABLED, 1); load(BURNT_THREADS); } diff --git a/tests/spi_master_async_multi_device/test_params.json b/tests/spi_master_async_multi_device/test_params.json new file mode 100644 index 0000000..af35acc --- /dev/null +++ b/tests/spi_master_async_multi_device/test_params.json @@ -0,0 +1,14 @@ +{ + "THREAD_PROFILES": [ + { + "COMBINED": 1, + "BURNT_THREADS": 4 + }, + { + "COMBINED": 0, + "BURNT_THREADS": 3 + } + ], + "MOSI_ENABLED": [0, 1], + "arch": ["xs2", "xs3"] +} diff --git a/tests/spi_master_async_rx_tx/CMakeLists.txt b/tests/spi_master_async_rx_tx/CMakeLists.txt new file mode 100644 index 0000000..e4499dc --- /dev/null +++ b/tests/spi_master_async_rx_tx/CMakeLists.txt @@ -0,0 +1,91 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +# Get JSON lists +file(READ ${CMAKE_CURRENT_LIST_DIR}/test_params.json params_json) + +# Get individual fields from params_json +string(JSON arch_list GET ${params_json} arch) +string(JSON thread_profile_list GET ${params_json} THREAD_PROFILES) +string(JSON speed_test_list GET ${params_json} SPEED_TESTS) +string(JSON transfer_width_list GET ${params_json} TRANSFER_WIDTH) +string(JSON spi_mode_list GET ${params_json} MODE) +string(JSON mosi_enabled_list GET ${params_json} MOSI_ENABLED) + +string(JSON arch_list_len LENGTH ${arch_list}) +string(JSON thread_profile_list_len LENGTH ${thread_profile_list}) +string(JSON speed_test_list_len LENGTH ${speed_test_list}) +string(JSON transfer_width_list_len LENGTH ${transfer_width_list}) +string(JSON spi_mode_list_len LENGTH ${spi_mode_list}) +string(JSON mosi_enabled_list_len LENGTH ${mosi_enabled_list}) + + +# Subtract one off each of the lengths because RANGE includes last element +math(EXPR arch_list_len "${arch_list_len} - 1") +math(EXPR thread_profile_list_len "${thread_profile_list_len} - 1") +math(EXPR speed_test_list_len "${speed_test_list_len} - 1") +math(EXPR transfer_width_list_len "${transfer_width_list_len} - 1") +math(EXPR spi_mode_list_len "${spi_mode_list_len} - 1") +math(EXPR mosi_enabled_list_len "${mosi_enabled_list_len} - 1") + + +set(APP_PCA_ENABLE ON) +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) +include(${CMAKE_CURRENT_LIST_DIR}/../../examples/deps.cmake) + + +foreach(i RANGE 0 ${arch_list_len}) + string(JSON arch GET ${arch_list} ${i}) + if(arch STREQUAL "xs3") + set(target "XK-EVK-XU316") + elseif(arch STREQUAL "xs2") + set(target "XCORE-200-EXPLORER") + endif() + foreach(j RANGE 0 ${thread_profile_list_len}) + string(JSON thread_profile GET ${thread_profile_list} ${j}) + string(JSON COMBINED GET ${thread_profile} COMBINED) + string(JSON BURNT_THREADS GET ${thread_profile} BURNT_THREADS) + + foreach(l RANGE 0 ${speed_test_list_len}) + string(JSON SPEED_TESTS GET ${speed_test_list} ${l}) + + foreach(m RANGE 0 ${mosi_enabled_list_len}) + string(JSON MOSI_ENABLED GET ${mosi_enabled_list} ${m}) + + foreach(n RANGE 0 ${transfer_width_list_len}) + string(JSON TRANSFER_WIDTH GET ${transfer_width_list} ${n}) + + foreach(o RANGE 0 ${spi_mode_list_len}) + string(JSON SPI_MODE GET ${spi_mode_list} ${o}) + + + set(config ${COMBINED}_${BURNT_THREADS}_${MOSI_ENABLED}_${SPEED_TESTS}_${TRANSFER_WIDTH}_${SPI_MODE}_${arch}) + message(STATUS "building config ${config}") + + project(spi_master_async_rx_tx) + set(APP_HW_TARGET ${target}) + + set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} + -DCOMBINED=${COMBINED} + -DBURNT_THREADS=${BURNT_THREADS} + -DMOSI_ENABLED=${MOSI_ENABLED} + -DSPEED_TESTS=${SPEED_TESTS} + -DTRANSFER_WIDTH=${TRANSFER_WIDTH} + -DSPI_MODE=${SPI_MODE} + -O2 + -g + -Wno-reinterpret-alignment) + + set(APP_INCLUDES src ../spi_master_tester_common) + + XMOS_REGISTER_APP() + message(STATUS "****${APP_COMPILER_FLAGS_${config}} ") + + unset(APP_COMPILER_FLAGS_${config}) + unset(CONFIG_COMPILER_FLAGS) + endforeach() + endforeach() + endforeach() + endforeach() + endforeach() +endforeach() diff --git a/legacy_tests/spi_master_async_rx_tx/config.xscope b/tests/spi_master_async_rx_tx/config.xscope similarity index 100% rename from legacy_tests/spi_master_async_rx_tx/config.xscope rename to tests/spi_master_async_rx_tx/config.xscope diff --git a/legacy_tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc b/tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc similarity index 68% rename from legacy_tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc rename to tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc index 64ba336..9779c3a 100644 --- a/legacy_tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc +++ b/tests/spi_master_async_rx_tx/src/spi_master_async_rx_tx.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include @@ -8,11 +8,10 @@ #include "spi_async_tester.h" in buffered port:32 p_miso = XS1_PORT_1A; -out port p_ss[1] = {XS1_PORT_1B}; +out port p_ss = XS1_PORT_1B; out buffered port:32 p_sclk = XS1_PORT_1C; out buffered port:32 p_mosi = XS1_PORT_1D; -clock cb0 = XS1_CLKBLK_1; -clock cb1 = XS1_CLKBLK_2; +clock cb = XS1_CLKBLK_1; out port setup_strobe_port = XS1_PORT_1E; out port setup_data_port = XS1_PORT_16B; @@ -22,72 +21,81 @@ typedef enum { SPI_TRANSFER_WIDTH_32 } t_transfer_width; +void delay_after_print(void){ + delay_microseconds(1000); +} + +/* This counts up to 16 bytes (steps of 4 if 32b) */ static void inc_state(unsigned &count, spi_mode_t &mode, unsigned &speed_index, t_transfer_width &transfer_width){ if(count == 16){ - count=0; - if(mode == SPI_MODE_3){ - mode = SPI_MODE_0; - if(transfer_width == SPI_TRANSFER_WIDTH_32){ - transfer_width = SPI_TRANSFER_WIDTH_8; - if(speed_index == SPEED_TESTS){ - _Exit(0); - } else { - speed_index++; - } - } else { - transfer_width++; - } - } else { - mode++; + count = 0; + if(++speed_index == SPEED_TESTS){ + printf("Transfers complete\n"); + delay_after_print(); + _Exit(0); } } else { - if(transfer_width == SPI_TRANSFER_WIDTH_8) + if(transfer_width == SPI_TRANSFER_WIDTH_8){ count++; - else { + } else { count+=4; } } - - + // printf("count: %u, speed_idx: %u (%u), mode: %d width: %d\n", count, speed_index, SPEED_TESTS, mode, transfer_width * 24 + 8); } + [[combinable]] void app(client interface spi_master_async_if spi_i, int mosi_enabled, int miso_enabled){ - unsigned speed_lut[3] = {500, 200, 2000}; + // if testing just one speed, do fastest (idx 0) + unsigned speed_lut[3] = {10000, 1000, 100}; uint8_t tx8[NUMBER_OF_TEST_BYTES]; uint8_t rx8[NUMBER_OF_TEST_BYTES]; + + for(unsigned i=0;i +#include +#include +#include +#include "spi.h" +#include "spi_async_tester.h" + +in buffered port:32 p_miso = XS1_PORT_1A; +out port p_ss = XS1_PORT_1B; +out buffered port:32 p_sclk = XS1_PORT_1C; +out buffered port:32 p_mosi = XS1_PORT_1D; +clock cb = XS1_CLKBLK_1; + +out port setup_strobe_port = XS1_PORT_1E; +out port setup_data_port = XS1_PORT_16B; + +#define SPI_MODE SPI_MODE_0 +#define TRANSFER_WIDTH 8 +#define SPI_KBPS 10000 + +typedef enum { + SPI_TRANSFER_WIDTH_8, + SPI_TRANSFER_WIDTH_32 +} t_transfer_width; + +void delay_after_print(void){ + delay_microseconds(1000); +} + +/* This counts up to 16 bytes (steps of 4 if 32b) */ +static void inc_state(unsigned &count, spi_mode_t &mode, t_transfer_width &transfer_width){ + // printf("count: %u\n", count); + if(count == 16){ + printf("Transfers complete\n"); + delay_after_print(); + _Exit(0); + } else { + if(transfer_width == SPI_TRANSFER_WIDTH_8){ + count++; + } else { + count+=4; + } + } + // printf("count: %u, mode: %d width: %d\n", count, mode, transfer_width * 24 + 8); +} + +void app(client interface spi_master_async_if spi_i){ + uint8_t tx8[NUMBER_OF_TEST_BYTES]; + uint8_t rx8[NUMBER_OF_TEST_BYTES]; + + for(unsigned i=0;i None: + self._miso_port = miso_port + self._mosi_port = mosi_port + self._sck_port = sck_port + self._ss_port = ss_port + self._ss_port_width = px.pyxsim.xsi_get_port_width(ss_port.split(':')[1] if ":" in ss_port else ss_port) # May need to trim on tile[x]: + self._setup_strobe_port = setup_strobe_port + self._setup_data_port = setup_data_port + + def get_setup_data(self, + xsi: px.pyxsim.Xsi, + setup_strobe_port: str, + setup_data_port: str) -> int: + self.wait_for_port_pins_change([setup_strobe_port]) + self.wait_for_port_pins_change([setup_strobe_port]) + return xsi.sample_port_pins(setup_data_port) + + def run(self) -> None: + xsi: px.pyxsim.Xsi = self.xsi + + print("SPI Master checker started") + + # some timing constants + xsi_tick_freq_hz = float(1e15) # pending merge of https://github.com/xmos/test_support/blob/develop/lib/python/Pyxsim/pyxsim.py#L246-L265 + millisecond_ticks = xsi_tick_freq_hz / 1e3 + microsecond_ticks = xsi_tick_freq_hz / 1e6 + nanosecond_ticks = xsi_tick_freq_hz / 1e9 + + sck_value = xsi.sample_port_pins(self._sck_port) + ss_value = xsi.sample_port_pins(self._ss_port) + ss_deaserted_value = (0xffffffff >> (32 - self._ss_port_width)) + + while True: + #first do the setup rx from DUT + strobe_val = xsi.sample_port_pins(self._setup_strobe_port) + if strobe_val == 1: + self.wait_for_port_pins_change([self._setup_strobe_port]) + + expected_cpol = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_cpha = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_frequency_in_khz = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_mosi_enabled = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_miso_enabled = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_device_id = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_interframe_space = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_num_bytes = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + # print(f"Got Settings cpol:{expected_cpol} cpha:{expected_cpha} mosi:{expected_miso_enabled} miso:{expected_miso_enabled} expected_frequency_in_khz:{expected_frequency_in_khz} expected_device_id:{expected_device_id} expected_interframe_space:{expected_interframe_space} expected_num_bytes:{expected_num_bytes}") + + clock_half_period = millisecond_ticks / (expected_frequency_in_khz*2) + + all_ss_deserted = True + if (xsi.sample_port_pins(self._ss_port) != ss_deaserted_value): + all_ss_deserted = False + + # Wait until all SS go high + while not all_ss_deserted: + self.wait_for_port_pins_change([self._ss_port]) + all_ss_deserted = True if xsi.sample_port_pins(self._ss_port) == ss_deaserted_value else False + # print("ALL HIGH", ss_deaserted_value) + + error = False + + # Wait for any SS to assert + active_slave = -1 # no active slaves + while(active_slave == -1): + self.wait_for_port_pins_change([self._ss_port]) + ss_port_val = xsi.sample_port_pins(self._ss_port) + for i in range(self._ss_port_width): + if ((ss_port_val >> i) & 1) == 0: + assert active_slave == -1, f"more than one SS asserted, SS port val: 0x{ss_port_val:x}" + active_slave = i + # print(f"active_slave: {active_slave}") + + last_clock_event_time = xsi.get_time() + + rx_bit_counter = 0 + tx_bit_counter = 0 + tx_data = [0xfe, 0xf7, 0xfb, 0xef, 0xdf, 0xbf, 0xfd, 0x7f, 0x01, 0x08, 0x04, 0x10, 0x20, 0x04, 0x02, 0x80] + rx_data = [0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x04, 0x80, 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f] + rx_byte = 0 + tx_byte = tx_data[0] + # check the polarity + + sampled_cpol = xsi.sample_port_pins(self._sck_port) + if sampled_cpol != expected_cpol: + print(f"ERROR: unexpected clock polarity {sampled_cpol} (expected {expected_cpol}) at the slave select point, time: {xsi.get_time() / nanosecond_ticks}ns") + error = True + clock_edge_number = 0 + + #probably not physically possible but good for testing + if expected_cpha == 0: + xsi.drive_port_pins(self._miso_port, (tx_byte>>7)&1) + tx_bit_counter += 1 + tx_byte = tx_byte << 1 + + ss_value = ((xsi.sample_port_pins(self._ss_port) >> active_slave) & 1) # Select of interest + sck_value = xsi.sample_port_pins(self._sck_port) + + while ss_value == 0: + self.wait_for_port_pins_change([self._ss_port] + [self._sck_port]) + + # check no other SS asserted + ss_port_val = xsi.sample_port_pins(self._ss_port) & ss_deaserted_value + # print(f"{self._ss_port}, 0x{ss_port_val:x}, 0x{ss_deaserted_value:x}, {active_slave}, {(ss_deaserted_value & ~(1 << active_slave)):x}") + for i in range(self._ss_port_width): + if (ss_port_val & (1 << i) == 0) and (i != active_slave): + error = True + print(f"Error: Additional slave selected during first transaction, SS port val:0x{ss_port_val:x} (active slave:{active_slave} mask 0x{ss_deaserted_value:x}) at time: {xsi.get_time() / nanosecond_ticks}ns") + + if (ss_value == ((xsi.sample_port_pins(self._ss_port) >> active_slave) & 1) and (sck_value == xsi.sample_port_pins(self._sck_port))): + continue + + ss_value = ((xsi.sample_port_pins(self._ss_port) >> active_slave) & 1) + sck_value = xsi.sample_port_pins(self._sck_port) + + if ss_value == 0: + clock_event_time = xsi.get_time() + measured_time_elapsed = clock_event_time - last_clock_event_time + if clock_edge_number > 1 and (measured_time_elapsed*1.05) < clock_half_period : + print(f"ERROR: Clock half period less than allowed for given SCLK frequency, measured_time_elapsed: {measured_time_elapsed/nanosecond_ticks:.2f}ns clock_half_period:{clock_half_period/nanosecond_ticks}ns, at time: {xsi.get_time() / nanosecond_ticks}ns") + error = True + last_clock_event_time = clock_event_time + + #check that the clock edges never go faster than the expected clock rate + if ss_value == 0: + clock_edge_number += 1 + # print(f"MISO clock_edge_number: {clock_edge_number}") + #the the clock must have transitioned + if sck_value == (expected_cpha ^ expected_cpol): + if expected_miso_enabled == 1: + #drive data out + xsi.drive_port_pins(self._miso_port, (tx_byte>>7)&1) + tx_bit_counter += 1 + tx_byte = tx_byte << 1 + if (tx_bit_counter%8) == 0: + index = tx_bit_counter//8 + if index < 16: + tx_byte = tx_data[index] + else: + tx_byte = 0 + else: + #clock data in + if expected_mosi_enabled == 1: + rx_byte = rx_byte << 1 + rx_byte += xsi.sample_port_pins(self._mosi_port) + rx_bit_counter = rx_bit_counter + 1 + if((rx_bit_counter%8) == 0): + expected_rx_byte = rx_data[(rx_bit_counter//8) - 1] + #print "slave got {seen} and expected {expect}".format(seen=rx_byte, expect=expected_rx_byte) + if expected_rx_byte != rx_byte: + print(f"ERROR: slave received incorrect data Got:{rx_byte:02x} Expected:{expected_rx_byte:02x} at time: {xsi.get_time() / nanosecond_ticks}ns") + error = True + # print(f"Checker correctly got byte: {rx_byte:02x} at time {xsi.get_time() / nanosecond_ticks}ns") + rx_byte = 0 + else: + if clock_edge_number != expected_num_bytes*2*8: + error = True + print(f"ERROR: incorrect number of clock edges at slave {clock_edge_number}/{expected_num_bytes*2*8} at time: {xsi.get_time() / nanosecond_ticks}ns") + if error: + print(f"Fail: CPOL:{expected_cpol} CPHA:{expected_cpha} KHz:{expected_frequency_in_khz} MOSI Enabled:{expected_mosi_enabled} MISO Enabled:{expected_miso_enabled}") diff --git a/tests/spi_master_sync_benchmark/CMakeLists.txt b/tests/spi_master_sync_benchmark/CMakeLists.txt new file mode 100644 index 0000000..bb400a0 --- /dev/null +++ b/tests/spi_master_sync_benchmark/CMakeLists.txt @@ -0,0 +1,93 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +# Get JSON lists +file(READ ${CMAKE_CURRENT_LIST_DIR}/test_params.json params_json) + +# Get individual fields from params_json +string(JSON arch_list GET ${params_json} arch) +string(JSON burnt_threads_list GET ${params_json} BURNT_THREADS) +string(JSON spi_mode_list GET ${params_json} SPI_MODE) +string(JSON miso_mosi_enabled_list GET ${params_json} MISO_MOSI_ENABLED) +string(JSON cb_enabled_list GET ${params_json} CB_ENABLED) + +string(JSON arch_list_len LENGTH ${arch_list}) +string(JSON burnt_threads_list_len LENGTH ${burnt_threads_list}) +string(JSON spi_mode_list_len LENGTH ${spi_mode_list}) +string(JSON miso_mosi_enabled_list_len LENGTH ${miso_mosi_enabled_list}) +string(JSON cb_enabled_list_len LENGTH ${cb_enabled_list}) + + +# Subtract one off each of the lengths because RANGE includes last element +math(EXPR arch_list_len "${arch_list_len} - 1") +math(EXPR burnt_threads_list_len "${burnt_threads_list_len} - 1") +math(EXPR spi_mode_list_len "${spi_mode_list_len} - 1") +math(EXPR miso_mosi_enabled_list_len "${miso_mosi_enabled_list_len} - 1") +math(EXPR cb_enabled_list_len "${cb_enabled_list_len} - 1") + + +set(APP_PCA_ENABLE ON) +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) +include(${CMAKE_CURRENT_LIST_DIR}/../../examples/deps.cmake) + + +foreach(i RANGE 0 ${arch_list_len}) + string(JSON arch GET ${arch_list} ${i}) + if(arch STREQUAL "xs3") + set(target "XK-EVK-XU316") + elseif(arch STREQUAL "xs2") + set(target "XCORE-200-EXPLORER") + endif() + foreach(j RANGE 0 ${burnt_threads_list_len}) + string(JSON burnt_threads GET ${burnt_threads_list} ${j}) + + foreach(k RANGE 0 ${spi_mode_list_len}) + string(JSON SPI_MODE GET ${spi_mode_list} ${k}) + + foreach(l RANGE 0 ${miso_mosi_enabled_list_len}) + string(JSON miso_mosi_enabled GET ${miso_mosi_enabled_list} ${l}) + + foreach(m RANGE 0 ${cb_enabled_list_len}) + string(JSON cb_enabled GET ${cb_enabled_list} ${m}) + + set(config ${burnt_threads}_${SPI_MODE}_${miso_mosi_enabled}_${cb_enabled}_${arch}) + message(STATUS "building config ${config}") + + project(spi_master_sync_benchmark) + set(APP_HW_TARGET ${target}) + + string(FIND "${config}" "mosi" pos) + if(NOT pos EQUAL -1) + list(APPEND CONFIG_COMPILER_FLAGS "-DMOSI_ENABLED=1") + else() + list(APPEND CONFIG_COMPILER_FLAGS "-DMOSI_ENABLED=0") + endif() + + string(FIND "${config}" "miso" pos) + if(NOT pos EQUAL -1) + list(APPEND CONFIG_COMPILER_FLAGS "-DMISO_ENABLED=1") + else() + list(APPEND CONFIG_COMPILER_FLAGS "-DMISO_ENABLED=0") + endif() + + set(APP_INCLUDES src ../spi_master_tester_common) + + set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} + -DBURNT_THREADS=${burnt_threads} + -DSPI_MODE=${SPI_MODE} + -DCB_ENABLED=${cb_enabled} + -O2 + -g + -Wno-reinterpret-alignment) + + + XMOS_REGISTER_APP() + message(STATUS "****${APP_COMPILER_FLAGS_${config}} ") + + unset(APP_COMPILER_FLAGS_${config}) + unset(CONFIG_COMPILER_FLAGS) + endforeach() + endforeach() + endforeach() + endforeach() +endforeach() diff --git a/legacy_tests/spi_master_async_shutdown/config.xscope b/tests/spi_master_sync_benchmark/config.xscope similarity index 100% rename from legacy_tests/spi_master_async_shutdown/config.xscope rename to tests/spi_master_sync_benchmark/config.xscope diff --git a/tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc b/tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc new file mode 100644 index 0000000..560472b --- /dev/null +++ b/tests/spi_master_sync_benchmark/src/spi_master_sync_benchmark.xc @@ -0,0 +1,135 @@ +// Copyright 2015-2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. +#include +#include +#include +#include +#include "spi.h" +#include "spi_sync_tester.h" +extern "C"{ + #include "../src/spi_fwk.h" +} + +// access internal functions +extern void spi_master_determine_clock_settings(spi_master_source_clock_t *source_clock, unsigned *divider, unsigned speed_in_khz); +extern unsigned spi_master_get_actual_clock_rate(spi_master_source_clock_t source_clock, unsigned divider); + + + +in buffered port:32 p_miso = XS1_PORT_1A; +out port p_ss = XS1_PORT_1B; +out buffered port:32 p_sclk = XS1_PORT_1C; +out buffered port:32 p_mosi = XS1_PORT_1D; +clock cb = XS1_CLKBLK_1; + +out port setup_strobe_port = XS1_PORT_1E; +out port setup_data_port = XS1_PORT_16B; + +#if CB_ENABLED + #define MAX_TEST_SPEED 150000 + #define MIN_TEST_SPEED 10000 +#else + #if BURNT_THREADS > 3 + #define MAX_TEST_SPEED 3000 + #else + #define MAX_TEST_SPEED 4000 // Above this speed SPI synch tends to fail badly so limit upper + #endif + #define MIN_TEST_SPEED 1000 +#endif + +static unsigned get_max_speed(unsigned transfer_width, client interface spi_master_if i){ + unsigned min_test_speed = MIN_TEST_SPEED, max_test_speed = MAX_TEST_SPEED;//kbps + unsigned iteration = 0; + unsigned test_speed = min_test_speed; + while(1){ + // Make sure we set the actual speed attainable +#if CB_ENABLED + spi_master_source_clock_t source_clock; + unsigned divider; + spi_master_determine_clock_settings(&source_clock, ÷r, test_speed); + unsigned actual_test_speed = spi_master_get_actual_clock_rate(source_clock, divider); + + // Improve MISO timing + if(MISO_ENABLED){ + spi_master_miso_capture_timing_t miso_capture_timing = {0}; + if(actual_test_speed > 50000){ + miso_capture_timing.miso_sample_delay = (actual_test_speed - 50000) / 18000; + printf("MISO delay setting: %d\n", miso_capture_timing.miso_sample_delay); + } else { + miso_capture_timing.miso_sample_delay = spi_master_sample_delay_1_2; + } + miso_capture_timing.miso_pad_delay = 0; + i.set_miso_capture_timing(0, miso_capture_timing); + } +#else + unsigned clkblkless_period_ticks = (XS1_TIMER_KHZ + test_speed - 1) / test_speed; + unsigned actual_test_speed = XS1_TIMER_KHZ / clkblkless_period_ticks; +#endif + + printf("testing:%u:%u:", transfer_width, actual_test_speed); + int error = 0; + if(transfer_width == 8){ + error = test_transfer8(i, setup_strobe_port, setup_data_port, 0, 100, + SPI_MODE, actual_test_speed, MOSI_ENABLED, MISO_ENABLED); + } else { + error = test_transfer32(i, setup_strobe_port, setup_data_port, 0, 100, + SPI_MODE, actual_test_speed, MOSI_ENABLED, MISO_ENABLED); + } + + + + if(error){ + printf("FAIL\n"); + test_speed = (test_speed + min_test_speed) / 2; + + } else { + printf("PASS\n"); + test_speed = (test_speed + max_test_speed) / 2; + } + if(iteration++ == 5) return 0; // This always gets us there + } + return 0; +} + +void app(client interface spi_master_if i, int mosi_enabled, int miso_enabled){ + printf("%d\n", get_max_speed(8, i)); + printf("%d\n", get_max_speed(32, i)); + _Exit(1); +} + +static void load(static const unsigned num_threads){ + switch(num_threads){ + case 3: par {par(int i=0;i<3;i++) while(1);}break; + case 4: par {par(int i=0;i<4;i++) while(1);}break; + case 5: par {par(int i=0;i<5;i++) while(1);}break; + case 6: par {par(int i=0;i<6;i++) while(1);}break; + case 7: par {par(int i=0;i<7;i++) while(1);}break; + } +} +#if MOSI_ENABLED +#define MOSI p_mosi +#else +#define MOSI null +#endif + +#if MISO_ENABLED +#define MISO p_miso +#else +#define MISO null +#endif + +#if CB_ENABLED +#define CB cb +#else +#define CB null +#endif + +int main(){ + interface spi_master_if i[1]; + par { + spi_master(i, 1, p_sclk, MOSI, MISO, p_ss, 1, CB); + app(i[0], MOSI_ENABLED, MISO_ENABLED); + load(BURNT_THREADS); + } + return 0; +} diff --git a/tests/spi_master_sync_benchmark/test_params.json b/tests/spi_master_sync_benchmark/test_params.json new file mode 100644 index 0000000..5e8cb1e --- /dev/null +++ b/tests/spi_master_sync_benchmark/test_params.json @@ -0,0 +1,7 @@ +{ + "BURNT_THREADS": [3, 7], + "SPI_MODE": [0, 1, 2, 3], + "MISO_MOSI_ENABLED": ["miso", "mosi", "miso_and_mosi"], + "CB_ENABLED": [1, 0], + "arch": ["xs2", "xs3"] +} diff --git a/tests/spi_master_sync_clock_port_sharing/CMakeLists.txt b/tests/spi_master_sync_clock_port_sharing/CMakeLists.txt new file mode 100644 index 0000000..898c8b7 --- /dev/null +++ b/tests/spi_master_sync_clock_port_sharing/CMakeLists.txt @@ -0,0 +1,26 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +set(APP_PCA_ENABLE ON) +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) +include(${CMAKE_CURRENT_LIST_DIR}/../../examples/deps.cmake) + +project(spi_master_sync_clock_port_sharing) +set(target "XK-EVK-XU316") +set(APP_HW_TARGET ${target}) + +set(COMPILER_FLAGS_COMMON -O2 + -g + -Wno-reinterpret-alignment) + + +set(APP_COMPILER_FLAGS_COMBINED ${COMPILER_FLAGS_COMMON} + -DCOMBINED=1) + +set(APP_COMPILER_FLAGS_NOT_COMBINED ${COMPILER_FLAGS_COMMON} + -DCOMBINED=0) + + +set(APP_INCLUDES src ../spi_master_tester_common) + +XMOS_REGISTER_APP() diff --git a/legacy_tests/spi_master_sync_benchmark/config.xscope b/tests/spi_master_sync_clock_port_sharing/config.xscope similarity index 100% rename from legacy_tests/spi_master_sync_benchmark/config.xscope rename to tests/spi_master_sync_clock_port_sharing/config.xscope diff --git a/legacy_tests/spi_master_sync_clock_port_sharing/spi_master_sync_clock_port_sharing.xc b/tests/spi_master_sync_clock_port_sharing/src/spi_master_sync_clock_port_sharing.xc similarity index 86% rename from legacy_tests/spi_master_sync_clock_port_sharing/spi_master_sync_clock_port_sharing.xc rename to tests/spi_master_sync_clock_port_sharing/src/spi_master_sync_clock_port_sharing.xc index 2e05a57..e541e52 100644 --- a/legacy_tests/spi_master_sync_clock_port_sharing/spi_master_sync_clock_port_sharing.xc +++ b/tests/spi_master_sync_clock_port_sharing/src/spi_master_sync_clock_port_sharing.xc @@ -1,4 +1,4 @@ -// Copyright 2020-2021 XMOS LIMITED. +// Copyright 2020-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include @@ -9,7 +9,7 @@ #include "spi_sync_tester.h" in buffered port:32 p_miso = XS1_PORT_1A; -out port p_ss[1] = {XS1_PORT_1B}; +out port p_ss = XS1_PORT_1B; out buffered port:32 p_sclk = XS1_PORT_1C; out buffered port:32 p_mosi = XS1_PORT_1D; clock cb = XS1_CLKBLK_1; @@ -23,6 +23,8 @@ void app(client interface spi_master_if spi_i, int mosi_enabled, int miso_enable timer always; int start; always :> start; + start += 1000; // wait 10us to start + while (1) { select { @@ -46,8 +48,11 @@ void app(client interface spi_master_if spi_i, int mosi_enabled, int miso_enable } count++; - if (count == 8) + if (count == 8){ + printf("Transfers complete\n"); + delay_microseconds(100); // Flush _Exit(0); + } break; } @@ -60,6 +65,8 @@ void timebomb(){ tmr :> t; tmr when timerafter(t + 10000000) :> void; printf("Timeout!\n"); + delay_milliseconds(1); + printf("\n"); _Exit(1); } diff --git a/tests/spi_master_sync_multi_client/CMakeLists.txt b/tests/spi_master_sync_multi_client/CMakeLists.txt new file mode 100644 index 0000000..6a7e33f --- /dev/null +++ b/tests/spi_master_sync_multi_client/CMakeLists.txt @@ -0,0 +1,82 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +# Get JSON lists +file(READ ${CMAKE_CURRENT_LIST_DIR}/test_params.json params_json) + +# Get individual fields from params_json +string(JSON arch_list GET ${params_json} arch) +string(JSON burnt_threads_list GET ${params_json} BURNT_THREADS) +string(JSON cb_enabled_list GET ${params_json} CB_ENABLED) +string(JSON miso_mosi_enabled_list GET ${params_json} MISO_MOSI_ENABLED) + +string(JSON arch_list_len LENGTH ${arch_list}) +string(JSON burnt_threads_list_len LENGTH ${burnt_threads_list}) +string(JSON cb_enabled_list_len LENGTH ${cb_enabled_list}) +string(JSON miso_mosi_enabled_list_len LENGTH ${miso_mosi_enabled_list}) + + +# Subtract one off each of the lengths because RANGE includes last element +math(EXPR arch_list_len "${arch_list_len} - 1") +math(EXPR burnt_threads_list_len "${burnt_threads_list_len} - 1") +math(EXPR cb_enabled_list_len "${cb_enabled_list_len} - 1") +math(EXPR miso_mosi_enabled_list_len "${miso_mosi_enabled_list_len} - 1") + + +set(APP_PCA_ENABLE ON) +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) +include(${CMAKE_CURRENT_LIST_DIR}/../../examples/deps.cmake) + + +foreach(i RANGE 0 ${arch_list_len}) + string(JSON arch GET ${arch_list} ${i}) + if(arch STREQUAL "xs3") + set(target "XK-EVK-XU316") + elseif(arch STREQUAL "xs2") + set(target "XCORE-200-EXPLORER") + endif() + foreach(j RANGE 0 ${burnt_threads_list_len}) + string(JSON burnt_threads GET ${burnt_threads_list} ${j}) + + foreach(k RANGE 0 ${cb_enabled_list_len}) + string(JSON cb_enabled GET ${cb_enabled_list} ${k}) + + foreach(l RANGE 0 ${miso_mosi_enabled_list_len}) + string(JSON miso_mosi_enabled GET ${miso_mosi_enabled_list} ${l}) + + set(config ${burnt_threads}_${cb_enabled}_${miso_mosi_enabled}_${arch}) + message(STATUS "building config ${config}") + + project(spi_master_sync_multi_client) + set(APP_HW_TARGET ${target}) + + string(FIND "${config}" "mosi" pos) + if(NOT pos EQUAL -1) + list(APPEND CONFIG_COMPILER_FLAGS "-DMOSI_ENABLED=1") + else() + list(APPEND CONFIG_COMPILER_FLAGS "-DMOSI_ENABLED=0") + endif() + + string(FIND "${config}" "miso" pos) + if(NOT pos EQUAL -1) + list(APPEND CONFIG_COMPILER_FLAGS "-DMISO_ENABLED=1") + else() + list(APPEND CONFIG_COMPILER_FLAGS "-DMISO_ENABLED=0") + endif() + + set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} + -DBURNT_THREADS=${burnt_threads} + -DCB_ENABLED=${cb_enabled} + -O2 + -g + -Wno-reinterpret-alignment) + set(APP_INCLUDES src ../spi_master_tester_common) + + XMOS_REGISTER_APP() + + unset(APP_COMPILER_FLAGS_${config}) + unset(CONFIG_COMPILER_FLAGS) + endforeach() + endforeach() + endforeach() +endforeach() diff --git a/legacy_tests/spi_master_sync_clock_port_sharing/config.xscope b/tests/spi_master_sync_multi_client/config.xscope similarity index 100% rename from legacy_tests/spi_master_sync_clock_port_sharing/config.xscope rename to tests/spi_master_sync_multi_client/config.xscope diff --git a/legacy_tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc b/tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc similarity index 84% rename from legacy_tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc rename to tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc index 04e71a1..7416584 100644 --- a/legacy_tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc +++ b/tests/spi_master_sync_multi_client/src/spi_master_sync_multi_client.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include @@ -9,20 +9,23 @@ #include "spi_sync_tester.h" in buffered port:32 p_miso = XS1_PORT_1A; -out port p_ss[1] = {XS1_PORT_1B}; +out port p_ss = XS1_PORT_1B; out buffered port:32 p_sclk = XS1_PORT_1C; out buffered port:32 p_mosi = XS1_PORT_1D; clock cb = XS1_CLKBLK_1; +#define SPEED_KBPS 10000 + out port setup_strobe_port = XS1_PORT_1E; out port setup_data_port = XS1_PORT_16B; void app(client interface spi_master_if i, int mosi_enabled, int miso_enabled, chanend c){ set_core_fast_mode_on(); while(1){ - i.begin_transaction(0, 736, SPI_MODE_3); + i.begin_transaction(0, SPEED_KBPS, SPI_MODE_3); i.transfer8(0xff); i.end_transaction(100); + delay_microseconds(10); // Allow other clients to access SPI and avoid hogging by one c <: 1; } } @@ -40,6 +43,7 @@ void watcher(chanend c[CLIENTS]){ any_not_seen |= (seen[j] == 0); if(!any_not_seen){ + printf("Transfers complete\n"); _Exit(0); } break; @@ -71,11 +75,6 @@ static void load(static const unsigned num_threads){ #define MISO null #endif -#if CB_ENABLED -#define CB cb -#else -#define CB null -#endif /* * Tests: * - no client is ever starved @@ -85,7 +84,7 @@ int main(){ chan c[3]; interface spi_master_if i[3]; par { - spi_master(i, 3, p_sclk, MOSI, MISO, p_ss, 1, CB); + spi_master(i, 3, p_sclk, MOSI, MISO, p_ss, 1, cb); app(i[0], MOSI_ENABLED, MISO_ENABLED, c[0]); app(i[1], MOSI_ENABLED, MISO_ENABLED, c[1]); app(i[2], MOSI_ENABLED, MISO_ENABLED, c[2]); diff --git a/tests/spi_master_sync_multi_client/test_params.json b/tests/spi_master_sync_multi_client/test_params.json new file mode 100644 index 0000000..79f1f9b --- /dev/null +++ b/tests/spi_master_sync_multi_client/test_params.json @@ -0,0 +1,6 @@ +{ + "BURNT_THREADS": [3, 4], + "CB_ENABLED": [1], + "MISO_MOSI_ENABLED": ["miso", "mosi", "miso_and_mosi"], + "arch": ["xs2", "xs3"] +} diff --git a/tests/spi_master_sync_multi_device/CMakeLists.txt b/tests/spi_master_sync_multi_device/CMakeLists.txt new file mode 100644 index 0000000..0b21045 --- /dev/null +++ b/tests/spi_master_sync_multi_device/CMakeLists.txt @@ -0,0 +1,82 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +# Get JSON lists +file(READ ${CMAKE_CURRENT_LIST_DIR}/test_params.json params_json) + +# Get individual fields from params_json +string(JSON arch_list GET ${params_json} arch) +string(JSON burnt_threads_list GET ${params_json} BURNT_THREADS) +string(JSON cb_enabled_list GET ${params_json} CB_ENABLED) +string(JSON miso_mosi_enabled_list GET ${params_json} MISO_MOSI_ENABLED) + +string(JSON arch_list_len LENGTH ${arch_list}) +string(JSON burnt_threads_list_len LENGTH ${burnt_threads_list}) +string(JSON cb_enabled_list_len LENGTH ${cb_enabled_list}) +string(JSON miso_mosi_enabled_list_len LENGTH ${miso_mosi_enabled_list}) + + +# Subtract one off each of the lengths because RANGE includes last element +math(EXPR arch_list_len "${arch_list_len} - 1") +math(EXPR burnt_threads_list_len "${burnt_threads_list_len} - 1") +math(EXPR cb_enabled_list_len "${cb_enabled_list_len} - 1") +math(EXPR miso_mosi_enabled_list_len "${miso_mosi_enabled_list_len} - 1") + + +set(APP_PCA_ENABLE ON) +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) +include(${CMAKE_CURRENT_LIST_DIR}/../../examples/deps.cmake) + + +foreach(i RANGE 0 ${arch_list_len}) + string(JSON arch GET ${arch_list} ${i}) + if(arch STREQUAL "xs3") + set(target "XK-EVK-XU316") + elseif(arch STREQUAL "xs2") + set(target "XCORE-200-EXPLORER") + endif() + foreach(j RANGE 0 ${burnt_threads_list_len}) + string(JSON burnt_threads GET ${burnt_threads_list} ${j}) + + foreach(k RANGE 0 ${cb_enabled_list_len}) + string(JSON cb_enabled GET ${cb_enabled_list} ${k}) + + foreach(l RANGE 0 ${miso_mosi_enabled_list_len}) + string(JSON miso_mosi_enabled GET ${miso_mosi_enabled_list} ${l}) + + set(config ${burnt_threads}_${cb_enabled}_${miso_mosi_enabled}_${arch}) + message(STATUS "building config ${config}") + + project(spi_master_sync_multi_device) + set(APP_HW_TARGET ${target}) + + string(FIND "${config}" "mosi" pos) + if(NOT pos EQUAL -1) + list(APPEND CONFIG_COMPILER_FLAGS "-DMOSI_ENABLED=1") + else() + list(APPEND CONFIG_COMPILER_FLAGS "-DMOSI_ENABLED=0") + endif() + + string(FIND "${config}" "miso" pos) + if(NOT pos EQUAL -1) + list(APPEND CONFIG_COMPILER_FLAGS "-DMISO_ENABLED=1") + else() + list(APPEND CONFIG_COMPILER_FLAGS "-DMISO_ENABLED=0") + endif() + + set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} + -DBURNT_THREADS=${burnt_threads} + -DCB_ENABLED=${cb_enabled} + -O2 + -g + -Wno-reinterpret-alignment) + set(APP_INCLUDES src ../spi_master_tester_common) + + XMOS_REGISTER_APP() + + unset(APP_COMPILER_FLAGS_${config}) + unset(CONFIG_COMPILER_FLAGS) + endforeach() + endforeach() + endforeach() +endforeach() diff --git a/legacy_tests/spi_master_sync_multi_client/config.xscope b/tests/spi_master_sync_multi_device/config.xscope similarity index 100% rename from legacy_tests/spi_master_sync_multi_client/config.xscope rename to tests/spi_master_sync_multi_device/config.xscope diff --git a/legacy_tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc b/tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc similarity index 91% rename from legacy_tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc rename to tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc index f0e5459..c8fcdf9 100644 --- a/legacy_tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc +++ b/tests/spi_master_sync_multi_device/src/spi_master_sync_multi_device.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include @@ -10,7 +10,7 @@ #define NUM_SS 2 in buffered port:32 p_miso = XS1_PORT_1A; -out port p_ss[2] = {XS1_PORT_1B, XS1_PORT_1G}; +out port p_ss = XS1_PORT_4A; out buffered port:32 p_sclk = XS1_PORT_1C; out buffered port:32 p_mosi = XS1_PORT_1D; clock cb = XS1_CLKBLK_1; @@ -47,6 +47,7 @@ void app(client interface spi_master_if i, unsigned num_ss, test_transfer8 (i, setup_strobe_port, setup_data_port, 1, ifg, mode, KBPS, mosi_enabled, miso_enabled); + printf("Transfers complete\n"); _Exit(0); } @@ -72,16 +73,10 @@ static void load(static const unsigned num_threads){ #define MISO null #endif -#if CB_ENABLED -#define CB cb -#else -#define CB null -#endif - int main(){ interface spi_master_if i[1]; par { - spi_master(i, 1, p_sclk, MOSI, MISO, p_ss, NUM_SS, CB); + spi_master(i, 1, p_sclk, MOSI, MISO, p_ss, NUM_SS, cb); app(i[0], NUM_SS, MOSI_ENABLED, MISO_ENABLED); load(BURNT_THREADS); } diff --git a/tests/spi_master_sync_multi_device/test_params.json b/tests/spi_master_sync_multi_device/test_params.json new file mode 100644 index 0000000..3f57237 --- /dev/null +++ b/tests/spi_master_sync_multi_device/test_params.json @@ -0,0 +1,6 @@ +{ + "BURNT_THREADS": [3, 7], + "CB_ENABLED": [1, 0], + "MISO_MOSI_ENABLED": ["miso", "mosi", "miso_and_mosi"], + "arch": ["xs2", "xs3"] +} diff --git a/tests/spi_master_sync_rx_tx/CMakeLists.txt b/tests/spi_master_sync_rx_tx/CMakeLists.txt new file mode 100644 index 0000000..a71c61f --- /dev/null +++ b/tests/spi_master_sync_rx_tx/CMakeLists.txt @@ -0,0 +1,90 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +# Get JSON lists +file(READ ${CMAKE_CURRENT_LIST_DIR}/test_params.json params_json) + +# Get individual fields from params_json +string(JSON arch_list GET ${params_json} arch) +string(JSON burnt_threads_list GET ${params_json} BURNT_THREADS) +string(JSON spi_mode_list GET ${params_json} SPI_MODE) +string(JSON miso_mosi_enabled_list GET ${params_json} MISO_MOSI_ENABLED) +string(JSON cb_enabled_list GET ${params_json} CB_ENABLED) + +string(JSON arch_list_len LENGTH ${arch_list}) +string(JSON burnt_threads_list_len LENGTH ${burnt_threads_list}) +string(JSON spi_mode_list_len LENGTH ${spi_mode_list}) +string(JSON miso_mosi_enabled_list_len LENGTH ${miso_mosi_enabled_list}) +string(JSON cb_enabled_list_len LENGTH ${cb_enabled_list}) + + +# Subtract one off each of the lengths because RANGE includes last element +math(EXPR arch_list_len "${arch_list_len} - 1") +math(EXPR burnt_threads_list_len "${burnt_threads_list_len} - 1") +math(EXPR spi_mode_list_len "${spi_mode_list_len} - 1") +math(EXPR miso_mosi_enabled_list_len "${miso_mosi_enabled_list_len} - 1") +math(EXPR cb_enabled_list_len "${cb_enabled_list_len} - 1") + + +set(APP_PCA_ENABLE ON) +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) +include(${CMAKE_CURRENT_LIST_DIR}/../../examples/deps.cmake) + + +foreach(i RANGE 0 ${arch_list_len}) + string(JSON arch GET ${arch_list} ${i}) + if(arch STREQUAL "xs3") + set(target "XK-EVK-XU316") + elseif(arch STREQUAL "xs2") + set(target "XCORE-200-EXPLORER") + endif() + foreach(j RANGE 0 ${burnt_threads_list_len}) + string(JSON burnt_threads GET ${burnt_threads_list} ${j}) + + foreach(k RANGE 0 ${spi_mode_list_len}) + string(JSON spi_mode GET ${spi_mode_list} ${k}) + + foreach(l RANGE 0 ${miso_mosi_enabled_list_len}) + string(JSON miso_mosi_enabled GET ${miso_mosi_enabled_list} ${l}) + + foreach(m RANGE 0 ${cb_enabled_list_len}) + string(JSON cb_enabled GET ${cb_enabled_list} ${m}) + + set(config ${burnt_threads}_${miso_mosi_enabled}_${spi_mode}_${cb_enabled}_${arch}) + message(STATUS "building config ${config}") + + project(spi_master_sync_rx_tx) + set(APP_HW_TARGET ${target}) + + string(FIND "${config}" "mosi" pos) + if(NOT pos EQUAL -1) + list(APPEND CONFIG_COMPILER_FLAGS "-DMOSI_ENABLED=1") + else() + list(APPEND CONFIG_COMPILER_FLAGS "-DMOSI_ENABLED=0") + endif() + + string(FIND "${config}" "miso" pos) + if(NOT pos EQUAL -1) + list(APPEND CONFIG_COMPILER_FLAGS "-DMISO_ENABLED=1") + else() + list(APPEND CONFIG_COMPILER_FLAGS "-DMISO_ENABLED=0") + endif() + + set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} + -DBURNT_THREADS=${burnt_threads} + -DSPI_MODE=${spi_mode} + -DCB_ENABLED=${cb_enabled} + -O2 + -g + -Wno-reinterpret-alignment) + set(APP_INCLUDES src ../spi_master_tester_common) + + XMOS_REGISTER_APP() + + unset(APP_COMPILER_FLAGS_${config}) + unset(CONFIG_COMPILER_FLAGS) + endforeach() + endforeach() + endforeach() + endforeach() +endforeach() diff --git a/legacy_tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc b/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc similarity index 52% rename from legacy_tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc rename to tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc index 4b02070..710df2a 100644 --- a/legacy_tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc +++ b/tests/spi_master_sync_rx_tx/src/spi_master_sync_rx_tx.xc @@ -1,4 +1,4 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include @@ -8,7 +8,7 @@ #include "spi_sync_tester.h" in buffered port:32 p_miso = XS1_PORT_1A; -out port p_ss[1] = {XS1_PORT_1B}; +out port p_ss = XS1_PORT_1B; out buffered port:32 p_sclk = XS1_PORT_1C; out buffered port:32 p_mosi = XS1_PORT_1D; clock cb = XS1_CLKBLK_1; @@ -16,24 +16,35 @@ clock cb = XS1_CLKBLK_1; out port setup_strobe_port = XS1_PORT_1E; out port setup_data_port = XS1_PORT_16B; -void app(client interface spi_master_if i, int mosi_enabled, int miso_enabled){ - +#if CB_ENABLED +#define SPEED_TESTS 3 +unsigned speed_lut[SPEED_TESTS] = {1000, 10000, 33000}; // Speed in kHz +#else #define SPEED_TESTS 1 - unsigned speed_lut[SPEED_TESTS] = {1500}; +unsigned speed_lut[SPEED_TESTS] = {1000}; // Speed in kHz +#endif - for(spi_mode_t mode = SPI_MODE_0; mode <= SPI_MODE_3; mode ++){ - for(unsigned speed_index = 0; speed_index < SPEED_TESTS; speed_index++){ - test_transfer8(i, setup_strobe_port, setup_data_port, 0, 100, - mode, speed_lut[speed_index], mosi_enabled, miso_enabled); - } + +void app(client interface spi_master_if i, int mosi_enabled, int miso_enabled, int spi_mode){ + + // printf("Device 8 SPI_MODE: %d\n", spi_mode); + for(unsigned speed_index = 0; speed_index < SPEED_TESTS; speed_index++){ + test_transfer8(i, setup_strobe_port, setup_data_port, 0, 100, + spi_mode, speed_lut[speed_index], mosi_enabled, miso_enabled); } - for(spi_mode_t mode = SPI_MODE_0; mode <= SPI_MODE_3; mode ++){ - for(unsigned speed_index = 0; speed_index < SPEED_TESTS; speed_index++){ - test_transfer32(i, setup_strobe_port, setup_data_port, 0, 100, - mode, speed_lut[speed_index], mosi_enabled, miso_enabled); - } + // printf("Device 32 SPI_MODE: %d\n", spi_mode); + for(unsigned speed_index = 0; speed_index < SPEED_TESTS; speed_index++){ + test_transfer32(i, setup_strobe_port, setup_data_port, 0, 100, + spi_mode, speed_lut[speed_index], mosi_enabled, miso_enabled); } - _Exit(1); + // printf("Device array SPI_MODE: %d\n", spi_mode); + for(unsigned speed_index = 0; speed_index < SPEED_TESTS; speed_index++){ + test_transfer32(i, setup_strobe_port, setup_data_port, 0, 100, + spi_mode, speed_lut[speed_index], mosi_enabled, miso_enabled); + } + + printf("Transfers complete\n"); + _Exit(0); } static void load(static const unsigned num_threads){ @@ -68,7 +79,7 @@ int main(){ interface spi_master_if i[1]; par { spi_master(i, 1, p_sclk, MOSI, MISO, p_ss, 1, CB); - app(i[0], MOSI_ENABLED, MISO_ENABLED); + app(i[0], MOSI_ENABLED, MISO_ENABLED, SPI_MODE); load(BURNT_THREADS); } return 0; diff --git a/tests/spi_master_sync_rx_tx/test_params.json b/tests/spi_master_sync_rx_tx/test_params.json new file mode 100644 index 0000000..0087ae2 --- /dev/null +++ b/tests/spi_master_sync_rx_tx/test_params.json @@ -0,0 +1,7 @@ +{ + "BURNT_THREADS": [3, 7], + "MISO_MOSI_ENABLED": ["miso", "mosi", "miso_and_mosi"], + "SPI_MODE": [0, 1, 2, 3], + "CB_ENABLED": [1, 0], + "arch": ["xs2", "xs3"] +} diff --git a/tests/spi_master_sync_shutdown/CMakeLists.txt b/tests/spi_master_sync_shutdown/CMakeLists.txt new file mode 100644 index 0000000..b467726 --- /dev/null +++ b/tests/spi_master_sync_shutdown/CMakeLists.txt @@ -0,0 +1,61 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +# Get JSON lists +file(READ ${CMAKE_CURRENT_LIST_DIR}/test_params.json params_json) + +# Get individual fields from params_json +string(JSON arch_list GET ${params_json} arch) +string(JSON distributed_list GET ${params_json} DISTRIBUTED) +string(JSON cb_enabled_list GET ${params_json} CB_ENABLED) + +string(JSON arch_list_len LENGTH ${arch_list}) +string(JSON distributed_list_len LENGTH ${distributed_list}) +string(JSON cb_enabled_list_len LENGTH ${cb_enabled_list}) + +# Subtract one off each of the lengths because RANGE includes last element +math(EXPR arch_list_len "${arch_list_len} - 1") +math(EXPR distributed_list_len "${distributed_list_len} - 1") +math(EXPR cb_enabled_list_len "${cb_enabled_list_len} - 1") + + +set(APP_PCA_ENABLE ON) +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) +include(${CMAKE_CURRENT_LIST_DIR}/../../examples/deps.cmake) + + +foreach(i RANGE 0 ${arch_list_len}) + string(JSON arch GET ${arch_list} ${i}) + if(arch STREQUAL "xs3") + set(target "XK-EVK-XU316") + elseif(arch STREQUAL "xs2") + set(target "XCORE-200-EXPLORER") + endif() + foreach(j RANGE 0 ${distributed_list_len}) + string(JSON distributed GET ${distributed_list} ${j}) + + foreach(k RANGE 0 ${cb_enabled_list_len}) + string(JSON cb_enabled GET ${cb_enabled_list} ${k}) + + set(config ${distributed}_${cb_enabled}_${arch}) + message(STATUS "building config ${config}") + + project(spi_master_sync_shutdown) + set(APP_HW_TARGET ${target}) + + set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} + -DDISTRIBUTED=${distributed} + -DCB_ENABLED=${cb_enabled} + -O2 + -g + -Wno-reinterpret-alignment) + + set(APP_INCLUDES src ../spi_master_tester_common) + + XMOS_REGISTER_APP() + + unset(APP_COMPILER_FLAGS_${config}) + unset(CONFIG_COMPILER_FLAGS) + endforeach() + endforeach() +endforeach() diff --git a/tests/spi_master_sync_shutdown/src/spi_master_sync_shutdown.xc b/tests/spi_master_sync_shutdown/src/spi_master_sync_shutdown.xc new file mode 100644 index 0000000..038f3ac --- /dev/null +++ b/tests/spi_master_sync_shutdown/src/spi_master_sync_shutdown.xc @@ -0,0 +1,78 @@ +// Copyright 2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. +#include +#include +#include +#include +#include "spi.h" +#include "spi_sync_tester.h" + + +in buffered port:32 p_miso = on tile[0]: XS1_PORT_1A; +out port p_ss = on tile[0]: XS1_PORT_1B; +out buffered port:32 p_sclk = on tile[0]: XS1_PORT_1C; +out buffered port:32 p_mosi = on tile[0]: XS1_PORT_1D; +clock cb = on tile[0]: XS1_CLKBLK_1; + +out port setup_strobe_port = on tile[0]: XS1_PORT_1E; +out port setup_data_port = on tile[0]: XS1_PORT_16B; + +#define SPI_MODE SPI_MODE_0 +#define SPI_KBPS 1000 + + +// We can only distribute if the main par is a flat list of tasks, not a loop +// However a clean exit should result in no exception +#if DISTRIBUTED +#define LOOPS 1 +#else +#define LOOPS 5 +#endif + +void app(client interface spi_master_if i, int mosi_enabled, int miso_enabled, int spi_mode){ + for(int loop = 0; loop < LOOPS; loop++){ + test_transfer8(i, setup_strobe_port, setup_data_port, 0, 100, + spi_mode, SPI_KBPS, mosi_enabled, miso_enabled); + + test_transfer32(i, setup_strobe_port, setup_data_port, 0, 100, + spi_mode, SPI_KBPS, mosi_enabled, miso_enabled); + + i.shutdown(); + } + + printf("Transfers complete\n"); + + // Should exit normally, no need for forced exit +} + +int main(){ + interface spi_master_if i[1]; + par { +#if DISTRIBUTED + par + { + #if CB_ENABLED + [[distribute]] + spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb); + #else + [[distribute]] + spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, null); + #endif + app(i[0], 1, 1, SPI_MODE); + } +#else // NOT distributed - uses own thread + par + { + on tile[0]: { + #if CB_ENABLED + for(int loop = 0; loop < LOOPS; loop++){spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, cb);} + #else + for(int loop = 0; loop < LOOPS; loop++){spi_master(i, 1, p_sclk, p_mosi, p_miso, p_ss, 1, null);} + #endif + } + on tile[0]: app(i[0], 1, 1, SPI_MODE); + } +#endif // NOT distributed + } + return 0; +} diff --git a/tests/spi_master_sync_shutdown/test_params.json b/tests/spi_master_sync_shutdown/test_params.json new file mode 100644 index 0000000..32b490a --- /dev/null +++ b/tests/spi_master_sync_shutdown/test_params.json @@ -0,0 +1,5 @@ +{ + "DISTRIBUTED": [0, 1], + "CB_ENABLED": [0, 1], + "arch": ["xs2", "xs3"] +} diff --git a/legacy_tests/lib_spi_master_tester/src/common.h b/tests/spi_master_tester_common/common.h similarity index 89% rename from legacy_tests/lib_spi_master_tester/src/common.h rename to tests/spi_master_tester_common/common.h index f002f32..608b9f1 100644 --- a/legacy_tests/lib_spi_master_tester/src/common.h +++ b/tests/spi_master_tester_common/common.h @@ -1,12 +1,12 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #ifndef COMMON_H_ #define COMMON_H_ static void set_mode_bits(spi_mode_t mode, unsigned &cpol, unsigned &cpha){ switch(mode){ - case SPI_MODE_0:cpol = 0; cpha= 1; break; - case SPI_MODE_1:cpol = 0; cpha= 0; break; + case SPI_MODE_0:cpol = 0; cpha= 0; break; + case SPI_MODE_1:cpol = 0; cpha= 1; break; case SPI_MODE_2:cpol = 1; cpha= 0; break; case SPI_MODE_3:cpol = 1; cpha= 1; break; } @@ -18,8 +18,10 @@ static void send_data_to_tester( unsigned data){ setup_data_port <: data; sync(setup_data_port); + setup_strobe_port <: 1; // Twice to meet timing on harness setup_strobe_port <: 1; setup_strobe_port <: 0; + setup_strobe_port <: 0; } static void broadcast_settings( diff --git a/legacy_tests/lib_spi_master_tester/src/spi_async_tester.h b/tests/spi_master_tester_common/spi_async_tester.h similarity index 77% rename from legacy_tests/lib_spi_master_tester/src/spi_async_tester.h rename to tests/spi_master_tester_common/spi_async_tester.h index 7bec60a..a2dcbb9 100644 --- a/legacy_tests/lib_spi_master_tester/src/spi_async_tester.h +++ b/tests/spi_master_tester_common/spi_async_tester.h @@ -1,9 +1,9 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #ifndef SPI_SYNC_TESTER_H_ #define SPI_SYNC_TESTER_H_ -#define VERBOSE 0 +#define VERBOSE 1 #include "common.h" diff --git a/legacy_tests/lib_spi_master_tester/src/spi_sync_tester.h b/tests/spi_master_tester_common/spi_sync_tester.h similarity index 51% rename from legacy_tests/lib_spi_master_tester/src/spi_sync_tester.h rename to tests/spi_master_tester_common/spi_sync_tester.h index 0576379..d35b50c 100644 --- a/legacy_tests/lib_spi_master_tester/src/spi_sync_tester.h +++ b/tests/spi_master_tester_common/spi_sync_tester.h @@ -1,9 +1,9 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #ifndef SPI_SYNC_TESTER_H_ #define SPI_SYNC_TESTER_H_ -#define VERBOSE 0 +#define VERBOSE 1 #include "common.h" @@ -25,17 +25,18 @@ int test_transfer8(client interface spi_master_if i, for(unsigned j=0;j #include #include #include #include "spi.h" +#include "common.h" out buffered port:32 p_miso = XS1_PORT_1A; in port p_ss = XS1_PORT_1B; @@ -17,91 +18,43 @@ out port setup_data_port = XS1_PORT_16B; in port setup_resp_port = XS1_PORT_1F; -#if (TRANSFER_SIZE == SPI_TRANSFER_SIZE_8) -#define BITS_PER_TRANSFER 8 -#elif (TRANSFER_SIZE == SPI_TRANSFER_SIZE_32) -#define BITS_PER_TRANSFER 32 +#if (TRANSFER_SIZE == 8) +#define SPI_TRANSFER_SIZE SPI_TRANSFER_SIZE_8 +#elif (TRANSFER_SIZE == 32) +#define SPI_TRANSFER_SIZE SPI_TRANSFER_SIZE_32 #else #error Invalid transfer size given #endif -static void set_mode_bits(spi_mode_t mode, unsigned &cpol, unsigned &cpha){ - switch(mode){ - case SPI_MODE_0:cpol = 0; cpha= 1; break; - case SPI_MODE_1:cpol = 0; cpha= 0; break; - case SPI_MODE_2:cpol = 1; cpha= 0; break; - case SPI_MODE_3:cpol = 1; cpha= 1; break; - } -} - -static void send_data_to_tester( - out port setup_strobe_port, - out port setup_data_port, - unsigned data){ - setup_data_port <: data; - sync(setup_data_port); - setup_strobe_port <: 1; - setup_strobe_port <: 0; -} - -static void broadcast_settings( - out port setup_strobe_port, - out port setup_data_port, - spi_mode_t mode, - int mosi_enabled, - int miso_enabled, - unsigned num_bits, - unsigned kbps, - unsigned initial_clock_delay // in ns -){ - unsigned cpha, cpol; - - set_mode_bits(mode, cpol, cpha); - - // printf("Testing: %d %d\n", kbps, initial_clock_delay); - - setup_strobe_port <: 0; - - send_data_to_tester(setup_strobe_port, setup_data_port, cpol); - send_data_to_tester(setup_strobe_port, setup_data_port, cpha); - send_data_to_tester(setup_strobe_port, setup_data_port, miso_enabled); - send_data_to_tester(setup_strobe_port, setup_data_port, num_bits); - send_data_to_tester(setup_strobe_port, setup_data_port, kbps); - send_data_to_tester(setup_strobe_port, setup_data_port, initial_clock_delay); -} - -static int request_response( - out port setup_strobe_port, - in port setup_resp_port -){ - int r; - setup_strobe_port <: 1; - setup_strobe_port <: 0; - setup_resp_port :> r; - return r; - -} [[combinable]] void app(server interface spi_slave_callback_if spi_i, int mosi_enabled, int miso_enabled){ + (const void*)tx_data; // Remove warning of unused var + (const void*)rx_data; // Remove warning of unused var + unsigned bpt = 0; - spi_transfer_type_t tt = TRANSFER_SIZE; + spi_transfer_type_t tt = SPI_TRANSFER_SIZE; switch(tt){ case SPI_TRANSFER_SIZE_8:bpt = 8;break; case SPI_TRANSFER_SIZE_32:bpt = 32;break; } + // Clock delay after SS in nanoseconds unsigned cd_max = 40000; unsigned cd_min = 0; unsigned cd = (cd_max + cd_min)/2; + unsigned cd_last_good = cd_max; - unsigned kbps_max = 250000; + // SPI speed + unsigned kbps_max = 100000; unsigned kbps_min = 0; unsigned kbps = (kbps_max + kbps_min)/2; -// unsigned kbps = 7692; + unsigned kbps_last_good = kbps_min; + + int found_solution = 0; int finding_speed = 1; @@ -124,58 +77,74 @@ void app(server interface spi_slave_callback_if spi_i, 0xfefdfbf7, 0xefdfbf7f }; int error = 0; + // printf("broadcast_settings\n"); broadcast_settings(setup_strobe_port, setup_data_port, SPI_MODE, mosi_enabled, miso_enabled, bpt*4, kbps, cd); unsigned rx_count = 0; unsigned tx_count = 0; unsigned rep_count = 0; + while(1){ select { case spi_i.master_requires_data() -> uint32_t r:{ switch(tt){ - case SPI_TRANSFER_SIZE_8: - tx_count &= 0xf; - r = tx_data_8[tx_count++]; - break; - case SPI_TRANSFER_SIZE_32: - tx_count &= 0x3; - r = tx_data_32[tx_count++]; - break; - default: - __builtin_unreachable(); - break; + case SPI_TRANSFER_SIZE_8: + tx_count &= 0xf; + r = tx_data_8[tx_count++]; + break; + case SPI_TRANSFER_SIZE_32: + tx_count &= 0x3; + r = tx_data_32[tx_count++]; + break; + default: + __builtin_unreachable(); + break; } break; } case spi_i.master_supplied_data(uint32_t datum, uint32_t valid_bits):{ switch(tt){ - case SPI_TRANSFER_SIZE_8: - rx_count &= 0xf; - if(datum != rx_data_8[rx_count]) - error=1; - break; - case SPI_TRANSFER_SIZE_32: - rx_count &= 0x3; - if(datum != rx_data_32[rx_count]) - error=1; - break; - default: - __builtin_unreachable(); - break; + case SPI_TRANSFER_SIZE_8: + rx_count &= 0xf; + if(datum != rx_data_8[rx_count]){ + error=1; + printf("Error in receiving slave 8 MOSI, expected: 0x%x got: 0x%x\n", rx_data_8[rx_count], datum); + } + break; + case SPI_TRANSFER_SIZE_32: + rx_count &= 0x3; + if(datum != rx_data_32[rx_count]){ + error=1; + printf("Error in receiving slave 32 MOSI, expected: 0x%x got: 0x%x\n", rx_data_32[rx_count], datum); + } + break; + default: + __builtin_unreachable(); + break; } rx_count++; - if(valid_bits != bpt) + if(valid_bits != bpt){ error = 1; + printf("Error in receiving slave bpt expected: %d got: %d\n", bpt, valid_bits); + } break; } case spi_i.master_ends_transaction():{ + error |= request_response(setup_strobe_port, setup_resp_port); + if(!error){ + found_solution = 1; + cd_last_good = cd; + kbps_last_good = kbps; + } + + // First do speed if(finding_speed){ if(error == 1) kbps_max = kbps; @@ -185,7 +154,7 @@ void app(server interface spi_slave_callback_if spi_i, unsigned next_kbps = (kbps_max + kbps_min)/2; if(next_kbps == kbps){ rep_count++; - if(rep_count == 8){ + if(rep_count == 4){ finding_speed = 0; rep_count = 0; } @@ -207,9 +176,14 @@ void app(server interface spi_slave_callback_if spi_i, unsigned next_cd = (cd_max + cd_min)/2; if(next_cd == cd){ rep_count++; - if(rep_count == 8){ - printf("%d %d %d %d %d %d %d\n", SPI_MODE, TRANSFER_SIZE, BURNT_THREADS, miso_enabled, mosi_enabled, cd, kbps); - _Exit(1); + if(rep_count == 4){ + if(found_solution){ + printf("RESULT: %d %d %d %d %d %d %d\n", SPI_MODE, TRANSFER_SIZE, BURNT_THREADS, miso_enabled, mosi_enabled, cd_last_good, kbps_last_good); + _Exit(0); + } else { + printf("ERROR! Run did not find a workable setting\n"); + _Exit(-1); + } } } else{ @@ -224,6 +198,8 @@ void app(server interface spi_slave_callback_if spi_i, } } + // printf("error from host: %d\n", error); + // printf("broadcast_NEW settings mode: %d mosi_enabled %d miso_enabled %d, num_bits %d kbps %d cd: %u\n", SPI_MODE, mosi_enabled, miso_enabled, bpt*4, kbps, cd); broadcast_settings(setup_strobe_port, setup_data_port, SPI_MODE, mosi_enabled, miso_enabled, bpt*4, kbps, cd); error = 0; @@ -257,11 +233,11 @@ int main(){ #if COMBINED == 1 [[combine]] par { - spi_slave(i, p_sclk, p_mosi, MISO, p_ss, cb, SPI_MODE, TRANSFER_SIZE); + spi_slave(i, p_sclk, p_mosi, MISO, p_ss, cb, SPI_MODE, SPI_TRANSFER_SIZE); app(i, MOSI_ENABLED, MISO_ENABLED); } #else - spi_slave(i, p_sclk, p_mosi, MISO, p_ss, cb, SPI_MODE, TRANSFER_SIZE); + spi_slave(i, p_sclk, p_mosi, MISO, p_ss, cb, SPI_MODE, SPI_TRANSFER_SIZE); app(i, MOSI_ENABLED, MISO_ENABLED); #endif load(BURNT_THREADS); diff --git a/tests/spi_slave_benchmark/test_params.json b/tests/spi_slave_benchmark/test_params.json new file mode 100644 index 0000000..5efebf2 --- /dev/null +++ b/tests/spi_slave_benchmark/test_params.json @@ -0,0 +1,24 @@ +{ + "THREAD_PROFILES": [ + { + "COMBINED": 1, + "BURNT_THREADS": 3 + }, + { + "COMBINED": 1, + "BURNT_THREADS": 7 + }, + { + "COMBINED": 0, + "BURNT_THREADS": 2 + }, + { + "COMBINED": 0, + "BURNT_THREADS": 6 + } + ], + "MISO_ENABLED": [0, 1], + "MODE": [0, 1, 2, 3], + "TRANSFER_SIZE": [8, 32], + "arch": ["xs2", "xs3"] +} diff --git a/tests/spi_slave_checker.py b/tests/spi_slave_checker.py new file mode 100644 index 0000000..65f5479 --- /dev/null +++ b/tests/spi_slave_checker.py @@ -0,0 +1,177 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +import Pyxsim as px +from functools import partial + +# We need to disable output buffering for this test to work on MacOS; this has +# no effect on Linux systems. Let's redefine print once to avoid putting the +# same argument everywhere. +print = partial(print, flush=True) + + +class SPISlaveChecker(px.SimThread): + """" + This simulator thread will act as SPI master and check any transactions + caused by the master. + """ + def __init__(self, + sck_port: str, + mosi_port: str, + miso_port: str, + ss_port: str, + setup_strobe_port: str, + setup_data_port: str, + setup_resp_port: str) -> None: + self._miso_port = miso_port + self._mosi_port = mosi_port + self._sck_port = sck_port + self._ss_port = ss_port + self._setup_strobe_port = setup_strobe_port + self._setup_data_port = setup_data_port + self._setup_resp_port = setup_resp_port + + def get_setup_data(self, + xsi: px.pyxsim.Xsi, + setup_strobe_port: str, + setup_data_port: str) -> int: + self.wait_for_port_pins_change([setup_strobe_port]) + self.wait_for_port_pins_change([setup_strobe_port]) + return xsi.sample_port_pins(setup_data_port) + + def run(self): + xsi: px.pyxsim.Xsi = self.xsi + xsi.drive_port_pins(self._ss_port,1) + + print("SPI Slave checker started") + + # some timing constants + xsi_tick_freq_hz = float(1e15) # pending merge of https://github.com/xmos/test_support/blob/develop/lib/python/Pyxsim/pyxsim.py#L246-L265 + nanosecond_ticks = xsi_tick_freq_hz / 1e9 + microsecond_ticks = xsi_tick_freq_hz / 1e6 + millisecond_ticks = xsi_tick_freq_hz / 1e3 + + while True: + #first do the setup rx + strobe_val = xsi.sample_port_pins(self._setup_strobe_port) + if strobe_val == 1: + xsi.drive_port_pins(self._sck_port, expected_cpol) + xsi.drive_port_pins(self._ss_port, 1) + self.wait_for_port_pins_change([self._setup_strobe_port]) + + expected_cpol = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_cpha = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_miso_enabled = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_num_bits = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + kbps = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + initial_clock_delay = int(self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port)) + print(f"Got Settings:cpol {expected_cpol} cpha {expected_cpha} miso {expected_miso_enabled} num_bits {expected_num_bits} kbps {kbps} init delay {initial_clock_delay} ") + initial_clock_delay = initial_clock_delay * nanosecond_ticks + + # drive initial values while slave starts up for the first time + xsi.drive_port_pins(self._sck_port, expected_cpol) + xsi.drive_port_pins(self._ss_port, 1) + + time_trigger = xsi.get_time() + time_trigger += 10 * microsecond_ticks + self.wait_until(time_trigger) + + # check MISO isn't driving + miso_driving = xsi.is_port_driving(self._miso_port) + if miso_driving: + print(f"Error: MISO still driving before ss assert") + + + xsi.drive_port_pins(self._setup_resp_port, 0) # This port also doubles as tester ready to report signal + xsi.drive_port_pins(self._sck_port, expected_cpol) + xsi.drive_port_pins(self._ss_port, 0) + + time_trigger += initial_clock_delay + self.wait_until(time_trigger) + + tx_data = [0xaa, 0xf7, 0xfb, 0xef, 0xdf, 0xbf, 0xfd, 0x7f, 0x01, 0x08, 0x04, 0x10, 0x20, 0x04, 0x02, 0x80] + rx_data = [0xaa, 0x02, 0x04, 0x08, 0x10, 0x20, 0x04, 0x80, 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f] + rx_byte = 0 + tx_byte = tx_data[0] + + clock_val = (expected_cpol^expected_cpha)&1 + bit_count = 0 + total_bit_count = 0 + byte_count = 0 + + half_clock = millisecond_ticks/(2*kbps) + error = 0 + + while total_bit_count < expected_num_bits: + # print (f"Drive bit {total_bit_count} @ {xsi.get_time()}") + #clock edge and drive data out + xsi.drive_port_pins(self._sck_port, clock_val) + xsi.drive_port_pins(self._mosi_port,(tx_byte>>7)&1) + tx_byte = tx_byte<<1 + + time_trigger += half_clock + self.wait_until(time_trigger) + + #clockedge and read data in + xsi.drive_port_pins(self._sck_port, 1-clock_val) + val = xsi.sample_port_pins(self._miso_port) + + time_trigger += half_clock + self.wait_until(time_trigger) + + rx_byte = (rx_byte<<1) + val + bit_count = bit_count + 1 + total_bit_count = total_bit_count + 1 + if bit_count == 8: + bit_count = 0 + if expected_miso_enabled: + if rx_byte != rx_data[byte_count]: + error = 1 + print(f"Error: tester MISO got:{rx_byte:02x} expected:{rx_data[byte_count]:02x} byte_count:{byte_count} at time: {xsi.get_time() / nanosecond_ticks}ns") + rx_byte = 0 + byte_count = byte_count + 1 + if byte_count*8 < expected_num_bits: + tx_byte = tx_data[byte_count] + + #check the final few rx'd bits + if bit_count and expected_miso_enabled: + if rx_byte != rx_data[byte_count]>>(8-bit_count): + error = 1 + print(f"Error: MISO sub bit rx got:{rx_byte:02x} expected:{rx_data[byte_count]>>(8-bit_count):02x} {byte_count} at time: {xsi.get_time() / nanosecond_ticks}ns") + + time_trigger += half_clock + self.wait_until(time_trigger) + + # Deassert SS + xsi.drive_port_pins(self._sck_port, expected_cpol) + xsi.drive_port_pins(self._ss_port, 1) + ss_deasserted_time = time_trigger + + # Test MISO is disabled + count_nanoseconds = 0 + max_nanoseconds = 2000 # This is quite lax because, in the test master_supplied_data() does a lot of processing and delays MISO being de-asserted + # We typically see times of 150ns or less + miso_driving = xsi.is_port_driving(self._miso_port) + while miso_driving and count_nanoseconds < max_nanoseconds: + miso_driving = xsi.is_port_driving(self._miso_port) + time_trigger += nanosecond_ticks + self.wait_until(time_trigger) + count_nanoseconds += 1 + if miso_driving: + error = 1 + print(f"Error: MISO still driving {max_nanoseconds}ns after ss deassert, at time: {xsi.get_time() / nanosecond_ticks}ns") + # print(f"MISO deasserted at {(time_trigger - ss_deasserted_time) / nanosecond_ticks}ns after SS, at time: {xsi.get_time() / nanosecond_ticks}ns") + + + # Report back to DUT + if xsi.sample_port_pins(self._setup_strobe_port) != 0: + print("Error - setup_strobe_port not 0 at end of test") + error = 1 + # setup strobe (trigger to DUT) is low so DUT not requested yet + + # This section corresponds to request_response() in the DUT + xsi.drive_port_pins(self._setup_resp_port, 1) # Tester ready to report + self.wait_for_port_pins_change([self._setup_strobe_port]) # Wait for DUT to ready read, sends 1 + xsi.drive_port_pins(self._setup_resp_port, error) + self.wait_for_port_pins_change([self._setup_strobe_port]) # wait for it to go low again + + diff --git a/tests/spi_slave_checker_intertransaction.py b/tests/spi_slave_checker_intertransaction.py new file mode 100644 index 0000000..e4dd0a1 --- /dev/null +++ b/tests/spi_slave_checker_intertransaction.py @@ -0,0 +1,143 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. + +import Pyxsim as px +from functools import partial + +# We need to disable output buffering for this test to work on MacOS; this has +# no effect on Linux systems. Let's redefine print once to avoid putting the +# same argument everywhere. +print = partial(print, flush=True) + + +class SPISlaveIntertransactionChecker(px.SimThread): + """" + This simulator thread will act as SPI slave and check any transactions + caused by the master. + """ + def __init__(self, + sck_port: str, + mosi_port: str, + miso_port: str, + ss_port: str, + setup_strobe_port: str, + setup_data_port: str, + setup_resp_port: str, + master_req_exit_port: str, + starting_delay: int, + delay_step: int) -> None: + self._miso_port = miso_port + self._mosi_port = mosi_port + self._sck_port = sck_port + self._ss_port = ss_port + self._setup_strobe_port = setup_strobe_port + self._setup_data_port = setup_data_port + self._setup_resp_port = setup_resp_port + self._master_req_exit_port = master_req_exit_port + self._intertransaction_delay = starting_delay + self._delay_step = delay_step + + def get_setup_data(self, + xsi: px.pyxsim.Xsi, + setup_strobe_port: str, + setup_data_port: str) -> int: + self.wait_for_port_pins_change([setup_strobe_port]) + self.wait_for_port_pins_change([setup_strobe_port]) + return xsi.sample_port_pins(setup_data_port) + + def run(self): + xsi: px.pyxsim.Xsi = self.xsi + xsi.drive_port_pins(self._ss_port,1) + + print("SPI Slave checker started") + + #first do the setup rx + strobe_val = xsi.sample_port_pins(self._setup_strobe_port) + if strobe_val == 1: + xsi.drive_port_pins(self._sck_port, expected_cpol) + xsi.drive_port_pins(self._ss_port, 1) + self.wait_for_port_pins_change([self._setup_strobe_port]) + + expected_cpol = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_cpha = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_miso_enabled = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + expected_num_bits = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + kbps = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + initial_clock_delay = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) * 1000 + print(f"Got Settings:cpol {expected_cpol} cpha {expected_cpha} miso {expected_miso_enabled} num_bits {expected_num_bits} kbps {kbps} init delay {initial_clock_delay} ") + + # drive initial values while slave starts up for the first time + xsi.drive_port_pins(self._sck_port, expected_cpol) + xsi.drive_port_pins(self._ss_port, 1) + self.wait_until(xsi.get_time() + 10000000) + error = 0 + + while True: + self.wait_until(xsi.get_time() + self._intertransaction_delay) + + error_check = xsi.sample_port_pins(self._setup_strobe_port) + if error == 1 or error_check == 1: + print(f"Delay is {self._intertransaction_delay/1000} ns") + print("Request exit on error") + xsi.drive_port_pins(self._master_req_exit_port, 1) + + if self._intertransaction_delay > 0: + self._intertransaction_delay = self._intertransaction_delay - self._delay_step + if self._intertransaction_delay < 0: + self._intertransaction_delay = 0 + else: + print(f"Delay is {self._intertransaction_delay}") + print("Request exit on success") + xsi.drive_port_pins(self._master_req_exit_port, 1) + + xsi.drive_port_pins(self._sck_port, expected_cpol) + xsi.drive_port_pins(self._ss_port, 0) + self.wait_until(xsi.get_time() + initial_clock_delay) + + tx_data = [0xaa, 0xf7, 0xfb, 0xef, 0xdf, 0xbf, 0xfd, 0x7f, 0x01, 0x08, 0x04, 0x10, 0x20, 0x04, 0x02, 0x80] + rx_data = [0xaa, 0x02, 0x04, 0x08, 0x10, 0x20, 0x04, 0x80, 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f] + rx_byte = 0 + tx_byte = tx_data[0] + + clock_val = (expected_cpol^expected_cpha)&1 + bit_count = 0 + total_bit_count = 0 + byte_count = 0 + + half_clock = 1000000000/(2*kbps) + + while total_bit_count < expected_num_bits: + # print "Drive bit %d" % total_bit_count + #clock edge and drive data out + xsi.drive_port_pins(self._sck_port, clock_val) + xsi.drive_port_pins(self._mosi_port,(tx_byte>>7)&1) + tx_byte = tx_byte<<1 + self.wait_until(xsi.get_time() + half_clock) + + #clockedge and read data in + xsi.drive_port_pins(self._sck_port, 1-clock_val) + val = xsi.sample_port_pins(self._miso_port) + self.wait_until(xsi.get_time() + half_clock) + rx_byte = (rx_byte<<1) + val + bit_count = bit_count + 1 + total_bit_count = total_bit_count + 1 + if bit_count == 8: + bit_count = 0 + if expected_miso_enabled: + if rx_byte != rx_data[byte_count]: + error = 1 + # print(f"frx got:{rx_byte:02x} expected:{rx_data[byte_count]:02x} {byte_count}") + rx_byte = 0 + byte_count = byte_count + 1 + if byte_count*8 < expected_num_bits: + tx_byte = tx_data[byte_count] + + #check the final few rx'd bits + if bit_count and expected_miso_enabled: + if rx_byte != rx_data[byte_count]>>(8-bit_count): + error = 1 + # print(f"sub bit rx got:{rx_byte:02x} expected:{rx_data[byte_count]>>(8-bit_count):02x} {byte_count}") + self.wait_until(xsi.get_time() + half_clock) + + xsi.drive_port_pins(self._sck_port, expected_cpol) + xsi.drive_port_pins(self._ss_port, 1) diff --git a/tests/spi_slave_rx_tx/CMakeLists.txt b/tests/spi_slave_rx_tx/CMakeLists.txt new file mode 100644 index 0000000..b719463 --- /dev/null +++ b/tests/spi_slave_rx_tx/CMakeLists.txt @@ -0,0 +1,82 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +# Get JSON lists +file(READ ${CMAKE_CURRENT_LIST_DIR}/test_params.json params_json) + +# Get individual fields from params_json +string(JSON arch_list GET ${params_json} arch) +string(JSON thread_profile_list GET ${params_json} THREAD_PROFILES) +string(JSON mode_list GET ${params_json} MODE) +string(JSON transfer_size_list GET ${params_json} TRANSFER_SIZE) +string(JSON miso_enabled_list GET ${params_json} MISO_ENABLED) + +string(JSON arch_list_len LENGTH ${arch_list}) +string(JSON thread_profile_list_len LENGTH ${thread_profile_list}) +string(JSON mode_list_len LENGTH ${mode_list}) +string(JSON transfer_size_list_len LENGTH ${transfer_size_list}) +string(JSON miso_enabled_list_len LENGTH ${miso_enabled_list}) + + +# Subtract one off each of the lengths because RANGE includes last element +math(EXPR arch_list_len "${arch_list_len} - 1") +math(EXPR thread_profile_list_len "${thread_profile_list_len} - 1") +math(EXPR mode_list_len "${mode_list_len} - 1") +math(EXPR transfer_size_list_len "${transfer_size_list_len} - 1") +math(EXPR miso_enabled_list_len "${miso_enabled_list_len} - 1") + + +set(APP_PCA_ENABLE ON) +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) +include(${CMAKE_CURRENT_LIST_DIR}/../../examples/deps.cmake) + + +foreach(i RANGE 0 ${arch_list_len}) + string(JSON arch GET ${arch_list} ${i}) + if(arch STREQUAL "xs3") + set(target "XK-EVK-XU316") + elseif(arch STREQUAL "xs2") + set(target "XCORE-200-EXPLORER") + endif() + foreach(j RANGE 0 ${thread_profile_list_len}) + string(JSON thread_profile GET ${thread_profile_list} ${j}) + string(JSON COMBINED GET ${thread_profile} COMBINED) + string(JSON BURNT_THREADS GET ${thread_profile} BURNT_THREADS) + + foreach(k RANGE 0 ${mode_list_len}) + string(JSON SPI_MODE GET ${mode_list} ${k}) + + foreach(l RANGE 0 ${transfer_size_list_len}) + string(JSON SPI_TRANSFER_SIZE GET ${transfer_size_list} ${l}) + + foreach(m RANGE 0 ${miso_enabled_list_len}) + string(JSON MISO_ENABLED GET ${miso_enabled_list} ${m}) + + set(config ${COMBINED}_${BURNT_THREADS}_${MISO_ENABLED}_${SPI_MODE}_${SPI_TRANSFER_SIZE}_${arch}) + message(STATUS "building config ${config}") + + project(spi_slave_rx_tx) + set(APP_HW_TARGET ${target}) + + set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} + -DCOMBINED=${COMBINED} + -DBURNT_THREADS=${BURNT_THREADS} + -DMISO_ENABLED=${MISO_ENABLED} + -DSPI_MODE=${SPI_MODE} + -DTRANSFER_SIZE=SPI_TRANSFER_SIZE_${SPI_TRANSFER_SIZE} + -O2 + -g + -Wno-reinterpret-alignment) + + set(APP_INCLUDES src ../spi_slave_tester_common) + + XMOS_REGISTER_APP() + message(STATUS "****${APP_COMPILER_FLAGS_${config}} ") + + unset(APP_COMPILER_FLAGS_${config}) + unset(CONFIG_COMPILER_FLAGS) + endforeach() + endforeach() + endforeach() + endforeach() +endforeach() diff --git a/legacy_tests/spi_master_sync_rx_tx/config.xscope b/tests/spi_slave_rx_tx/config.xscope similarity index 100% rename from legacy_tests/spi_master_sync_rx_tx/config.xscope rename to tests/spi_slave_rx_tx/config.xscope diff --git a/legacy_tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc b/tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc similarity index 70% rename from legacy_tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc rename to tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc index 991d283..0e73187 100644 --- a/legacy_tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc +++ b/tests/spi_slave_rx_tx/src/spi_slave_rx_tx.xc @@ -1,10 +1,11 @@ -// Copyright 2015-2021 XMOS LIMITED. +// Copyright 2015-2025 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include #include #include #include #include "spi.h" +#include "common.h" out buffered port:32 p_miso = XS1_PORT_1A; in port p_ss = XS1_PORT_1B; @@ -16,19 +17,8 @@ out port setup_strobe_port = XS1_PORT_1E; out port setup_data_port = XS1_PORT_16B; in port setup_resp_port = XS1_PORT_1F; -#define NUMBER_OF_TEST_BYTES 16 #define KBPS 1000 -static const uint8_t tx_data[NUMBER_OF_TEST_BYTES] = { - 0xaa, 0x02, 0x04, 0x08, 0x10, 0x20, 0x04, 0x80, - 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f -}; - -static const uint8_t rx_data[NUMBER_OF_TEST_BYTES] = { - 0xaa, 0xf7, 0xfb, 0xef, 0xdf, 0xbf, 0xfd, 0x7f, - 0x01, 0x08, 0x04, 0x10, 0x20, 0x04, 0x02, 0x80, -}; - #if (TRANSFER_SIZE == SPI_TRANSFER_SIZE_8) #define BITS_PER_TRANSFER 8 @@ -39,60 +29,8 @@ static const uint8_t rx_data[NUMBER_OF_TEST_BYTES] = { #endif -static void set_mode_bits(spi_mode_t mode, unsigned &cpol, unsigned &cpha){ - switch(mode){ - case SPI_MODE_0:cpol = 0; cpha= 1; break; - case SPI_MODE_1:cpol = 0; cpha= 0; break; - case SPI_MODE_2:cpol = 1; cpha= 0; break; - case SPI_MODE_3:cpol = 1; cpha= 1; break; - } -} - -static void send_data_to_tester( - out port setup_strobe_port, - out port setup_data_port, - unsigned data){ - setup_data_port <: data; - sync(setup_data_port); - setup_strobe_port <: 1; - setup_strobe_port <: 0; -} - -static void broadcast_settings( - out port setup_strobe_port, - out port setup_data_port, - spi_mode_t mode, - int mosi_enabled, - int miso_enabled, - unsigned num_bits, - unsigned kbps, - unsigned initial_clock_delay // in ns -){ - unsigned cpha, cpol; - - set_mode_bits(mode, cpol, cpha); - - setup_strobe_port <: 0; - - send_data_to_tester(setup_strobe_port, setup_data_port, cpol); - send_data_to_tester(setup_strobe_port, setup_data_port, cpha); - send_data_to_tester(setup_strobe_port, setup_data_port, miso_enabled); - send_data_to_tester(setup_strobe_port, setup_data_port, num_bits); - send_data_to_tester(setup_strobe_port, setup_data_port, kbps); - send_data_to_tester(setup_strobe_port, setup_data_port, initial_clock_delay); -} - -static int request_response( - out port setup_strobe_port, - in port setup_resp_port -){ - int r; - setup_strobe_port <: 1; - setup_strobe_port <: 0; - setup_resp_port :> r; - return r; +// This sends 128b transfer then steps through from 1b to SPI_TRANSFER_SIZE bits and exits -} [[combinable]] void app(server interface spi_slave_callback_if spi_i, int mosi_enabled, int miso_enabled){ @@ -108,6 +46,9 @@ void app(server interface spi_slave_callback_if spi_i, unsigned num_bits = NUMBER_OF_TEST_BYTES*8; //First check a multi byte transfer + printf("Send initial settings\n"); + // printf("%u\n", num_bits); + broadcast_settings(setup_strobe_port, setup_data_port, SPI_MODE, mosi_enabled, miso_enabled, num_bits, KBPS, 2000); @@ -116,6 +57,7 @@ void app(server interface spi_slave_callback_if spi_i, while(1){ select { case spi_i.master_requires_data() -> uint32_t r:{ + // printf("master_requires_data\n"); if(tx_byte_no < NUMBER_OF_TEST_BYTES){ switch(tt){ case SPI_TRANSFER_SIZE_8: @@ -133,16 +75,19 @@ void app(server interface spi_slave_callback_if spi_i, } if(!miso_enabled){ printf("Error: master cannot require data when miso is not enabled\n"); + delay_after_print(); _Exit(1); } break; } case spi_i.master_supplied_data(uint32_t datum, uint32_t valid_bits):{ + // printf("master_supplied_data\n"); for(unsigned i=0; i> (valid_bits - 8))&0xff; if(rx_data[rx_byte_no] != d){ printf("Error: Expected %02x from master but got %02x for transfer of %d\n", rx_data[rx_byte_no], d, num_bits); + delay_after_print(); _Exit(1); } rx_byte_no++; @@ -160,6 +105,7 @@ void app(server interface spi_slave_callback_if spi_i, if(datum != d){ printf("Error: Expected %02x from master but got %02x for transfer of %d\n", d, datum, num_bits); + delay_after_print(); _Exit(1); } } @@ -167,19 +113,31 @@ void app(server interface spi_slave_callback_if spi_i, } case spi_i.master_ends_transaction():{ + // printf("master_ends_transaction\n"); //Then check all sub word transfers - if(num_bits == NUMBER_OF_TEST_BYTES*8) + if(num_bits == NUMBER_OF_TEST_BYTES*8){ num_bits = 0; + } + if(num_bits == bpt){ + printf("Test completed\n"); + delay_after_print(); + _Exit(0); + } num_bits++; int r = request_response(setup_strobe_port, setup_resp_port); + if(r){ printf("Error: Master Rx error\n"); + delay_after_print(); _Exit(1); - } - if(num_bits > bpt) + if(num_bits > bpt){ + printf("Error: Too many bits %d expecting %d\n", num_bits, bpt); + delay_after_print(); _Exit(1); + } + broadcast_settings(setup_strobe_port, setup_data_port, SPI_MODE, mosi_enabled, miso_enabled, num_bits, KBPS, 2000); diff --git a/tests/spi_slave_rx_tx/test_params.json b/tests/spi_slave_rx_tx/test_params.json new file mode 100644 index 0000000..5efebf2 --- /dev/null +++ b/tests/spi_slave_rx_tx/test_params.json @@ -0,0 +1,24 @@ +{ + "THREAD_PROFILES": [ + { + "COMBINED": 1, + "BURNT_THREADS": 3 + }, + { + "COMBINED": 1, + "BURNT_THREADS": 7 + }, + { + "COMBINED": 0, + "BURNT_THREADS": 2 + }, + { + "COMBINED": 0, + "BURNT_THREADS": 6 + } + ], + "MISO_ENABLED": [0, 1], + "MODE": [0, 1, 2, 3], + "TRANSFER_SIZE": [8, 32], + "arch": ["xs2", "xs3"] +} diff --git a/tests/spi_slave_shutdown/CMakeLists.txt b/tests/spi_slave_shutdown/CMakeLists.txt new file mode 100644 index 0000000..1eb36ad --- /dev/null +++ b/tests/spi_slave_shutdown/CMakeLists.txt @@ -0,0 +1,52 @@ +cmake_minimum_required(VERSION 3.21) +include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake) + +# Get JSON lists +file(READ ${CMAKE_CURRENT_LIST_DIR}/test_params.json params_json) + +# Get individual fields from params_json +string(JSON arch_list GET ${params_json} arch) +string(JSON combined_list GET ${params_json} COMBINED) + +string(JSON arch_list_len LENGTH ${arch_list}) +string(JSON combined_list_len LENGTH ${combined_list}) + +# Subtract one off each of the lengths because RANGE includes last element +math(EXPR arch_list_len "${arch_list_len} - 1") +math(EXPR combined_list_len "${combined_list_len} - 1") + + +set(APP_PCA_ENABLE ON) +set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..) +include(${CMAKE_CURRENT_LIST_DIR}/../../examples/deps.cmake) + + +foreach(i RANGE 0 ${arch_list_len}) + string(JSON arch GET ${arch_list} ${i}) + if(arch STREQUAL "xs3") + set(target "XK-EVK-XU316") + elseif(arch STREQUAL "xs2") + set(target "XCORE-200-EXPLORER") + endif() + foreach(j RANGE 0 ${combined_list_len}) + string(JSON combined GET ${combined_list} ${j}) + + set(config ${combined}_${arch}) + message(STATUS "building config ${config}") + + project(spi_slave_shutdown) + set(APP_HW_TARGET ${target}) + + set(APP_COMPILER_FLAGS_${config} ${CONFIG_COMPILER_FLAGS} + -DCOMBINED=${combined} + -O2 + -g + -Wno-reinterpret-alignment) + set(APP_INCLUDES src ../spi_slave_tester_common) + + XMOS_REGISTER_APP() + + unset(APP_COMPILER_FLAGS_${config}) + unset(CONFIG_COMPILER_FLAGS) + endforeach() +endforeach() diff --git a/legacy_tests/spi_slave_benchmark/config.xscope b/tests/spi_slave_shutdown/config.xscope similarity index 100% rename from legacy_tests/spi_slave_benchmark/config.xscope rename to tests/spi_slave_shutdown/config.xscope diff --git a/tests/spi_slave_shutdown/src/spi_slave_shutdown.xc b/tests/spi_slave_shutdown/src/spi_slave_shutdown.xc new file mode 100644 index 0000000..ae4e99e --- /dev/null +++ b/tests/spi_slave_shutdown/src/spi_slave_shutdown.xc @@ -0,0 +1,194 @@ +// Copyright 2015-2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. +#include +#include +#include +#include +#include "spi.h" +#include "common.h" + +out buffered port:32 p_miso = XS1_PORT_1A; +in port p_ss = XS1_PORT_1B; +in port p_sclk = XS1_PORT_1C; +in buffered port:32 p_mosi = XS1_PORT_1D; +clock cb = XS1_CLKBLK_1; + +out port setup_strobe_port = XS1_PORT_1E; +out port setup_data_port = XS1_PORT_16B; +in port setup_resp_port = XS1_PORT_1F; + +#define NUMBER_OF_TEST_BYTES 16 +#define KBPS 1000 +#define SPI_MODE SPI_MODE_0 +#define BURNT_THREADS 0 +#define TRANSFER_SIZE SPI_TRANSFER_SIZE_8 + + + +// This sends 128b transfer then steps through from 1b to SPI_TRANSFER_SIZE bits and exits + +[[combinable]] +void app(server interface spi_slave_callback_if spi_i, + int mosi_enabled, int miso_enabled){ + + unsigned bpt = 0; + spi_transfer_type_t tt = TRANSFER_SIZE; + switch(tt){ + case SPI_TRANSFER_SIZE_8:bpt = 8;break; + case SPI_TRANSFER_SIZE_32:bpt = 32;break; + } + + + unsigned num_bits = NUMBER_OF_TEST_BYTES*8; + + //First check a multi byte transfer + printf("Send initial settings\n"); + // printf("%u\n", num_bits); + + broadcast_settings(setup_strobe_port, setup_data_port, + SPI_MODE, mosi_enabled, miso_enabled, num_bits, KBPS, 2000); + + unsigned rx_byte_no = 0; + unsigned tx_byte_no = 0; + while(1){ + select { + case spi_i.master_requires_data() -> uint32_t r:{ + // printf("master_requires_data\n"); + if(tx_byte_no < NUMBER_OF_TEST_BYTES){ + switch(tt){ + case SPI_TRANSFER_SIZE_8: + r = tx_data[tx_byte_no]; + tx_byte_no++; + break; + case SPI_TRANSFER_SIZE_32: + r = (tx_data[tx_byte_no+3]<<0) + | (tx_data[tx_byte_no+2]<<8) + | (tx_data[tx_byte_no+1]<<16) + | (tx_data[tx_byte_no+0]<<24); + tx_byte_no+=4; + break; + } + } + if(!miso_enabled){ + printf("Error: master cannot require data when miso is not enabled\n"); + delay_after_print(); + _Exit(1); + } + break; + } + case spi_i.master_supplied_data(uint32_t datum, uint32_t valid_bits):{ + // printf("master_supplied_data\n"); + for(unsigned i=0; i> (valid_bits - 8))&0xff; + if(rx_data[rx_byte_no] != d){ + printf("Error: Expected %02x from master but got %02x for transfer of %d\n", + rx_data[rx_byte_no], d, num_bits); + delay_after_print(); + _Exit(1); + } + rx_byte_no++; + datum <<= 8; + } + + if(valid_bits < 8){ + datum <<= (8-valid_bits); + } else + datum >>= (valid_bits-8); + datum &= 0xff; + + if(valid_bits&0x7){ + uint32_t d =(rx_data[rx_byte_no]>>(8-(valid_bits&0x7)))<<(8-(valid_bits&0x7)); + if(datum != d){ + printf("Error: Expected %02x from master but got %02x for transfer of %d\n", + d, datum, num_bits); + delay_after_print(); + _Exit(1); + } + } + break; + } + + case spi_i.master_ends_transaction():{ + // printf("master_ends_transaction\n"); + //Then check all sub word transfers + if(num_bits == NUMBER_OF_TEST_BYTES*8){ + num_bits = 0; + } + if(num_bits == bpt){ + int r = request_response(setup_strobe_port, setup_resp_port); + if(r){ + printf("Error: Master Rx error\n"); + delay_after_print(); + _Exit(1); + } + spi_i.request_shutdown(); + break; + } + num_bits++; + + int r = request_response(setup_strobe_port, setup_resp_port); + + if(r){ + printf("Error: Master Rx error\n"); + delay_after_print(); + _Exit(1); + } + if(num_bits > bpt){ + printf("Error: Too many bits %d expecting %d\n", num_bits, bpt); + delay_after_print(); + _Exit(1); + } + + + broadcast_settings(setup_strobe_port, setup_data_port, + SPI_MODE, mosi_enabled, miso_enabled, num_bits, KBPS, 2000); + rx_byte_no = 0; + tx_byte_no = 0; + break; + } + + case spi_i.shutdown_complete(): + printf("Test completed\n"); + delay_after_print(); + return; + break; + } + } +} + +static void load(static const unsigned num_threads){ + switch(num_threads){ + case 0: return; + case 3: par {par(int i=0;i<3;i++) while(1);}break; + case 6: par {par(int i=0;i<6;i++) while(1);}break; + case 7: par {par(int i=0;i<7;i++) while(1);}break; + } +} + +#define MISO p_miso +#define MOSI_ENABLED 1 +#define MISO_ENABLED 1 +#define NUM_LOOPS 3 + +int main(){ + interface spi_slave_callback_if i; + par { +#if COMBINED == 1 + for(int n = 0; n < NUM_LOOPS; n++){ + [[combine]] + par { + spi_slave(i, p_sclk, p_mosi, MISO, p_ss, cb, SPI_MODE, TRANSFER_SIZE); + app(i, MOSI_ENABLED, MISO_ENABLED); + } + } +#else + // This will NOT combine + for(int n = 0; n < NUM_LOOPS; n++) + spi_slave(i, p_sclk, p_mosi, MISO, p_ss, cb, SPI_MODE, TRANSFER_SIZE); + for(int n = 0; n < NUM_LOOPS; n++) + app(i, MOSI_ENABLED, MISO_ENABLED); +#endif + load(BURNT_THREADS); + } + return 0; +} diff --git a/tests/spi_slave_shutdown/test_params.json b/tests/spi_slave_shutdown/test_params.json new file mode 100644 index 0000000..909d30f --- /dev/null +++ b/tests/spi_slave_shutdown/test_params.json @@ -0,0 +1,4 @@ +{ + "COMBINED": [0, 1], + "arch": ["xs2", "xs3"] +} diff --git a/tests/spi_slave_tester_common/common.h b/tests/spi_slave_tester_common/common.h new file mode 100644 index 0000000..0de6dc3 --- /dev/null +++ b/tests/spi_slave_tester_common/common.h @@ -0,0 +1,96 @@ +// Copyright 2015-2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. +#ifndef COMMON_SLAVE_H_ +#define COMMON_SLAVE_H_ + +#include + +static void set_mode_bits(spi_mode_t mode, unsigned &cpol, unsigned &cpha){ + switch(mode){ + case SPI_MODE_0:cpol = 0; cpha= 0; break; + case SPI_MODE_1:cpol = 0; cpha= 1; break; + case SPI_MODE_2:cpol = 1; cpha= 0; break; + case SPI_MODE_3:cpol = 1; cpha= 1; break; + } +} + +static void send_data_to_tester( + out port setup_strobe_port, + out port setup_data_port, + unsigned data){ + setup_data_port <: data; + sync(setup_data_port); + setup_strobe_port <: 1; // Twice to meet timing on harness + setup_strobe_port <: 1; + setup_strobe_port <: 0; + setup_strobe_port <: 0; +} + +static void broadcast_settings( + out port setup_strobe_port, + out port setup_data_port, + spi_mode_t mode, + int mosi_enabled, + int miso_enabled, + unsigned num_bits, + unsigned kbps, + unsigned initial_clock_delay // in ns + +){ + unsigned cpha, cpol; + + set_mode_bits(mode, cpol, cpha); + + setup_strobe_port <: 0; + setup_strobe_port <: 0; + + send_data_to_tester(setup_strobe_port, setup_data_port, cpol); + send_data_to_tester(setup_strobe_port, setup_data_port, cpha); + send_data_to_tester(setup_strobe_port, setup_data_port, miso_enabled); + send_data_to_tester(setup_strobe_port, setup_data_port, num_bits); + send_data_to_tester(setup_strobe_port, setup_data_port, kbps); + send_data_to_tester(setup_strobe_port, setup_data_port, initial_clock_delay); +} + +static int request_response( + out port setup_strobe_port, + in port setup_resp_port +){ + int r; + setup_resp_port when pinseq(1) :> r; // Wait for ACK from tester first + + setup_strobe_port <: 1; // Repeat to make sure we are not too fast + setup_strobe_port <: 1; + setup_strobe_port <: 1; + setup_strobe_port <: 1; + setup_strobe_port <: 0; + setup_strobe_port <: 0; + setup_strobe_port <: 0; + setup_strobe_port <: 0; + + setup_resp_port :> r; + + return r; + +} + +void delay_after_print(void){ + delay_microseconds(10); +} + +#define NUMBER_OF_TEST_BYTES 16 +#define NUMBER_OF_TEST_WORDS (NUMBER_OF_TEST_BYTES/sizeof(uint32_t)) + +static const uint8_t tx_data[NUMBER_OF_TEST_BYTES] = { + 0xaa, 0x02, 0x04, 0x08, 0x10, 0x20, 0x04, 0x80, + 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f +}; + +static const uint8_t rx_data[NUMBER_OF_TEST_BYTES] = { + 0xaa, 0xf7, 0xfb, 0xef, 0xdf, 0xbf, 0xfd, 0x7f, + 0x01, 0x08, 0x04, 0x10, 0x20, 0x04, 0x02, 0x80, +}; + + + +#endif /* COMMON_SLAVE_H_ */ diff --git a/tests/test_master_async_multi_client.py b/tests/test_master_async_multi_client.py new file mode 100644 index 0000000..b4ed10d --- /dev/null +++ b/tests/test_master_async_multi_client.py @@ -0,0 +1,52 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +from pathlib import Path +import Pyxsim +import pytest +from spi_master_checker import SPIMasterChecker +import os +from helpers import generate_tests_from_json, create_if_needed, print_expected_vs_output + + +appname = "spi_master_async_multi_client" +test_params_file = Path(__file__).parent / f"{appname}/test_params.json" + +def do_test(capfd, combined, burnt, mosi_enabled, arch, id): + id_string = f"{combined}_{burnt}_{mosi_enabled}_{arch}" + filepath = Path(__file__).resolve().parent + binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" + assert binary.exists() + + checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", + "tile[0]:XS1_PORT_1D", + "tile[0]:XS1_PORT_1A", + "tile[0]:XS1_PORT_1B", + "tile[0]:XS1_PORT_1E", + "tile[0]:XS1_PORT_16B") + + with open(filepath/f"expected/master_sync.expect") as exp: + expected = exp.read().splitlines() + + tester = Pyxsim.testers.ComparisonTester(expected, + regexp = False, + ordered = True) + + simargs = "--plugin LoopbackPort.dll '-port tile[0] XS1_PORT_1A 1 0 -port tile[0] XS1_PORT_1D 1 0'".split() + # simargs += "--vcd-tracing '-o trace.vcd -tile tile[0] -pads -ports -functions'".split() + + Pyxsim.run_on_simulator_( + binary, + simargs=simargs, + do_xe_prebuild = False, + simthreads = [checker], + capfd=capfd, + timeout=60) # In case of lock-up + + output = print_expected_vs_output(expected, capfd) + assert tester.run(output), output + + +@pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) +def test_master_async_multi_client(capfd, params, request): + do_test(capfd, *params, request.node.callspec.id) + diff --git a/tests/test_master_async_multi_device.py b/tests/test_master_async_multi_device.py new file mode 100644 index 0000000..b92e80b --- /dev/null +++ b/tests/test_master_async_multi_device.py @@ -0,0 +1,47 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +from pathlib import Path +import Pyxsim +import pytest +from spi_master_checker import SPIMasterChecker +import os +from helpers import generate_tests_from_json, create_if_needed, print_expected_vs_output + + +appname = "spi_master_async_multi_device" +test_params_file = Path(__file__).parent / f"{appname}/test_params.json" + +def do_test(capfd, combined, burnt, mosi_enabled, arch, id): + id_string = f"{combined}_{burnt}_{mosi_enabled}_{arch}" + filepath = Path(__file__).resolve().parent + binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" + assert binary.exists() + + checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", + "tile[0]:XS1_PORT_1D", + "tile[0]:XS1_PORT_1A", + "tile[0]:XS1_PORT_4A", # multiple bits of this port for SS + "tile[0]:XS1_PORT_1E", + "tile[0]:XS1_PORT_16B") + + with open(filepath/f"expected/master_sync.expect") as exp: + expected = exp.read().splitlines() + + tester = Pyxsim.testers.ComparisonTester(expected, + regexp = False, + ordered = True) + + Pyxsim.run_on_simulator_( + binary, + # simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -pads -functions'], + do_xe_prebuild = False, + simthreads = [checker], + capfd=capfd) + + output = print_expected_vs_output(expected, capfd) + assert tester.run(output), output + + +@pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) +def test_master_async_multi_device(capfd, params, request): + do_test(capfd, *params, request.node.callspec.id) diff --git a/tests/test_master_async_rx_tx.py b/tests/test_master_async_rx_tx.py new file mode 100644 index 0000000..b7f5fb8 --- /dev/null +++ b/tests/test_master_async_rx_tx.py @@ -0,0 +1,46 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +from pathlib import Path +import Pyxsim +import pytest +from spi_master_checker import SPIMasterChecker +from helpers import generate_tests_from_json, create_if_needed, print_expected_vs_output + +appname = "spi_master_async_rx_tx" +test_params_file = Path(__file__).parent / f"{appname}/test_params.json" + +def do_test(capfd, combined, burnt, mosi_enabled, transfer_width, speed_tests, spi_mode, arch, id): + id_string = f"{combined}_{burnt}_{mosi_enabled}_{speed_tests}_{transfer_width}_{spi_mode}_{arch}" + filepath = Path(__file__).resolve().parent + binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" + assert binary.exists() + + checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", + "tile[0]:XS1_PORT_1D", + "tile[0]:XS1_PORT_1A", + "tile[0]:XS1_PORT_1B", + "tile[0]:XS1_PORT_1E", + "tile[0]:XS1_PORT_16B") + + with open(filepath/f"expected/master_sync.expect") as exp: + expected = exp.read().splitlines() + + tester = Pyxsim.testers.ComparisonTester(expected, + regexp = False, + ordered = True) + + Pyxsim.run_on_simulator_( + binary, + # simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -ports -ports-detailed -pads -functions'], + do_xe_prebuild = False, + simthreads = [checker], + capfd=capfd) + + output = print_expected_vs_output(expected, capfd) + assert tester.run(output), output + + +@pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) +def test_master_async_rx_tx(capfd, params, request): + # print("***", params) + do_test(capfd, *params, request.node.callspec.id) diff --git a/tests/test_master_async_shutdown.py b/tests/test_master_async_shutdown.py new file mode 100644 index 0000000..bc39771 --- /dev/null +++ b/tests/test_master_async_shutdown.py @@ -0,0 +1,41 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +from pathlib import Path +import Pyxsim +import pytest +from spi_master_checker import SPIMasterChecker +from helpers import generate_tests_from_json, create_if_needed, print_expected_vs_output + +appname = "spi_master_async_shutdown" + +def do_test(capfd): + filepath = Path(__file__).resolve().parent + binary = filepath/f"{appname}/bin/{appname}.xe" + assert binary.exists() + + checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", + "tile[0]:XS1_PORT_1D", + "tile[0]:XS1_PORT_1A", + "tile[0]:XS1_PORT_1B", + "tile[0]:XS1_PORT_1E", + "tile[0]:XS1_PORT_16B") + + with open(filepath/f"expected/master_sync.expect") as exp: + expected = exp.read().splitlines() + + tester = Pyxsim.testers.ComparisonTester(expected, + regexp = False, + ordered = True) + + Pyxsim.run_on_simulator_( + binary, + # simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -ports -ports-detailed -functions'], + do_xe_prebuild = False, + simthreads = [checker], + capfd=capfd) + + output = print_expected_vs_output(expected, capfd) + assert tester.run(output), output + +def test_master_async_shutdown(capfd, request): + do_test(capfd) \ No newline at end of file diff --git a/tests/test_master_sync_benchmark.py b/tests/test_master_sync_benchmark.py new file mode 100644 index 0000000..5231cc8 --- /dev/null +++ b/tests/test_master_sync_benchmark.py @@ -0,0 +1,77 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. + +from pathlib import Path +import Pyxsim +import pytest +from spi_master_checker import SPIMasterChecker +from helpers import generate_tests_from_json, write_csv_row, create_if_needed, sort_csv_table + +appname = "spi_master_sync_benchmark" +test_params_file = Path(__file__).parent / f"{appname}/test_params.json" +test_results_file = Path.cwd()/f"logs/{appname}.txt" + +# This logs to a csv file since we don't want to do checking - it's just benchmark results +class Resultlogger(Pyxsim.testers.ComparisonTester): + def __init__(self, id): + # Turn ID back into a dict + self.result = dict(item.split('=') for item in id.split(', ')) + + def run(self, output): + ignore_list = ["SPI Master checker", "MISO delay setting"] + result_8b = None + result_32b = None + for line in output: print(line) + for line in reversed(output): + if any(skip in line for skip in ignore_list): + continue + if "PASS" in line: + width, speed = line.split(':')[1:3] + if int(width) == 8 and result_8b is None: + result_8b = speed + continue + if int(width) == 32 and result_32b is None: + result_32b = speed + self.result["result_8b"] = result_8b + self.result["result_32b"] = result_32b + assert result_8b and result_32b, "No timing results found" + + print(self.result) + write_csv_row(test_results_file, self.result) + +@pytest.fixture(scope="module", autouse=True) +def remove_test_results(): + create_if_needed(test_results_file.parent) + if test_results_file.exists(): + test_results_file.unlink() + yield + # Post test cleanup + sort_csv_table(test_results_file) + +def do_benchmark_sync(capfd, burnt, spi_mode, miso_mosi_enabled, cb_enabled, arch, id): + id_string = f"{burnt}_{spi_mode}_{miso_mosi_enabled}_{cb_enabled}_{arch}" + filepath = Path(__file__).resolve().parent + binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" + assert binary.exists(), f"Binary file {binary} not present - please pre-build" + + checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", + "tile[0]:XS1_PORT_1D", + "tile[0]:XS1_PORT_1A", + "tile[0]:XS1_PORT_1B", + "tile[0]:XS1_PORT_1E", + "tile[0]:XS1_PORT_16B") + + tester = Resultlogger(id) + + Pyxsim.run_on_simulator_( + binary, + tester = tester, + do_xe_prebuild = False, + simthreads = [checker], + # simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -clock-blocks -ports -ports-detailed -pads -functions'], + capfd=capfd) + + +@pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) +def test_master_sync_benchmark(capfd, params, request): + do_benchmark_sync(capfd, *params, request.node.callspec.id) \ No newline at end of file diff --git a/tests/test_master_sync_clock_port_sharing.py b/tests/test_master_sync_clock_port_sharing.py new file mode 100644 index 0000000..c965c85 --- /dev/null +++ b/tests/test_master_sync_clock_port_sharing.py @@ -0,0 +1,47 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +from pathlib import Path +import Pyxsim +import pytest +from spi_master_checker import SPIMasterChecker +from helpers import print_expected_vs_output + + +appname = "spi_master_sync_clock_port_sharing" + +def do_test(capfd, combined, id): + id_string = f"{combined}" + filepath = Path(__file__).resolve().parent + binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" + assert binary.exists() + + pytest.xfail("Changing clock port clockblock is expected to affect the next transfer") + + checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", + "tile[0]:XS1_PORT_1D", + "tile[0]:XS1_PORT_1A", + "tile[0]:XS1_PORT_1B", + "tile[0]:XS1_PORT_1E", + "tile[0]:XS1_PORT_16B") + + with open(filepath/f"expected/master_sync.expect") as exp: + expected = exp.read().splitlines() + + tester = Pyxsim.testers.ComparisonTester(expected, + regexp = False, + ordered = True) + + Pyxsim.run_on_simulator_( + binary, + #simargs=['--vcd-tracing', '-o ./spi_master_sync_multi_device/trace.vcd -tile tile[0] -pads -functions'], + do_xe_prebuild = False, + simthreads = [checker], + capfd=capfd) + + output = print_expected_vs_output(expected, capfd) + assert tester.run(output), output + + +@pytest.mark.parametrize("combined", ["COMBINED", "NOT_COMBINED"], ids=["COMBINED=1", "COMBINED=0"]) +def test_master_sync_clock_port_sharing(capfd, combined, request): + do_test(capfd, combined, request.node.callspec.id) diff --git a/tests/test_master_sync_multi_client.py b/tests/test_master_sync_multi_client.py new file mode 100644 index 0000000..a3dcaf5 --- /dev/null +++ b/tests/test_master_sync_multi_client.py @@ -0,0 +1,47 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +from pathlib import Path +import Pyxsim +import pytest +from spi_master_checker import SPIMasterChecker +from helpers import generate_tests_from_json, create_if_needed, print_expected_vs_output + + +appname = "spi_master_sync_multi_client" +test_params_file = Path(__file__).parent / f"{appname}/test_params.json" + +def do_test(capfd, burnt, cb_enabled, miso_mosi_enabled, arch, id): + id_string = f"{burnt}_{cb_enabled}_{miso_mosi_enabled}_{arch}" + filepath = Path(__file__).resolve().parent + binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" + assert binary.exists() + + checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", + "tile[0]:XS1_PORT_1D", + "tile[0]:XS1_PORT_1A", + "tile[0]:XS1_PORT_1B", + "tile[0]:XS1_PORT_1E", + "tile[0]:XS1_PORT_16B") + + with open(filepath/f"expected/master_sync.expect") as exp: + expected = exp.read().splitlines() + + tester = Pyxsim.testers.ComparisonTester(expected, + regexp = False, + ordered = True) + + Pyxsim.run_on_simulator_( + binary, + # simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -ports -ports-detailed -pads -functions'], + do_xe_prebuild = False, + simthreads = [checker], + capfd=capfd, + timeout=30) + + output = print_expected_vs_output(expected, capfd) + assert tester.run(output), output + + +@pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) +def test_master_sync_multi_client(capfd, params, request): + do_test(capfd, *params, request.node.callspec.id) diff --git a/tests/test_master_sync_multi_device.py b/tests/test_master_sync_multi_device.py new file mode 100644 index 0000000..5d222f6 --- /dev/null +++ b/tests/test_master_sync_multi_device.py @@ -0,0 +1,50 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +from pathlib import Path +import Pyxsim +import pytest +from spi_master_checker import SPIMasterChecker +from helpers import generate_tests_from_json, create_if_needed, print_expected_vs_output +from itertools import zip_longest + + +appname = "spi_master_sync_multi_device" +test_params_file = Path(__file__).parent / f"{appname}/test_params.json" + +def do_test(capfd, burnt, cb_enabled, miso_mosi_enabled, arch, id): + id_string = f"{burnt}_{cb_enabled}_{miso_mosi_enabled}_{arch}" + filepath = Path(__file__).resolve().parent + binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" + assert binary.exists() + + checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", + "tile[0]:XS1_PORT_1D", + "tile[0]:XS1_PORT_1A", + "tile[0]:XS1_PORT_4A", # multiple bits of this port for SS + "tile[0]:XS1_PORT_1E", + "tile[0]:XS1_PORT_16B") + + with open(filepath/f"expected/master_sync.expect") as exp: + expected = exp.read().splitlines() + + tester = Pyxsim.testers.ComparisonTester(expected, + regexp = False, + ordered = True) + + simargs = ['--vcd-tracing', '-o trace.vcd -tile tile[0] -pads -ports -ports-detailed -functions -instructions -cycles -cores'] + simargs = [] # Disable VCD tracing + + Pyxsim.run_on_simulator_( + binary, + simargs=simargs, + do_xe_prebuild = False, + simthreads = [checker], + capfd=capfd) + + output = print_expected_vs_output(expected, capfd) + assert tester.run(output), output + + +@pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) +def test_master_sync_multi_device(capfd, params, request): + do_test(capfd, *params, request.node.callspec.id) diff --git a/tests/test_master_sync_rx_tx.py b/tests/test_master_sync_rx_tx.py new file mode 100644 index 0000000..a65902d --- /dev/null +++ b/tests/test_master_sync_rx_tx.py @@ -0,0 +1,46 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +from pathlib import Path +import Pyxsim +import pytest +from spi_master_checker import SPIMasterChecker +from helpers import generate_tests_from_json, create_if_needed, print_expected_vs_output +from itertools import zip_longest + +appname = "spi_master_sync_rx_tx" +test_params_file = Path(__file__).parent / f"{appname}/test_params.json" + +def do_test(capfd, burnt, spi_mode, miso_mosi_enabled, cb_enabled, arch, id): + id_string = f"{burnt}_{spi_mode}_{miso_mosi_enabled}_{cb_enabled}_{arch}" + filepath = Path(__file__).resolve().parent + binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" + assert binary.exists() + + checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", + "tile[0]:XS1_PORT_1D", + "tile[0]:XS1_PORT_1A", + "tile[0]:XS1_PORT_1B", + "tile[0]:XS1_PORT_1E", + "tile[0]:XS1_PORT_16B") + + with open(filepath/f"expected/master_sync.expect") as exp: + expected = exp.read().splitlines() + + tester = Pyxsim.testers.ComparisonTester(expected, + regexp = False, + ordered = True) + + Pyxsim.run_on_simulator_( + binary, + # simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -ports -ports-detailed -pads -functions'], + do_xe_prebuild = False, + simthreads = [checker], + capfd=capfd) + + output = print_expected_vs_output(expected, capfd) + assert tester.run(output), output + +@pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) +def test_master_sync_rx_tx(capfd, params, request): + # print("********", params) + do_test(capfd, *params, request.node.callspec.id) \ No newline at end of file diff --git a/tests/test_master_sync_shutdown.py b/tests/test_master_sync_shutdown.py new file mode 100644 index 0000000..35cd7e7 --- /dev/null +++ b/tests/test_master_sync_shutdown.py @@ -0,0 +1,46 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +from pathlib import Path +import Pyxsim +import pytest +from spi_master_checker import SPIMasterChecker +from helpers import generate_tests_from_json, create_if_needed, print_expected_vs_output + +appname = "spi_master_sync_shutdown" +test_params_file = Path(__file__).parent / f"{appname}/test_params.json" + +def do_test(distributed, cb_enabled, arch, capfd): + filepath = Path(__file__).resolve().parent + id_string = f"{distributed}_{cb_enabled}_{arch}" + app_build = "distributed" if distributed else "own_thread" + binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" + assert binary.exists() + + checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", + "tile[0]:XS1_PORT_1D", + "tile[0]:XS1_PORT_1A", + "tile[0]:XS1_PORT_1B", + "tile[0]:XS1_PORT_1E", + "tile[0]:XS1_PORT_16B") + + with open(filepath/f"expected/master_sync.expect") as exp: + expected = exp.read().splitlines() + + tester = Pyxsim.testers.ComparisonTester(expected, + regexp = False, + ordered = True) + + Pyxsim.run_on_simulator_( + binary, + # simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -ports -ports-detailed -pads -functions'], + do_xe_prebuild = False, + simthreads = [checker], + capfd=capfd) + + output = print_expected_vs_output(expected, capfd) + assert tester.run(output), output + + +@pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) +def test_master_sync_shutdown(capfd, params, request): + do_test(*params, capfd) \ No newline at end of file diff --git a/tests/test_slave_benchmark.py b/tests/test_slave_benchmark.py new file mode 100644 index 0000000..b7c8fa0 --- /dev/null +++ b/tests/test_slave_benchmark.py @@ -0,0 +1,78 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +from pathlib import Path +import Pyxsim +import pytest +from spi_slave_checker import SPISlaveChecker +from helpers import generate_tests_from_json, write_csv_row, create_if_needed, sort_csv_table + +appname = "spi_slave_benchmark" +test_params_file = Path(__file__).parent / f"{appname}/test_params.json" +test_results_file = Path.cwd()/f"logs/{appname}.txt" + +# This logs to a csv file since we don't want to do checking - it's just benchmark results +class Resultlogger(Pyxsim.testers.ComparisonTester): + def __init__(self, id): + # Turn ID back into a dict + self.result = dict(item.split('=') for item in id.split(', ')) + + + def run(self, output): + # DUT outputs RESULT: SPI_MODE, TRANSFER_SIZE, BURNT_THREADS, miso_enabled, mosi_enabled, cd, kbps + + for line in output: + print(line) + ignore_list = ["SPI Slave checker", "Drive bit"] + result_clock_delay_ns = None + result_kbps = None + for line in output: + if any(skip in line for skip in ignore_list): + continue + if "RESULT:" in line: + result_kbps = line.split(' ')[-1] + result_clock_delay_ns = line.split(' ')[-2] + self.result["CLK_DLY_NS"] = result_clock_delay_ns + self.result["KBPS"] = result_kbps + + assert result_clock_delay_ns and result_kbps, "No timing results found" + + write_csv_row(test_results_file, self.result) + +@pytest.fixture(scope="module", autouse=True) +def remove_test_results(): + create_if_needed(test_results_file.parent) + if test_results_file.exists(): + test_results_file.unlink() + yield + # Post test cleanup + sort_csv_table(test_results_file) + +def do_benchmark_slave(capfd, combined, burnt, miso_enabled, spi_mode, transfer_size, arch, id): + id_string = f"{combined}_{burnt}_{miso_enabled}_{spi_mode}_{transfer_size}_{arch}" + filepath = Path(__file__).resolve().parent + binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" + assert binary.exists() + + checker = SPISlaveChecker("tile[0]:XS1_PORT_1C", + "tile[0]:XS1_PORT_1D", + "tile[0]:XS1_PORT_1A", + "tile[0]:XS1_PORT_1B", + "tile[0]:XS1_PORT_1E", + "tile[0]:XS1_PORT_16B", + "tile[0]:XS1_PORT_1F") + + tester = Resultlogger(id) + + Pyxsim.run_on_simulator_( + binary, + tester = tester, + # simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -ports -pads -functions'], + do_xe_prebuild = False, + simthreads = [checker], + capfd=capfd + ) + +@pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) +def test_slave_benchmark(capfd, params, request): + do_benchmark_slave(capfd, *params, request.node.callspec.id) + diff --git a/tests/test_slave_rx_tx.py b/tests/test_slave_rx_tx.py new file mode 100644 index 0000000..570fc14 --- /dev/null +++ b/tests/test_slave_rx_tx.py @@ -0,0 +1,47 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +from pathlib import Path +import Pyxsim +import pytest +from spi_slave_checker import SPISlaveChecker +from helpers import generate_tests_from_json, create_if_needed, print_expected_vs_output + +appname = "spi_slave_rx_tx" +test_params_file = Path(__file__).parent / f"{appname}/test_params.json" + +def do_slave_rx_tx(capfd, combined, burnt, miso_enabled, spi_mode, transfer_size, arch, id): + id_string = f"{combined}_{burnt}_{miso_enabled}_{spi_mode}_{transfer_size}_{arch}" + filepath = Path(__file__).resolve().parent + binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" + assert binary.exists() + + checker = SPISlaveChecker("tile[0]:XS1_PORT_1C", + "tile[0]:XS1_PORT_1D", + "tile[0]:XS1_PORT_1A", + "tile[0]:XS1_PORT_1B", + "tile[0]:XS1_PORT_1E", + "tile[0]:XS1_PORT_16B", + "tile[0]:XS1_PORT_1F") + + with open(filepath/f"expected/slave.expect") as exp: + expected = exp.read().splitlines() + expected = expected[:3 + transfer_size] + expected[-1:] + + tester = Pyxsim.testers.ComparisonTester(expected, + regexp = True, + ordered = True) + + Pyxsim.run_on_simulator_( + binary, + # simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -ports -pads -functions'], + do_xe_prebuild = False, + simthreads = [checker], + capfd=capfd + ) + + output = print_expected_vs_output(expected, capfd) + assert tester.run(output) + +@pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) +def test_slave_rx_tx(capfd, params, request): + do_slave_rx_tx(capfd, *params, request.node.callspec.id) diff --git a/tests/test_slave_shutdown.py b/tests/test_slave_shutdown.py new file mode 100644 index 0000000..1eecb44 --- /dev/null +++ b/tests/test_slave_shutdown.py @@ -0,0 +1,51 @@ +# Copyright 2015-2025 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +from pathlib import Path +import Pyxsim +import pytest +from spi_slave_checker import SPISlaveChecker +from helpers import generate_tests_from_json, create_if_needed, print_expected_vs_output + +appname = "spi_slave_shutdown" +test_params_file = Path(__file__).parent / f"{appname}/test_params.json" + +def do_test(combined, arch, capfd): + filepath = Path(__file__).resolve().parent + id_string = f"{combined}_{arch}" + binary = filepath/f"{appname}/bin/{id_string}/{appname}_{id_string}.xe" + assert binary.exists() + + checker = SPISlaveChecker("tile[0]:XS1_PORT_1C", + "tile[0]:XS1_PORT_1D", + "tile[0]:XS1_PORT_1A", + "tile[0]:XS1_PORT_1B", + "tile[0]:XS1_PORT_1E", + "tile[0]:XS1_PORT_16B", + "tile[0]:XS1_PORT_1F") + + with open(filepath/f"expected/slave.expect") as exp: + expected = exp.read().splitlines() + transfer_size = 8 + NUM_LOOPS = 3 # See spi_slave_shutdown.xc for equivalent define. Must match + expected = expected[:3 + transfer_size] + expected[-1:] + expected = expected + expected[1:] * (NUM_LOOPS - 1) # We don't want SPI Slave checker started after the first time + + tester = Pyxsim.testers.ComparisonTester(expected, + regexp = True, + ordered = True) + + Pyxsim.run_on_simulator_( + binary, + # simargs=['--vcd-tracing', '-o ./trace.vcd -tile tile[0] -ports -ports-detailed -pads -functions'], + do_xe_prebuild = False, + simthreads = [checker], + capfd=capfd, + timeout=60) + + output = print_expected_vs_output(expected, capfd) + assert tester.run(output), output + + +@pytest.mark.parametrize("params", generate_tests_from_json(test_params_file)[0], ids=generate_tests_from_json(test_params_file)[1]) +def test_slave_shutdown(capfd, params, request): + do_test(*params, capfd) \ No newline at end of file