diff --git a/.gitlab-ci/bare-metal/poe-powered.sh b/.gitlab-ci/bare-metal/poe-powered.sh index 399384f9cd8..101fa606310 100755 --- a/.gitlab-ci/bare-metal/poe-powered.sh +++ b/.gitlab-ci/bare-metal/poe-powered.sh @@ -70,11 +70,6 @@ if [ -z "$BM_CMDLINE" ]; then exit 1 fi -if [ -z "$BM_BOOTCONFIG" ]; then - echo "Must set BM_BOOTCONFIG to your board's required boot configuration arguments" - exit 1 -fi - set -ex date +'%F %T' @@ -154,8 +149,10 @@ date +'%F %T' echo "$BM_CMDLINE" > /tftp/cmdline.txt -# Add some required options in config.txt -printf "$BM_BOOTCONFIG" >> /tftp/config.txt +# Add some options in config.txt, if defined +if [ -n "$BM_BOOTCONFIG" ]; then + printf "$BM_BOOTCONFIG" >> /tftp/config.txt +fi set +e ATTEMPTS=3 diff --git a/.gitlab-ci/common/init-stage1.sh b/.gitlab-ci/common/init-stage1.sh index 41f1112d43d..92222a5d4c7 100755 --- a/.gitlab-ci/common/init-stage1.sh +++ b/.gitlab-ci/common/init-stage1.sh @@ -7,10 +7,10 @@ set -ex cd / -mount -t proc none /proc -mount -t sysfs none /sys +findmnt --mountpoint /proc || mount -t proc none /proc +findmnt --mountpoint /sys || mount -t sysfs none /sys mount -t debugfs none /sys/kernel/debug -mount -t devtmpfs none /dev || echo possibly already mounted +findmnt --mountpoint /dev || mount -t devtmpfs none /dev mkdir -p /dev/pts mount -t devpts devpts /dev/pts mkdir /dev/shm diff --git a/.gitlab-ci/common/init-stage2.sh b/.gitlab-ci/common/init-stage2.sh index bc7717322f0..7440893a667 100755 --- a/.gitlab-ci/common/init-stage2.sh +++ b/.gitlab-ci/common/init-stage2.sh @@ -216,7 +216,11 @@ fi [ ${EXIT_CODE} -eq 0 ] && RESULT=pass || RESULT=fail set +x -echo "hwci: mesa: $RESULT" -# Sleep a bit to avoid kernel dump message interleave from LAVA ENDTC signal -sleep 1 + +# Print the final result; both bare-metal and LAVA look for this string to get +# the result of our run, so try really hard to get it out rather than losing +# the run. The device gets shut down right at this point, and a630 seems to +# enjoy corrupting the last line of serial output before shutdown. +for _ in $(seq 0 3); do echo "hwci: mesa: $RESULT"; sleep 1; echo; done + exit $EXIT_CODE diff --git a/.gitlab-ci/container/build-kdl.sh b/.gitlab-ci/container/build-kdl.sh index 5f00cfc6c60..e45127be542 100755 --- a/.gitlab-ci/container/build-kdl.sh +++ b/.gitlab-ci/container/build-kdl.sh @@ -5,12 +5,12 @@ set -ex KDL_REVISION="5056f71b100a68b72b285c6fc845a66a2ed25985" -git clone \ - https://gitlab.freedesktop.org/gfx-ci/ci-kdl.git \ - --depth 1 \ - ci-kdl.git +mkdir ci-kdl.git pushd ci-kdl.git -git checkout ${KDL_REVISION} +git init +git remote add origin https://gitlab.freedesktop.org/gfx-ci/ci-kdl.git +git fetch --depth 1 origin ${KDL_REVISION} +git checkout FETCH_HEAD popd python3 -m venv ci-kdl.venv diff --git a/.gitlab-ci/test-source-dep.yml b/.gitlab-ci/test-source-dep.yml index 4320fd8c175..ba4d23802a6 100644 --- a/.gitlab-ci/test-source-dep.yml +++ b/.gitlab-ci/test-source-dep.yml @@ -222,14 +222,23 @@ .lint-rustfmt-rules: rules: - !reference [.core-rules, rules] - - changes: + # in merge pipeline, formatting checks are not allowed to fail + - if: $GITLAB_USER_LOGIN == "marge-bot" && $CI_PIPELINE_SOURCE == "merge_request_event" + changes: &rust_file_list - src/**/*.rs when: on_success + allow_failure: false + # in other pipelines, formatting checks are allowed to fail + - changes: *rust_file_list + when: on_success + allow_failure: true .lint-clang-format-rules: rules: - !reference [.core-rules, rules] - - changes: + # in merge pipeline, formatting checks are not allowed to fail + - if: $GITLAB_USER_LOGIN == "marge-bot" && $CI_PIPELINE_SOURCE == "merge_request_event" + changes: &clang_format_file_list - .clang-format - .clang-format-include - .clang-format-ignore @@ -240,3 +249,8 @@ - src/amd/vulkan/**/* - src/amd/compiler/**/* when: on_success + allow_failure: false + # in other pipelines, formatting checks are allowed to fail + - changes: *clang_format_file_list + when: on_success + allow_failure: true diff --git a/.gitlab-ci/test/gitlab-ci.yml b/.gitlab-ci/test/gitlab-ci.yml index 7abdf8b6ebf..6b1aa0b81bf 100644 --- a/.gitlab-ci/test/gitlab-ci.yml +++ b/.gitlab-ci/test/gitlab-ci.yml @@ -23,11 +23,6 @@ stage: lint extends: - .use-debian/x86_64_build - rules: - # in merge pipeline, don't touch the default settings - - if: $GITLAB_USER_LOGIN == "marge-bot" && $CI_COMMIT_BRANCH == null - # in other pipelines, formatting checks are allowed to fail - - allow_failure: true variables: GIT_STRATEGY: fetch timeout: 10m @@ -385,7 +380,6 @@ clang-format: echo "export SCRIPTS_DIR=./install" >> ${JOB_FOLDER}/set-job-env-vars.sh echo "Variables passed through:" cat ${JOB_FOLDER}/set-job-env-vars.sh - echo "export CI_JOB_JWT=${CI_JOB_JWT}" >> ${JOB_FOLDER}/set-job-env-vars.sh set -x # Copy the mesa install tarball to the job folder, for later extraction diff --git a/.pick_status.json b/.pick_status.json new file mode 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"notes": null + } +] \ No newline at end of file diff --git a/VERSION b/VERSION index 67ca207feec..7090d1905fd 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -23.3.0-devel +23.3.3 diff --git a/android/Android.mk b/android/Android.mk index 24110e25d68..930d4cb61ad 100644 --- a/android/Android.mk +++ b/android/Android.mk @@ -41,8 +41,8 @@ include $(CLEAR_VARS) LOCAL_SHARED_LIBRARIES := libc libdl libdrm libm liblog libcutils libz libc++ libnativewindow libsync libhardware LOCAL_STATIC_LIBRARIES := libexpat libarect libelf -LOCAL_HEADER_LIBRARIES := libnativebase_headers hwvulkan_headers libbacktrace_headers -MESON_GEN_PKGCONFIGS := backtrace cutils expat hardware libdrm:$(LIBDRM_VERSION) nativewindow sync zlib:1.2.11 libelf +LOCAL_HEADER_LIBRARIES := libnativebase_headers hwvulkan_headers +MESON_GEN_PKGCONFIGS := cutils expat hardware libdrm:$(LIBDRM_VERSION) nativewindow sync zlib:1.2.11 libelf LOCAL_CFLAGS += $(BOARD_MESA3D_CFLAGS) ifneq ($(filter swrast,$(BOARD_MESA3D_GALLIUM_DRIVERS) $(BOARD_MESA3D_VULKAN_DRIVERS)),) @@ -88,8 +88,16 @@ MESON_GEN_PKGCONFIGS += DirectX-Headers endif ifneq ($(MESON_GEN_LLVM_STUB),) -MESON_LLVM_VERSION := 12.0.0 -LOCAL_SHARED_LIBRARIES += libLLVM12 +LLVM_VERSION_MAJOR = $(shell cat external/llvm-project/llvm/CMakeLists.txt | grep -o "LLVM_VERSION_MAJOR\s*\w*" | /bin/grep -o "[[:digit:]]*" | head -1) +MESON_LLVM_VERSION := $(LLVM_VERSION_MAJOR).0.0 +LOCAL_SHARED_LIBRARIES += libLLVM$(LLVM_VERSION_MAJOR) +endif + +ifneq ($(strip $(BOARD_MESA3D_GALLIUM_VA)),) +LIBVA_MAJOR_VERSION = $(shell cat hardware/intel/common/libva/meson.build | grep -o 'va_api_major_version = [0-9]\+' | grep -o '[0-9]*') +LIBVA_MINOR_VERSION = $(shell cat hardware/intel/common/libva/meson.build | grep -o 'va_api_minor_version = [0-9]\+' | grep -o '[0-9]*') +LOCAL_SHARED_LIBRARIES += libva +MESON_GEN_PKGCONFIGS += libva:$(LIBVA_MAJOR_VERSION).$(LIBVA_MINOR_VERSION) endif ifeq ($(shell test $(PLATFORM_SDK_VERSION) -ge 30; echo $$?), 0) @@ -180,6 +188,10 @@ endif $(foreach driver,$(BOARD_MESA3D_VULKAN_DRIVERS), \ $(eval $(call mesa3d-lib,vulkan.$(MESA_VK_LIB_SUFFIX_$(driver)),.so.0,hw,MESA3D_VULKAN_$(driver)_BIN))) +ifneq ($(strip $(BOARD_MESA3D_GALLIUM_VA)),) +$(eval $(call mesa3d-lib,libgallium_drv_video,.so.0,dri,MESA3D_GALLIUM_DRV_VIDEO_BIN)) +endif + ifneq ($(filter true, $(BOARD_MESA3D_BUILD_LIBGBM)),) # Modules 'libgbm', produces '/vendor/lib{64}/libgbm.so' $(eval $(call mesa3d-lib,$(MESA_LIBGBM_NAME),.so.1,,MESA3D_LIBGBM_BIN,$(MESA3D_TOP)/src/gbm/main)) diff --git a/android/mesa3d_cross.mk b/android/mesa3d_cross.mk index bfee1eadb2d..32ee987bc9a 100644 --- a/android/mesa3d_cross.mk +++ b/android/mesa3d_cross.mk @@ -65,6 +65,7 @@ MESON_GEN_FILES_TARGET := $(MESON_GEN_DIR)/.timestamp MESA3D_GALLIUM_DRI_DIR := $(MESON_OUT_DIR)/install/usr/local/lib/dri $(M_TARGET_PREFIX)MESA3D_GALLIUM_DRI_BIN := $(MESON_OUT_DIR)/install/usr/local/lib/libgallium_dri.so +$(M_TARGET_PREFIX)MESA3D_GALLIUM_DRV_VIDEO_BIN := $(MESON_OUT_DIR)/install/usr/local/lib/libgallium_drv_video.so $(M_TARGET_PREFIX)MESA3D_LIBEGL_BIN := $(MESON_OUT_DIR)/install/usr/local/lib/libEGL.so.1.0.0 $(M_TARGET_PREFIX)MESA3D_LIBGLESV1_BIN := $(MESON_OUT_DIR)/install/usr/local/lib/libGLESv1_CM.so.1.1.0 $(M_TARGET_PREFIX)MESA3D_LIBGLESV2_BIN := $(MESON_OUT_DIR)/install/usr/local/lib/libGLESv2.so.2.0.0 @@ -86,12 +87,17 @@ MESON_GEN_NINJA := \ -Dplatforms=android \ -Dplatform-sdk-version=$(PLATFORM_SDK_VERSION) \ -Dgallium-drivers=$(subst $(space),$(comma),$(BOARD_MESA3D_GALLIUM_DRIVERS)) \ + -Dgallium-va=$(if $(BOARD_MESA3D_GALLIUM_VA),enabled,disabled) \ + -Dvideo-codecs=$(BOARD_MESA3D_VIDEO_CODES) \ -Dvulkan-drivers=$(subst $(space),$(comma),$(subst radeon,amd,$(BOARD_MESA3D_VULKAN_DRIVERS))) \ -Dgbm=enabled \ -Degl=$(if $(BOARD_MESA3D_GALLIUM_DRIVERS),enabled,disabled) \ -Dllvm=$(if $(MESON_GEN_LLVM_STUB),enabled,disabled) \ -Dcpp_rtti=false \ -Dlmsensors=disabled \ + -Dandroid-libbacktrace=disabled \ + -Dallow-kcmp=enabled \ + -Dintel-xe-kmd=enabled \ MESON_BUILD := PATH=/usr/bin:/bin:/sbin:$$PATH ninja -C $(MESON_OUT_DIR)/build @@ -203,7 +209,9 @@ define m-c-flags endef define filter-c-flags - $(filter-out -std=gnu++17 -std=gnu++14 -std=gnu99 -fno-rtti, \ + $(filter-out -std=gnu++17 -std=gnu++14 -std=gnu99 -fno-rtti \ + -enable-trivial-auto-var-init-zero-knowing-it-will-be-removed-from-clang \ + -ftrivial-auto-var-init=zero, $(patsubst -W%,, $1)) endef @@ -281,15 +289,20 @@ endif touch $@ MESON_COPY_LIBGALLIUM := \ - cp `ls -1 $(MESA3D_GALLIUM_DRI_DIR)/* | head -1` $($(M_TARGET_PREFIX)MESA3D_GALLIUM_DRI_BIN) + cp `find $(MESA3D_GALLIUM_DRI_DIR) -name \*_dri.so | head -1` $($(M_TARGET_PREFIX)MESA3D_GALLIUM_DRI_BIN) + +MESON_COPY_LIBGALLIUM_VIDEO := \ + cp `find $(MESA3D_GALLIUM_DRI_DIR) -name \*_drv_video.so | head -1` $($(M_TARGET_PREFIX)MESA3D_GALLIUM_DRV_VIDEO_BIN) $(MESON_OUT_DIR)/install/.install.timestamp: MESON_COPY_LIBGALLIUM:=$(MESON_COPY_LIBGALLIUM) $(MESON_OUT_DIR)/install/.install.timestamp: MESON_BUILD:=$(MESON_BUILD) +$(MESON_OUT_DIR)/install/.install.timestamp: MESON_COPY_LIBGALLIUM_VIDEO:=$(MESON_COPY_LIBGALLIUM_VIDEO) $(MESON_OUT_DIR)/install/.install.timestamp: $(MESON_OUT_DIR)/.build.timestamp rm -rf $(dir $@) mkdir -p $(dir $@) DESTDIR=$(call relative-to-absolute,$(dir $@)) $(MESON_BUILD) install $(if $(BOARD_MESA3D_GALLIUM_DRIVERS),$(MESON_COPY_LIBGALLIUM)) + $(if $(BOARD_MESA3D_GALLIUM_VA),$(MESON_COPY_LIBGALLIUM_VIDEO)) touch $@ $($(M_TARGET_PREFIX)MESA3D_LIBGBM_BIN) $(MESA3D_GLES_BINS): $(MESON_OUT_DIR)/install/.install.timestamp @@ -310,8 +323,13 @@ $($(M_TARGET_PREFIX)TARGET_OUT_VENDOR_SHARED_LIBRARIES)/dri/.symlinks.timestamp: # Create Symlinks mkdir -p $(dir $@) ls -1 $(MESA3D_GALLIUM_DRI_DIR)/ | PATH=/usr/bin:$$PATH xargs -I{} ln -s -f libgallium_dri.so $(dir $@)/{} + ls -1 $(MESA3D_GALLIUM_DRI_DIR)/ | grep video | PATH=/usr/bin:$$PATH xargs -I{} ln -s -f libgallium_drv_video.so $(dir $@)/{} touch $@ $($(M_TARGET_PREFIX)MESA3D_GALLIUM_DRI_BIN): $(TARGET_OUT_VENDOR)/$(MESA3D_LIB_DIR)/dri/.symlinks.timestamp echo "Build $@" touch $@ + +$($(M_TARGET_PREFIX)MESA3D_GALLIUM_DRV_VIDEO_BIN): $(TARGET_OUT_VENDOR)/$(MESA3D_LIB_DIR)/dri/.symlinks.timestamp + echo "Build $@" + touch $@ \ No newline at end of file diff --git a/bin/gen_release_notes.py b/bin/gen_release_notes.py index 5520e55f17c..1ad60a30680 100755 --- a/bin/gen_release_notes.py +++ b/bin/gen_release_notes.py @@ -325,7 +325,7 @@ def update_release_notes_index(version: str) -> None: first_list = False new_relnotes.append(f'- :doc:`{version} release notes `\n') if (not first_list and second_list and - re.match(' \d+.\d+(.\d+)? ', line)): + re.match(r' \d+.\d+(.\d+)? ', line)): second_list = False new_relnotes.append(f' {version} \n') new_relnotes.append(line) diff --git a/docs/envvars.rst b/docs/envvars.rst index 4be7a1fe1f2..7c17d9ba962 100644 --- a/docs/envvars.rst +++ b/docs/envvars.rst @@ -41,22 +41,6 @@ LibGL environment variables Core Mesa environment variables ------------------------------- -.. envvar:: MESA_NO_ASM - - if set, disables all assembly language optimizations - -.. envvar:: MESA_NO_MMX - - if set, disables Intel MMX optimizations - -.. envvar:: MESA_NO_3DNOW - - if set, disables AMD 3DNow! optimizations - -.. envvar:: MESA_NO_SSE - - if set, disables Intel SSE optimizations - .. envvar:: MESA_NO_ERROR if set to 1, error checking is disabled as per :ext:`GL_KHR_no_error`. @@ -1342,6 +1326,8 @@ RADV driver environment variables enable wave64 for ray tracing shaders (GFX10+) ``video_decode`` enable experimental video decoding support + ``gsfastlaunch2`` + use GS_FAST_LAUNCH=2 for Mesh shaders (GFX11+) .. envvar:: RADV_TEX_ANISO @@ -1354,7 +1340,7 @@ RADV driver environment variables .. envvar:: RADV_THREAD_TRACE_CACHE_COUNTERS - enable/disable SQTT/RGP cache counters on GFX10+ (disabled by default) + enable/disable SQTT/RGP cache counters on GFX10+ (enabled by default) .. envvar:: RADV_THREAD_TRACE_INSTRUCTION_TIMING diff --git a/docs/relnotes.rst b/docs/relnotes.rst index 3c772398c25..0cc9d04d59b 100644 --- a/docs/relnotes.rst +++ b/docs/relnotes.rst @@ -3,6 +3,10 @@ Release Notes The release notes summarize what's new or changed in each Mesa release. +- :doc:`23.3.3 release notes ` +- :doc:`23.3.2 release notes ` +- :doc:`23.3.1 release notes ` +- :doc:`23.3.0 release notes ` - :doc:`23.1.9 release notes ` - :doc:`23.1.8 release notes ` - :doc:`23.1.7 release notes ` @@ -402,6 +406,10 @@ The release notes summarize what's new or changed in each Mesa release. :maxdepth: 1 :hidden: + 23.3.3 + 23.3.2 + 23.3.1 + 23.3.0 23.1.9 23.1.8 23.1.7 diff --git a/docs/relnotes/23.3.0.rst b/docs/relnotes/23.3.0.rst new file mode 100644 index 00000000000..f487ce19044 --- /dev/null +++ b/docs/relnotes/23.3.0.rst @@ -0,0 +1,6334 @@ +Mesa 23.3.0 Release Notes / 2023-11-29 +====================================== + +Mesa 23.3.0 is a new development release. People who are concerned +with stability and reliability should stick with a previous release or +wait for Mesa 23.3.1. + +Mesa 23.3.0 implements the OpenGL 4.6 API, but the version reported by +glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) / +glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used. +Some drivers don't support all the features required in OpenGL 4.6. OpenGL +4.6 is **only** available if requested at context creation. +Compatibility contexts may report a lower version depending on each driver. + +Mesa 23.3.0 implements the Vulkan 1.3 API, but the version reported by +the apiVersion property of the VkPhysicalDeviceProperties struct +depends on the particular driver being used. + +SHA256 checksum +--------------- + +:: + + 50f729dd60ed6335b989095baad81ef5edf7cfdd4b4b48b9b955917cb07d69c5 mesa-23.3.0.tar.xz + + +New drivers +----------- +- NVK: A Vulkan driver for Nvidia hardware + +New features +------------ +- VK_EXT_pipeline_robustness on ANV +- VK_KHR_maintenance5 on RADV +- OpenGL ES 3.1 on Asahi +- GL_ARB_compute_shader on Asahi +- GL_ARB_shader_atomic_counters on Asahi +- GL_ARB_shader_image_load_store on Asahi +- GL_ARB_shader_image_size on Asahi +- GL_ARB_shader_storage_buffer_object on Asahi +- GL_ARB_sample_shading on Asahi +- GL_OES_sample_variables on Asahi +- GL_OES_shader_multisample_interpolation on Asahi +- GL_OES_gpu_shader5 on Asahi +- EGL_ANDROID_blob_cache works when disk caching is disabled +- VK_KHR_cooperative_matrix on RADV/GFX11+ + + +Bug fixes +--------- + +- crash in si_update_tess_io_layout_state during _mesa_ReadPixels (radeonsi_dri, mesa 23.2.1) +- mesa: vertex attrib regression +- [RADV] War Thunder has some grass flickering. +- radv: satisfactory broken shader +- RADV problem with R7 M440 in some games +- gpu driver crashes when opening ingame map playing dead space 2023 +- [anv] Valheim water misrendering +- EGL/v3d: EGL applications under a X compositor doesn't work +- RADV: trunc_coord breaks ambient occlusion in Dirt Rally and other games +- radv: Mass Effect Legendary Edition: a line going across the screen is visible in some areas with Ambient Occlusion enabled +- anv: DIRT5 gfx11_generated_draws_spv_source triggers "assert(!copy_value_is_divergent(src) || copy_value_is_divergent(dest));" +- panfrost: gbm_bo_get_offset() wrongly returns 0 for second plane of NV12 buffers +- [RADV][TONGA] - BeamNG.drive (284160) - Artifacts are present when looking at the skybox. +- LEGO Star Wars: The Skywalker Saga graphical glitches (DXVK) on R9 380 +- [radv] Crypt not rendering properly +- Leaks of DescriptorSet debug names +- [Tracing flake] Missing geometry in trace\@freedreno-a630\@freedoom\@freedoom-phase2-gl-high.trace +- Unreal Engine 5.2 virtual shadow maps have glitchy/lazy tile updates +- RADV: Visual glitches in Unreal Engine 5.2.1 when using material with anisotropy and light channel 2 +- radv: Regression with UE5 test +- SIGSEGV with MESA_VK_TRACE=rgp and compute only queue +- [ANV] Corruptions in Battlefield 4 +- anv regression w/ commit e488773b29d97 ("anv: Fast clear depth/stencil surface in vkCmdClearAttachments") +- ir3: dEQP-GLES31.functional.synchronization.inter_invocation.image_atomic_read_write crash on a6xx gen4 +- Zink + Venus: driver can't handle INVALID<->LINEAR! +- Anv: Particles have black square artifacts on Counter Strike 2 on Skylake +- Lords of the Fallen 2023 Red Eye mode crashing game and desktop +- [radeonsi] [vulkan] [23.3-rc1 regression] Video output corrupted in QMplay2 with Vulkan renderer +- [BISECTED] ac/radeon commit somehow breaks nv12 surface from HEVC decode +- Parsec displays completely green screen with hardware decoder selected while using Mesa 23.3 and Mesa 24 +- H264 to H264 transcode output corruption with gst-vaapi +- opencl-jpeg-encoder does not work with nouveau/rusticl, works with nouveau/clover +- [R600] X-plane 11 demo (Linux Native) crashes upon launch on HD5870 and HD6970 +- Ubuntu 23.10 build error with rusticl_opencl_bindings.rs +- Rusticl fails to build +- ANV not handling VkMutableDescriptorTypeCreateInfoEXT::pMutableDescriptorTypeLists[i] being out of range +- tu: Wolfenstein: The New Order misrenders on a740 +- DRI_PRIME fails with ACO only radeonsi +- nir_to_tgsi: Incorrect handling of indirect array access +- ANV gen9 32 bit vulkan asserts on many cts tests +- GPU hang observed while launching 3DMark Wildlife Unlimited on MTL +- ac/gpu_info: Query maximum submitted IBs from the kernel +- RADV: regression in 23.2.1 causing GPU hang with RDNA1 in various UE5 games +- GPU page faults reported while playing Talos Principle 2 (demo) +- No CCS_E scanout on tgl+ with ANV +- anv: Modifier tests assert-fail on TGL+ +- ci: zink-tu jobs no longer included in manual pipelines +- [ANV][A770] GravityMark segfaults and buffer allocation errors +- etnaviv: gc2000 gles2 regression +- ci_run_n_monitor: pipeline finding unreliable +- nvk: Implement VK_EXT_dynamic_rendering_unused_attachments +- anv: jsl timeline semaphores flaky +- anv: OOB access in vkDestroyDevice? +- nvk: Implement VK_EXT_primitive_topology_list_restart +- nvk: Implement VK_EXT_image_sliced_view_of_3d +- nvk: Implement VK_KHR_workgroup_memory_explicit_layout +- util/macros: BITFIELD64_RANGE raises an error with mesa-clang if we try to set last bit +- r300/r400 regression; can't compile \`if/then` in shaders +- iris: gbm_bo_get_offset() wrongly returns 0 for second plane of NV12/P010 buffers +- nvk: Implement VK_EXT_depth_bias_control +- ICL/zink: gpu hang on 'piglit.object namespace pollution.framebuffer with gldrawpixels' +- [R600] Wolfenstein: The New Order text glitch on menu +- need extension to request image/texture not use data dependent compression +- rusticl: segfault in clCreateKernel on AMD Instinct MI100 +- !25587 broke xserver +- GPU Hang in Deep Rock Galactic on DG2 +- intel: Wrong length for 3DSTATE_3D_MODE on gfx125 +- [radeonsi] Wargame: Red Dragon /w OpenGL stopped working with ACO +- traces job reference images missing again sometimes +- Vulkan Texture/Polygon Glitches in Games +- freedreno: dmabuf modify query ignores format +- virgl: removing PIPE_CAP_CLEAR_TEXTURE completely breaks virglrenderer +- Turnip build error on termux +- failiure in amd llvm helper +- failiure in amd llvm helper +- radv_amdgpu_cs_submit: Assertion \`chunk_data[request->number_of_ibs - 1].ib_data.ip_type == request->ip_type' failed. +- hasvk: subgroups regression +- radeonsi: broken hardware decoding (vaapi/vulkan) on RDNA2 gpu (bisected) +- aco: SwizzleInvocationsMaskedAMD behavior is not correct for reads from inactive lanes +- anv: dEQP-VK.ssbo.phys.layout.random.16bit.scalar.13 slow +- [RDNA3] CS:GO - excessive power consumption and lower performance in Vulkan while MSAA is set to 4x or 8x +- [ICL] piglit.spec.arb_gl_spirv.execution.ssbo.unsized-array regression +- radv: Counter Strike 2 has multiple bugs while rendering smoke grenade effect +- Doom Eternal freezing on NAVI31 with current git +- iris CTS blend test fail with MSAA config on DG2 +- anv: 32bit mesa asserts +- RADV: Randomly dissapearing objects in Starfield with RX 5xx and Vega graphics +- anv: missing barrier handling on video engines +- radv: Star Wars The Old Republic hang when DCC is enabled +- radv: Resident Evil 6 hangs 7900XTX GPU when DCC is enabled if in Options go to Display settings +- radv: Resident Evil 6 Benchmark Tool hangs 7900 XTX GPU when DCC is enabled immediately after splash screen +- ANV: fp64 shader leaked +- v3d: noop drm-shim raises some warnings +- freedreno: crashdec/etc chip_id support +- intel: compute dispatches with variable workgroup size have ralloc_asprintf CPU overhead +- ci build issues with builtin types +- freedreno: running angle perf traces with GALLIUM_THREAD=0 crashes +- RadeonSI: glClear() causes clear texture for some frames on RX580 +- radeonsi: corruption when seeking video decoded with vaapi in mpv +- Zink/HasVK regression bisected to "gallium: move vertex stride to CSO" +- [radv] [Path Of Exile] - one setting in the workaround file breaks shadows/lighting rendering. Other workaround settings seems obsolete. +- radv: images don't always have extents in RGP +- shader_test causing a crash in compiler +- D3D12: Video decoding requirements are too restrictive. ID3D12VideoDevice3 should not be required. +- Crash in st_ReadPixels +- [regression] intel build issue on i386 +- [ANV] [DG2/A770] The Spirit and The Mouse, miscellaneous issues with Mesa Git +- zink on hasvk regression: Assertion \`(dyn)->vi_binding_strides[first_binding + i] == (strides[i])' failed. +- Penumbra: Overture hangs on new game loading screen +- [r300, RV516] Some deqp-gles2\@performance\@shader\@control_statement vertex tests cause hard lockup & reboot in mesa 22.3.1 (regression over 22.1.7) on a Radeon X1550 +- v3dv: Add a feature that implicitly copies the linear image to the tiled image prior to sampling from it +- radv: Regression from 266b2cfe5bf3feda16747c50c1638fb5a0426958 +- h264 encoding picture showed randomly repeated frames. +- Mesa CI: NAVI10 hangs when running VKCTS on Linux 6.1 +- zink: no uniform buffer objects support for v3dv? +- v3dv: Request for VkImageDrmFormatModifierExplicitCreateInfoEXT::pPlaneLayouts support +- [ANV] [DG2/A770] The Spirit and The Mouse, occasional flickering geometry +- [Google][Rex][anv] GLES dEQP test fails in anv when run via ANGLE-on-Venus on ChromeOS ARCVM. +- VAAPI on VCN: bad stream may crash whole gfx system +- Crash after GPU reset +- Bifrost PanVK should not be in CI +- [Intel][Vulkan][Gen12] vkCmdCopyImage() generates garbage data when the destination texture is bound to a piece of used device memory +- mesa: new glcts fails +- tu: GPL support is broken +- lavapipe: ycbcr regression +- aco: Assertion when compiling CP2077 shader +- anv: flakiness on tgl+ with samplemask handling +- [RADV] Dead by Daylight memory leak (shader-related?) on 23.1.6 +- r300: optionally convert MULs into output modifier for the following MUL or DOT instructions +- r300: better 1-x presubtract pattern matching +- gpu hang on DG2 when running KHR-GLES31.core.texture_cube_map_array.image_op_tess* +- KHR-GLES31.core.texture_cube_map_array.image_op_tessellation_evaluation_sh fail on GFX12+ +- wsi: deadlocks when DISPLAY is changed +- hasvk: Incompatible with minigbm/gralloc4 on Android +- VAAPI: AMDGPU crash on RX 6900 XT on corrupted video +- lavapipe/llvmpipe: shader unregister crash +- [ANV] [DG2/A380] Corruption in Borderlands 3 +- blorp regression on dg2 +- decouple -Dshader-cache= from EGL_ANDROID_blob_cache +- radv: commit 81641b01555faa4dd1dfc7de2513ad8d63e77ab7 leaded to artifacts in Quake II RTX +- [radv] Colors are distorted in Cyberpunk 2077 with ray tracing enabled +- Forza Horizon 5 stuttering since mesa 23.1.4 / 9b008673 revert as a FIX +- ubsan + gtest build fails +- glCopyTexSubImage2D is very slow on Intel +- NVE4 (GeForce 710) fails to get vdpau in mesa git +- [RADV] red and pink tinted shadows in Overwatch 2 on 7900 XTX +- nouveau prevents hardware acceleration with Chromium (Wayland) +- Corrupt text rendering in Blender +- DRI2 gallium frontend is using bad format type +- regression - MR 23089 - Hellblade RT crashing +- Incorrect vlVaCreateBuffer/vlVaMapBuffer behavior for buffer type VAEncCodedBufferType in Gallium +- Issue with clang-format +- Follow-up from "Draft: intel: Disable color fast-clears for blorp_copy" +- nightly VA-API build: new timeout +- r600: retire the SB optimizer +- ci: do not download perfetto on-fly in build jobs +- Shared Memory Leak With Qt OpenGL Applications +- OpenGL, SIGSEGV when program pipeline objects has separated vertex shader progam and separated fragment shader progam with in/out +- vaDeriveImage returns VA_STATUS_ERROR_OPERATION_FAILED +- 975a8ecc881873744d851ab0ef45ad7698eaa0ef "frontends/va: use resources instead of views" cause radeonsi can't play video. +- zink: reduce pipeline hash size +- Rusticl,radeonsi: ac_rtld error(2): too much LDS +- aco, radv Rage 2 menu corruption - bisected +- radv, aco: World War Z character texture regression on 7900xtx +- android: De-stage drm_gralloc support from mesa3d +- Cyberpunk screen goes black at game launch on integrated Gfx +- lavapipe/llvmpipe: regressions since descriptor rewrite +- intel: State cache invalidation after BLORP binding table setup ought to be unnecessary on ICL. +- ci: HW job logs have spam at the end +- kernel crash seen on AMD Raven device +- crocus: regression crashing in doubles/ubo tests +- turnip: object management CTS crashes +- a618: multiple assertions with different kernel config on u_vector_add +- [anv] Death Stranding crashes +- Can no longer build Clover without llvmspirvlib +- [radeonsi][vaapi] segfault in vl_video_buffer_sampler_view_components() when using vaapisink receiving I420 format +- Baldurs Gate 3 (DX11) - Graphical corruption on RDNA3 (ACO regression) +- [AMDGPU] Compiling large Blender Eevee shader node trees is unusably slow +- Building llvmpipe with LP_USE_TEXTURE_CACHE set fails since 23.2.0-rc1: error C2039: dynamic_state is not member of lp_build_sampler_soa in lp_tex_sample.c +- r300: calculate some cycles estimate for shader-db +- intel: Deathloop and other DX12 games fail assert(validated) with invalid SEL instruction +- GTF-GL46.gtf21.GL.build.CorrectFull_vert regressed on intel platforms +- error message when encoding via VAAPI AMD +- gpu hangs on dg2 with mesh shading enabled on vkcts +- radeonsi: Deadlock when creating a new GL context in parallel with linking a shader on another GL context +- robustness2 raygen tests intermittently fail in Intel Mesa CI +- ci/ci_run_n_monitor.py: KeyError: 'clang-format' +- glthread: huge performance regression +- DirectX games do not launch on Intel HD Graphics 4000 (IVB GT2) [bisected] +- rusticl: fails to build for iris + radeonsi + + +Changes +------- + +Adam Jackson (3): + +- egl: Implement EGL_EXT_explicit_device +- mesa: Implement and advertise GL_MESA_sampler_objects +- docs: Mention 'meson devenv' in the pre-install test instructions + +Aditya Swarup (6): + +- isl: enable Tile64 for 3D images +- intel/isl: Unittest for linear to Ytile conversion +- intel/isl: Convert linear texture to Tile4 format +- intel/isl: Convert Tile4 texture to linear format +- intel/isl: Linear to Tile-4 conversion unittest +- Revert "iris: Disable tiled memcpy for Tile4" + +Alba Mendez (1): + +- meson: support installation tags + +Alejandro Piñeiro (61): + +- v3dv: re-enable sync_fd import/export on the simulator +- broadcom(cle,clif,common,simulator): add 7.1 version on the list of versions to build +- broadcom/cle: update the packet definitions for new generation v71 +- broadcom/common: add some common v71 helpers +- broadcom/qpu: add comments on waddr not used on V3D 7.x +- broadcom/qpu: set V3D 7.x names for some waddr aliasing +- broadcom/compiler: rename small_imm to small_imm_b +- broadcom/compiler: add small_imm a/c/d on v3d_qpu_sig +- broadcom/qpu: add v71 signal map +- broadcom/qpu: define v3d_qpu_input, use on v3d_qpu_alu_instr +- broadcom/qpu: add raddr on v3d_qpu_input +- broadcom/qpu: defining shift/mask for raddr_c/d +- broadcom/commmon: add has_accumulators field on v3d_device_info +- broadcom/qpu: add qpu_writes_rf0_implicitly helper +- broadcom/qpu: add pack/unpack support for v71 +- broadcom/compiler: phys index depends on hw version +- broadcom/compiler: don't favor/select accum registers for hw not supporting it +- broadcom/vir: implement is_no_op_mov for v71 +- broadcom/compiler: update vir_to_qpu::set_src for v71 +- broadcom/qpu_schedule: add process_raddr_deps +- broadcom/qpu: update disasm_raddr for v71 +- broadcom/qpu: return false on qpu_writes_accumulatorXX helpers for v71 +- broadcom/compiler: add support for varyings on nir to vir generation for v71 +- broadcom/compiler: payload_w is loaded on rf3 for v71 +- broadcom/qpu_schedule: update write deps for v71 +- broadcom/compiler: update register classes to not include accumulators on v71 +- broadcom/qpu: implement switch rules for fmin/fmax fadd/faddnf for v71 +- broadcom/compiler: update one TMUWT restriction for v71 +- broadcom/compiler: update ldunif/ldvary comment for v71 +- broadcom/compiler: update payload registers handling when computing live intervals +- broadcom/qpu: new packing/conversion v71 instructions +- v3dv/meson: add v71 hw generation +- v3dv: emit TILE_BINNING_MODE_CFG and TILE_RENDERING_MODE_CFG_COMMON for v71 +- v3dv/cmd_buffer: emit TILE_RENDERING_MODE_CFG_RENDER_TARGET_PART1 for v71 +- v3dvx/cmd_buffer: emit CLEAR_RENDER_TARGETS for v71 +- v3dv/cmd_buffer: emit CLIPPER_XY_SCALING for v71 +- v3dv/uniforms: update VIEWPORT_X/Y_SCALE uniforms for v71 +- v3dv/cmd_buffer: just don't fill up early-z fields for CFG_BITS for v71 +- v3dv: default vertex attribute values are gen dependant +- v3dv/pipeline: default vertex attributes values are not needed for v71 +- v3dv/pipeline: handle GL_SHADER_STATE_RECORD changed size on v71 +- v3dv: no specific separate_segments flag for V3D 7.1 +- v3dv: add support for TFU jobs in v71 +- v3d: add v71 hw generation +- v3d: emit TILE_BINNING_MODE_CFG and TILE_RENDERING_MODE_CFG_COMMON for v71 +- v3d: TILE_RENDERING_MODE_CFG_RENDER_TARGET_PART1 +- v3d: emit CLEAR_RENDER_TARGETS for v71 +- v3d: just don't fill up early-z fields for CFG_BITS for v71 +- v3d: emit CLIPPER_XY_SCALING for v71 +- v3d: no specific separate_segments flag for V3D 7.1 +- v3d: default vertex attributes values are not needed for v71 +- v3d/uniforms: update VIEWPORT_X/Y_SCALE uniforms for v71 +- v3d: handle new texture state transfer functions in v71 +- v3d: handle new TEXTURE_SHADER_STATE v71 YCbCr fields +- v3d: setup render pass color clears for any format bpp in v71 +- v3d: GFX-1461 does not affect V3D 7.x +- v3d: don't convert floating point border colors in v71 +- v3d: handle Z clipping in v71 +- v3d: add support for TFU blit in v71 +- v3dv: implement depthBounds support for v71 +- doc/features: update after last v3d changes + +Alex Denes (1): + +- virgl: link VA driver with build-id + +Alexander Orzechowski (1): + +- radeonsi: Set PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET for auxiliary contexts + +Alyssa Rosenzweig (431): + +- zink: Switch to register intrinsics +- gallium/trace: Collect enums from multiple files +- gallium,util: Move blend enums to util/ +- gallium,util: Move util_blend_dst_alpha_to_one +- util/blend: Add helpers for normalizing inverts +- vulkan: Add helpers for blend enum translation +- lvp: Use common blend/logicop translation +- nir/lower_blend: Use util enums +- panfrost: Convert to PIPE_BLEND enums internally +- gallium: Remove pipe->compiler BLEND enum translation +- compiler: Remove blend enums duplicating util +- nir/legacy: Fix fneg(load_reg) case +- nir/legacy: Fix handling of fsat(fabs) +- ntt: Switch to new-style registers and modifiers +- ir3: Convert to register intrinsics +- nir: Add fence_{pbe,mem}_to_tex(_pixel)_agx intrinsics +- nir: Devendor load_sample_mask +- nir: Promote tess_coord_r600 to tess_coord_xy +- nir: Add nir_lower_tess_coord_z pass +- r600: Use nir_lower_tess_coord_xy +- ir3: Use nir_lower_tess_coord_z +- nir: Initialize workgroup_size in builder_init_simple_shader +- v3dv: Rely on nir_builder setting workgroup size +- radv: Rely on workgroup_size initialization +- panfrost: Fix transform feedback on v9 +- r600/sfn: Remove nir_register unit tests +- panfrost: Lower vertex_id for XFB +- panfrost: Fix transform feedback on v9 harder +- asahi: Augment fake drm_asahi_params_global +- asahi: Use nir_builder_at more +- asahi: Remove unused #define +- asahi: Refactor PBE upload routine +- asahi: Extract shader_initialize helper +- asahi: Serialize NIR in memory +- asahi: Identify background/EOT counts +- asahi,agx: Set coherency bit for clustered targets +- ail: Page-align layers for writable images +- asahi: Mark writeable images as such +- asahi: Reallocate to set the writeable image flag +- asahi: Add agx_batch_track_image helper +- asahi: Add texture/image indexing lowering pass +- asahi: Upload at most the max texture state registers +- asahi: Upload image descriptors +- asahi: Make clear the non-sRGBness of EOT images +- asahi: Don't restrict sampler views +- asahi: Forbid 2D Linear with images +- agx: Add try_coalesce_with helper +- agx: Try to allocate phis compatibly with sources +- agx: Try to allocate phi sources with phis +- agx: Try to allocate phi sources with loop phis +- agx: Vectorize 16-bit parallel copies +- agx: Reduce un/packs with mem access lowering +- agx: Fix bogus assert +- asahi: Augment PBE descriptor for software access +- asahi: Extend PBE packing for image support +- asahi: Use nir_lower_robust_access +- agx: Legalize image LODs to be 16-bit +- agx: Lower image size to txs +- agx: Generalize texture/PBE packing +- agx: Add image write instruction +- agx: Model texture bindless base +- agx: Handle bindless properly for txs lowering +- agx: Pack bindless textures +- agx: Translate texture bindless handles +- agx: Translate image_store from NIR +- agx: Handle frag side effects without render targets +- agx: Wait for outstanding stores before barriers +- agx: Implement image barriers +- agx: Handle early_fragment_tests +- agx: Add interleave opcode +- agx: Extract coords_for_buffer_texture helper +- agx: Extract texture_descriptor_ptr_for_* helpers +- agx: Lower image atomics +- agx: Lower buffer images +- asahi,agx: Fix txf sampler +- agx: Add image_load opcode +- agx: Extract texture write mask handling +- agx: Implement image_load +- agx: Emit global memory barriers for images +- agx: Don't emit silly barriers +- agx: Implement fence_*_to_tex_agx intrinsics +- agx: Add simple image fencing pass +- agx: Require tag writes with side effects +- agx: Plumb in coverage mask +- asahi: Extract sampler_view_for_surface +- asahi: Introduce concept of spilled render targets +- asahi: Add agx_tilebuffer_spills query +- asahi: Do not support masking with spilled RTs +- asahi: Ignore spilled render targets in EOT shaders +- asahi: Ignore spilled render targets with partial renders +- asahi: Extract some tilebuffer lowering code +- asahi: Lower tilebuffer access for spilled RTs +- asahi: Lower multisample image stores +- asahi: Permit meta shaders to use preambles +- asahi: Ignore spilled render targets for background load +- asahi: Offset clear colour uniform by 4 +- asahi: Execute preambles for background programs +- asahi: Advertise Z16_UNORM +- ir2: Switch to nir_legacy +- intel/fs: Don't read reg.base_offset +- panfrost: Remove unused helpers +- nir: Remove nir_lower_locals_to_regs +- nir: Rename lower_locals_to_reg_intrinsics back +- nir: Remove register arrays +- asahi: Don't depend on glibc to decode +- pan/bi: Remove leftover include +- nir/trivialize: Handle more RaW hazards +- panfrost: Disable blending for no-op logic ops +- nir/lower_blend: Fix 32-bit logicops +- nir/lower_blend: Optimize out PIPE_LOGICOP_NOOP +- clang-format: Ignore original panfrost commit +- nir/schedule: Assume no old-style registers +- gallium/u_simple_shaders: Optimize out ffloors +- gallium/u_transfer_helper: Remove dead forward decl +- nir/loop_analyze: Drop unused inverse_comparison +- nir/passthrough_gs: Drop unused array_size_for_prim +- panfrost: Add missing static inline annotation +- pan/decode: Drop unused debug function +- pan/mdg: Add missing static inline annotation +- panfrost: Drop unused decode_position for samples +- panfrost: Only define pan_blitter_get_blend_shaders for midgard +- panfrost: Add missing inline +- panfrost: Gate overdraw_alpha on Bifrost+ +- nir: Rename scoped_barrier -> barrier +- nir: Remove lower_to_source_mods +- nir: Remove lower_vec_to_movs +- nir: Remove reg_intrinsics parameter to convert_from_ssa +- nir: Remove register load/store builders +- r600/sfn: Stop referencing legacy functionality +- r600/sfn: Ignore instruction write masks +- nouveau/codegen: Drop writemask check +- vc4,broadcom/compiler: Drop write_mask handling +- zink: Collapse is_ssa check +- nir: Add {...} before case +- nir/from_ssa: Drop legacy reg support +- nir/schedule: Drop nir_schedule_dest_pressure +- nir: Drop NIR reg create/destroy +- nir: Remove nir_index_local_regs and callers +- nir/schedule: Drop more nir_register handling +- nir: Remove nir_foreach_register +- nir: remove nir_{src,dest}_for_reg +- ntt: Drop nir_register reference +- nir/print: Assume SSA +- nir/clone: Assume SSA +- nir/serialize: Drop legacy NIR +- nir/validate: Assume SSA +- nir: Remove impl->{registers,reg_alloc} +- nir: Remove nir_alu_dest::saturate +- treewide: Drop is_ssa asserts +- nir: Collapse some SSA checks +- treewide: Remove more is_ssa asserts +- nir: Remove reg-only dest manipulation +- nir: Remove stale todo +- nir/print: Drop legacy NIR +- nir: Drop nir_alu_src::{negate,abs} +- treewide: sed out more is_ssa +- pan/mdg: Assume SSA +- treewide: Drop some is_ssa if's +- nir: Drop trivial reg handling +- aco: Remove is_ssa check +- intel: Collapse is_ssa checks +- llvmpipe: Assume SSA +- ir3: Collapse is_ssa checks +- lima: Collapse is_ssa checks +- radeonsi: Collapse SSA check +- nir/gather_ssa_types: Collapse SSA checks +- nir/worklist: Assume SSA +- nir/range_analysis: Assume SSA +- treewide: Collapse more SSA checks +- nir/instr_set: Assume SSA +- nir: Collapse more SSA checks +- nir: Remove def_is_register +- nir: Do not init dests +- nir: Initialize source as a NULL SSA def +- nir: Collapse more SSA checks +- nir: Remove nir_{src,dest}::is_ssa +- nir: Drop nir_register +- nir/from_ssa: Remove pointless union +- ir3: Drop write_mask handling +- rogue: Stop reading write masks +- etnaviv: Don't use alu->dest.write_mask +- etnaviv: What if we just didn't have a compiler? +- intel/vec4: Don't use legacy write mask +- ntt: Evaluate write_mask check +- nir: Remove nir_alu_dest::write_mask +- nir: Remove nir_foreach_def +- lima: Clean up after deleting asserts +- nir: Remove no-op remove_def_cb +- nir: Drop no-op all_srcs_are_ssa +- nir: Simplify alu_instr_is_copy +- nir: Add load_coefficients_agx intrinsic +- agx: Implement nir_intrinsic_load_coefficients_agx +- agx: Allow more varying slots +- agx: Set lower_fisnormal +- agx: Forcibly vectorize pointcoord coeffs +- agx: Add interpolateAtOffset lowering pass +- agx: Lower flat shading in NIR +- asahi: Stub num_dies +- asahi: Move a bunch of helpers to common +- agx: Lower 8-bit ALU +- agx: Handle 8-bit vecs +- asahi,agx: Respect no16 even for I/O +- agx: Don't lower load_local_invocation_index +- agx/dce: Use the helper +- agx: Fix atomics with no destination +- agx: Fix shader info with sample mask writes +- agx: Do not move bindless handles +- agx: Put else instructions in the right block +- agx: Use unconditional else instruction +- agx: Optimize out pointless else instructions +- agx: Fix length bit confusion +- agx: Require an immediate for \`nest` +- agx: Use compressed fadd/fmul encodings +- agx: Optimize swaps of 2x16 channels +- agx: Optimize logical_end removal +- agx: Fix AGX_MESA_DEBUG=demand +- agx: Maintain ctx->max_reg while assigning regs +- agx: Allow 64-bit memory regs +- agx: Fix accounting for phis +- agx: Set phi sources in predecessors +- agx: Stop setting registers after the shader +- agx: Use agx_replace_src +- agx: Assert invariant stated in the comment +- agx: Don't use ssa_to_reg across blocks +- agx: Don't reuse ssa_to_reg across blocks +- agx: Remove unused allocation +- agx: Stop setting forwarding bit +- agx: Handle blocks with no predecessors +- agx: Lower f2u8/f2i8 +- agx: Handle conversions to 8-bit +- agx: Fix uadd_sat packing +- agx: Fix 64-bit immediate moves +- agx: Lower f2f16_rtz +- agx: Handle f2f16_rtne like f2f16 +- agx: Handle <32-bit local memory access +- agx: Do not allow creating vec8 +- asahi: Legalize compression before blitting +- nir: Drop "SSA" from NIR language +- agx: Stop passing nir_dest around +- agx: Remove agx_nir_ssa_index +- pan/mdg: Don't reference nir_dest +- pan/bi: Don't reference nir_dest +- asahi: Do not reference nir_dest +- panfrost: Do not reference nir_dest +- zink: Do not reference nir_dest +- ir3: Do not reference nir_dest +- dxil: Do not reference nir_dest +- nir: Drop nir_dest_init +- panfrost: Pack stride at CSO create time on v9 +- lvp,nir/lower_input_attachments: Use nir_trim_vector +- broadcom/compiler: Use nir_trim_vector explicitly +- nir: Assert that nir_ssa_for_src components matches +- nir: Add nir_shader_intrinsics_pass +- nir: Lower fquantize2f16 +- agx: Lower fquantize2f16 +- nir/lower_helper_writes: Consider bindless images +- nir/passthrough_gs: Correctly set vertices_in +- nir/passthrough_gs: Fix array size +- nir/print: Print access qualifiers for intrinsics +- nir/lower_gs_intrinsics: Remove end primitive for points +- panfrost/ci: Disable T720 +- nir: Add load_sysval_agx intrinsic +- agx: Fix extraneous bits with b2b32 +- agx: Use more barriers +- asahi: Copy CSO stride +- agx: Assert vertex_id, instance_id are VS-only +- asahi: Keep drawoverhead from OOMing itself +- agx: Don't blow up when lowering textures twice +- agx/lower_vbo: Handle nonzero component +- agx: Allow loop headers without later preds +- agx: Handle b2i8 +- agx: Convert 8-bit comparisons +- agx: Implement imul_high +- asahi: Advertise OpenGL ES 3.1! +- asahi/decode: Turn assert into error +- asahi: Report local_size from compiler +- asahi: Use local_size from compiler directly +- asahi: Pass layer stride in pixels, not elements +- agx: Clear sample count after lowering MSAA +- agx: Clear image_array after lowering +- asahi: Preserve atomic ops when rewriting image to bindless +- agx: Use 16-bit reg for pixel_coord +- asahi: Generalize query logic +- asahi: Simplify occlusion query batch tracking +- asahi: Refactor agx_get_query_result +- asahi: Only touch batch->occlusion_queries for occlusion +- asahi: Sync when beginning a query +- asahi: Add non-occlusion query tracking +- asahi: Add get_query_address helper +- agx/fence_images: Use intrinsics_pass +- agx: Do not fence write-only images +- asahi: Add missing LOD source for agx_meta's txfs +- agx: Do some texture lowering early +- agx: Add helper returning if a descriptor crawl is needed +- nir,asahi: Remove texture_base_agx +- asahi: Move UBO lowering into GL driver +- asahi: Add sysval tables for each shader stage +- asahi: Split out per-stage sysvals +- asahi: Collapse grid_info +- asahi: Extract agx_upload_textures +- asahi: Upload a single draw_uniforms per draw +- asahi: Add real per-stage dirty flags +- asahi: Extract sampler upload +- asahi: Put unuploaded uniforms on the batch +- asahi: Decouple sysval lowering from uniform assignment +- asahi: Use finer dirty tracking for blend constant +- asahi: Use proper dirty tracking for VBOs +- asahi: Dirty track VBOs + blend const separately +- asahi: Dirty the shader stage when the shader changes +- asahi: Fix shader stage dirtying +- treewide: Use nir_shader_intrinsic_pass sometimes +- treewide: Also handle struct nir_builder form +- nir/lower_shader_calls: Fix warning with clang +- nir: Add nir_before/after_impl cursors +- treewide: Use nir_before/after_impl in easy cases +- treewide: Use nir_before/after_impl for more elaborate cases +- radv: Use before/after_cf_list for entrypoints +- ci: Disable known broken Bifrost Vulkan job +- ci: Disable WHL jobs +- nir/opt_if: Simplify if's with general conditions +- asahi: Fixes for clang-warnings +- agx: Fix jmp_exec_none encoding +- agx/validate: Print to stderr +- agx: Annotate opcodes with a scheduling class +- agx: Add schedule-specialized get_sr variants +- agx: Include schedule class in the opcode info +- agx: Schedule for register pressure +- agx: Lower pack_32_4x8_split +- asahi: Force translucency for ignored render targets +- agx: Remove logical_end instructions +- agx: Lower pseudo-ops later +- agx: Expand nest +- agx: Lower nest later +- agx: Split nest instruction into begin_cf + break +- agx: Add break_if_*cmp instructions +- agx: Add agx_first/last_instr helpers +- agx: Use agx_first_instr +- agx: Detect conditional breaks +- agx: Omit push_exec at top level +- agx: Omit while_icmp without continue +- agx: Add helper to determine if a NIR loop uses continue +- agx: Only use nest by 1 for loops w/o continue +- agx: Add pseudo-instructions for icmp/fcmp +- agx: Generate unfused comparison pseudo ops +- agx: Fuse conditions into if's +- agx: Fuse compares into selects +- agx: Add unit test for if_cmp fusing +- agx: Add unit test for cmp+sel fusing +- asahi: Translate cube array dimension +- ail: Force page-alignment for layered attachments +- agx: Handle cube arrays when clamping arrays +- agx: Lower coordinates for cube map array images +- agx: Run opt_idiv_const after lowering texture +- asahi: Forbid linear 1D Array images +- asahi: Handle linear 1D Arrays +- asahi: Conditionally expose cube arrays +- gallium,mesa/st: Add PIPE_CONTEXT_NO_LOD_BIAS flag +- asahi: Skip LOD bias lowering for GLES +- nir: Add nir_function_instructions_pass helper +- nir: Add NIR_OP_IS_DERIVATIVE property +- nir: Hoist nir_op_is_derivative +- nir/opt_preamble: Use nir_op_is_derivative +- nir/opt_gcm: Use nir_op_is_derivative more +- nir/gather_info: Use nir_op_is_derivative +- nir/opt_sink: Sink load_constant_agx +- nir/opt_sink: Sink load_local_pixel_agx +- nir/opt_sink: Sink frag coord instructions +- nir/opt_sink: Do not move derivatives +- nir/opt_sink: Move ALU with constant sources +- nir/opt_sink: Also consider load_preamble as const +- agx: Enable sinking ALU +- treewide: Drop nir_ssa_for_src users +- treewide: Remove remaining nir_ssa_for_src +- nir: Remove nir_ssa_for_src +- asahi: Clamp index buffer extent to what's read +- agx: Align the reg file for 256-bit vectors +- agx: Hoist sample_mask/zs_emit +- agx: Set PIPE_SHADER_CAP_CONT_SUPPORTED +- agx: Augment if/else/while_cmp with a target +- agx: Add jumps to block ends +- agx: Add agx_prev_block helper +- agx: Insert jmp_exec_none instructions +- nir: Add layer_id_written_agx sysval +- nir: Support arrays in block_image_store_agx +- agx/nir_lower_texture: Allow disabling layer clamping +- agx: Pack block image store dim correctly +- agx: Handle layered block image stores +- agx: Add pass to lower layer ID writes +- asahi: Add helper to get layer id in internal program +- asahi,agx: Select layered rendering outputs +- agx: Support packed layered rendering writes +- agx/tilebuffer: Support layered layouts +- agx/lower_tilebuffer: Support spilled layered RTs +- asahi: Use layered layouts +- asahi: Expose VS_LAYER_VIEWPORT behind a flag +- asahi: Account for layering for attachment views +- asahi: Assume LAYER is flat-shaded +- asahi: Add pass to predicate layer ID reads +- asahi: Predicate layer ID reads +- asahi: Write to cubes/etc attachments as 2D array +- asahi: Use a 2D Array texture for array render targets +- asahi: Generate layered EOT programs +- asahi: Handle layered background programs +- lima/pp: Do not use union undefined behaviour +- nir: Add trivial nir_src_* getters +- nir: Use set_parent_instr internally +- nir: Use getters for nir_src::parent_* +- nir: Assert the nir_src union is used safely +- nir: Use a tagged pointer for nir_src parents +- nir: Add ACCESS_CAN_SPECULATE +- ir3: Set CAN_SPECULATE before opt_preamble +- ir3: Model cost of phi nodes for opt_preamble +- nir/opt_preamble: Walk cf_list manually +- nir/opt_preamble: Preserve IR when replacing phis +- nir/opt_preamble: Unify foreach_use logic +- nir/opt_preamble: Move phis for movable if's +- nir/opt_preamble: Respect ACCESS_CAN_SPECULATE +- freedreno/ci: Minetest +- r600/sfn: Handle load_global_constant +- nir/opt_phi_precision: Work with libraries +- nir/legalize_16bit_sampler_srcs: Use instr_pass +- nir/print: Handle KERNEL +- nir/lower_io: Use load_global_constant for OpenCL +- nir/opt_algebraic: Reduce int64 +- nir/opt_algebraic: Optimize LLVM booleans +- nir/trivialize_registers: Handle obscure load hazard +- hasvk: Support builiding on non-Intel +- crocus: Support building on non-Intel +- meson: Add vulkan-drivers=all option +- meson: Add gallium-drivers=all option +- agx: Fix fragment side effects scheduling + +Amber (7): + +- ir3: make wave_granularity configurable +- turnip: Add support for devices not supporting double thread size. +- turnip: make sampler_minmax support configurable. +- freedreno, turnip: set correct reg_size_vec4 for a6xx_gen1_low +- ir3: handle non-uniform case for atomic image/ssbo intrinsics +- freedreno: Add support for devices not supporting double thread size. +- turnip: Add debug option to allow non-conforming features. + +Andrew Randrianasulu (1): + +- nv50/ir: Remove few nvc0 specific defines from nv50-specific header. + +Antonio Gomes (9): + +- rusticl/kernel: Removing unnecessary clone in kernel launch +- rusticl/kernel: Add CsoWrapper +- rusticl/compiler: Add NirPrintfInfo +- rusticl: Move Cso to Program +- rusticl/compiler: Remove unnecessary functions +- rusticl: Move NirKernelBuild to ProgramDevBuild +- rusticl/program: New helper functions to NirKernelBuild +- rusticl/core: Delete KernelDevState and KernelDevStateInner +- rusticl/core: Make convert_spirv_to_nir output pair (KernelInfo, NirShader) + +Asahi Lina (29): + +- docs/tgsi: Specify that depth texture fetches are replicated +- asahi: Add synctvb debug flag +- asahi: Add smalltile debug option +- asahi: Add nomsaa debug flag +- asahi: decode: Add a params argument to pass through +- asahi: Add extra CDM header block for G14X +- asahi: wrap: Handle freeing shmems +- asahi: decode: Refactor to always copy GPU mem to local buffers +- asahi: decode: Add a function to construct decode_params from a chip_id +- asahi: Add a shared library interface for decode +- asahi: Add a noshadow debug flag +- asahi: Do not overallocate BOs by more than 2x +- asahi: Fix race in BO stats accounting +- asahi: Always use resource size, not BO size +- asahi: Print info about shadowed resources +- asahi: Impose limits on resource shadowing +- asahi: Force linear for SHARED buffers with no/implicit modifier +- asahi: Enable explicit coherency for G14D (multi-die) +- asahi: Handle non-written RTs correctly +- asahi: Fix incorrect BO bitmap reallocations +- asahi: Allocate staging resources as staging +- asahi: cmdbuf: Identify call/ret bits +- asahi: decode: Implement VDM call/ret +- asahi: decode: Do not assert on buffer overruns +- asahi: Fix VDM pipeline field width +- asahi: Add scaffolding for supporting driconf options +- asahi: Add and support the no_fp16 driconf flag +- driconf: Disable fp16 for browsers +- asahi: Allow no16 flag for disk cache + +Bas Nieuwenhuizen (16): + +- aco: fix nir_op_vec8/16 with 16-bit elements. +- aco: Fix some constant patterns in 16-bit vec4 construction with s_pack. +- nir: Fix 16-component nir_replicate. +- radv: Expose VK_EXT_external_memory_acquire_unmodified. +- util/perf: Add gpuvis integration. +- egl,venus,vulkan,turnip,freedreno: Update CPU trace init to init more than perfetto. +- vulkan: Add CPU tracing for vkWaitForFences. +- docs: Add documentation for gpuvis. +- vulkan: Add trace points for more Vulkan waiting functions. +- radv: Use a double jump to limit nops in DGC for dynamic sequence count. +- nir: Add AMD cooperative matrix intrinsics. +- aco: Add WMMA instructions. +- aco: Make RA understand WMMA instructions. +- radv: Don't transparently use wave32 with cooperative matrices. +- radv: Add cooperative matrix lowering. +- radv: Expose VK_KHR_cooperative_matrix. + +Benjamin Cheng (10): + +- radv/video: use app provided hevc scaling list order +- radv/video: copy from correct H264 scaling lists +- anv/video: copy from correct H264 scaling lists +- vulkan/video: add helper to derive H264 scaling lists +- radv/video: use vk_video_derive_h264_scaling_list +- anv/video: use vk_video_derive_h264_scaling_list +- util/vl: extract gallium vl scanning data to shared code +- radv/video: send h264 scaling list in raster order +- anv/video: send h264 scaling list in raster order +- radv/video: find SPS with pps_seq_parameter_set_id + +Benjamin Lee (1): + +- nvk: Fix segfault when opening DRI device file returns error + +Biswapriyo Nath (1): + +- radv/video: Match function definitions to declarations + +Boris Brezillon (1): + +- panfrost: Flag the right shader when updating images + +Boyuan Zhang (3): + +- virgl: Add vp9 picture desc +- virgl: Implement vp9 hardware decode +- radeonsi/vcn: disable tmz ctx buffer for VCN_2_2_0 + +Caio Oliveira (134): + +- nir: Use instructions_pass() for nir_fixup_deref_modes() +- meson: Ensure that LLVMSPIRVLib is not required for Clover +- nir: Let nir_fixup_deref_modes() fix deref_casts when possible +- nir: Add nir_opt_reuse_constants() +- radv: Use nir_opt_reuse_constants() +- compiler/types: Use ralloc for the key in array_types +- compiler/types: Use smaller keys for array_types table +- compiler/types: Extract get_explicit_matrix_instance() function +- compiler/types: Use smaller keys for explicit_matrix_types table +- anv/tests: Refactor state_pool_test_helper to not use macros for parametrization +- anv/tests: Link a single anv_tests binary using gtest +- anv/tests: Propagate failures to gtest +- hasvk/tests: Refactor state_pool_test_helper to not use macros for parametrization +- hasvk/tests: Link a single hasvk_tests binary using gtest +- hasvk/tests: Propagate failures to gtest +- util: Add convenience macros for linear allocator +- compiler/types: Use right hash for function types +- compiler/types: Don't duplicate empty string +- compiler/types: Constify a couple of pointers in glsl_type +- compiler/types: Remove unused GLSL_TYPE_FUNCTION and related functions +- compiler/types: Move GLSL specific builtin structs into glsl/ +- glsl: Add missing glsl_types initialization to test_optpass +- glsl: Don't create struct type builtins +- compiler/types: Add extra level of macro to builtin_macros +- compiler/types: Use designated initializer syntax to specify builtins +- compiler/types: Move local cache details to implementation file +- compiler/types: Add a mem_ctx for the glsl_type_cache +- compiler/types: Use type cache mem_ctx for hash tables +- compiler/types: Don't store a mem_ctx per type +- compiler/types: Simplify clearing the glsl_type_cache +- compiler/types: Move static asserts about glsl_type to a central place +- compiler/types: Store builtin types directly as data +- compiler/types: Use a linear (arena) allocator for glsl_types +- compiler/types: Make struct glsl_type visible to C code +- compiler/types: Add workaround to use builtin_type_macros.h in C +- compiler/types: Move builtin type initialization to C +- glsl: Annotate _mesa_glsl_error() with PRINTFLIKE +- compiler/types: Fix array name dimension flipping for unsized arrays +- compiler/types: Use Python to generate code for builtin types +- compiler/types: Use glsl_get_type_name() to access the type name +- compiler/types: Change glsl_type::name to be an uintptr_t +- compiler/types: Use a string table for builtin type names +- intel/compiler/xe2: Account for reg_unit() in TCS intrinsics +- intel/compiler/xe2: Account for reg_unit() in TES intrinsics +- intel/fs/xe2+: Update BS payload setup for Xe2 reg size. +- intel/fs/xe2+: Update TASK/MESH payload setup for Xe2 reg size. +- compiler: Use a meson dependency for libcompiler +- meson: Remove unnecessary inc_compiler mentions +- rusticl: Ensure NIR generated headers will be available +- clover: Hide SPIR-V related code behind HAVE_CLOVER_SPIRV +- clover: Only compile/depend libclspirv and libclnir when using SPIR-V support +- compiler: Only enable mesaclc helper if we have OpenCL SPIR-V support +- intel/compiler: Don't allocate memory for SIMD select error handling +- microsoft/compiler: Fix printf formatting string issues +- util: Add more PRINTFLIKE and MALLOCLIKE annotations +- util: Remove ralloc_parent from linear_header +- util: Use linear parent to (r)allocated extra nodes +- util: Remove size from linear_parent creation +- util: Make DECLARE_LINEAR_ALLOC_* macros assume no destructors +- util: Use an opaque type for linear context +- util: Remove usages of linear_realloc() +- util: Remove linear_realloc() +- util: Remove size information from child allocations +- util: Remove per-buffer header in linear alloc for release mode +- util: Add a few basic tests for linear_alloc +- util: Fix bookkeeping of linear node sizes +- intel/compiler: Don't store stage name and abbrev +- intel/compiler/xe2: URB fence uses LSC now +- intel/compiler/xe2: Fix URB writes in TCS +- intel/compiler/xe2: Update TCS ICP handle code to support SIMD16 +- compiler/types: Add support for Cooperative Matrix types +- nir: Add new intrinsics for Cooperative Matrix +- nir: Handle cooperative matrix in various passes +- spirv: Expose some memory related functions in vtn_private.h +- spirv: Let vtn_ssa_value hold references to variables +- spirv: Implement SPV_KHR_cooperative_matrix +- compiler/types: Remove private related declarations +- compiler/types: Remove use of new/delete +- compiler/types: Remove use of references +- compiler/types: Remove use of auto +- compiler/types: Use C compatible cast syntax +- compiler/types: Spell struct and enum in type names +- compiler/types: Add void parameter to ensure these are valid C prototypes +- intel/fs: Tweak default case of fs_inst::size_read() +- compiler/types: Move the C++ inline functions in glsl_type out of the struct body +- compiler/types: Move C declarations into glsl_types.h +- compiler/types: Flip wrapping of base_type checks +- compiler/types: Flip wrapping of various type identification checks +- compiler/types: Flip wrapping of convenience accessors for vector types +- compiler/types: Flip wrapping of basic "get type" functions +- rusticl: Add Rust bindings for inline glsl_types functions +- util: Add size to ralloc_header in debug mode +- util: Add a canary to identify gc_ctx in debug mode +- util: Add function print information about a ralloc tree +- util: Avoid waste space when linear alloc'ing large sizes +- spirv: Expose stage enum conversion in vtn_private.h +- spirv: Change spirv2nir to use the shorter shader name abbreviations +- spirv: List entry-points in spirv2nir when unsure what to use +- spirv: Let spirv2nir find out the shader to use +- intel/compiler: Don't emit calls to validate() in release build +- compiler/types: Flip wrapping of "type contains?" predicate functions +- compiler/types: Flip wrapping of array related functions +- compiler/types: Flip wrapping of cmat related functions +- compiler/types: Flip wrapping of CL related functions +- compiler/types: Flip wrapping of size related functions +- compiler/types: Flip wrapping of struct related functions +- compiler/types: Flip wrapping of interface related functions +- compiler/types: Flip wrapping of layout related functions +- compiler/types: Flip wrapping of record_compare +- compiler/types: Flip wrapping of get_instance() +- compiler/types: Flip wrapping of texture/sampler/image get instance functions +- compiler/types: Flip wrapping of various get instance functions +- compiler/types: Flip wrapping of get row/column type helpers +- compiler/types: Flip wrapping of remaining non-trivial type getters +- compiler/types: Flip wrapping of remaining small data getters +- compiler/types: Flip wrapping of numeric type conversion functions +- compiler/types: Move remaining code from nir_types to glsl_types +- rusticl: Add bindings for glsl_vector_type() +- compiler/types: Add more glsl_contains_*() functions and use them in C++ +- compiler/types: Add glsl_get_mul_type() and use it in C++ +- compiler/types: Add glsl_type_compare_no_precision() and use it in C++ +- compiler/types: Add glsl_type_uniform_locations() and use it in C++ +- compiler/types: Add glsl_get_std430_array_stride() and use it in C++ +- compiler/types: Add glsl_get_explicit_*() functions and use them in C++ +- compiler/types: Implement glsl_type::field_type() in terms of existing functions +- compiler/types: Add glsl_simple_explicit_type() and simplify glsl_simple_type() +- compiler/types: Add remaining type extraction functions and use them in C++ +- compiler/types: Use C instead of C++ constants for builtin types +- compiler/types: Remove usages of C++ members in glsl_types.cpp +- compiler/types: Annotate extern "C" only once in glsl_types.cpp +- compiler/types: Rename glsl_types.cpp to glsl_types.c +- compiler/types: Remove warnings about potential fallthrough +- compiler/types: Move comments and reorganize declarations +- anv: Fix leak when compiling internal kernels + +Carsten Haitzler (2): + +- kmsro: Add hdlcd DPU +- panfrost: Add GPU variant of G57 to the set of known ids + +Charles Giessen (1): + +- panvk: Use 1.0 in ICD Manifest json + +Charmaine Lee (8): + +- svga: set clear_texture to NULL for vgpu9 +- svga: fix stride used in vertex declaration +- svga: fix persistent mapped surface update to constant buffer +- svga: restrict use of rawbuf for constant buffer access to GL43 device +- svga: fix immediates used in rawbuf for constant buffer +- svga: use srv raw buffer for accessing readonly shader buffer +- svga: sync resource content from backing resource before image upload +- svga: ignore sampler view resource if not used by shaders + +Chia-I Wu (38): + +- radv: fix separate depth/stencil layouts in fb state +- radv: fix separate depth/stencil layouts in resolve meta +- radv: refactor depth clear in clear meta +- radv: fix separate depth/stencil layouts in clear meta +- amd/ci: update radv-stoney-aco-fails.txt for depth/stencil clear +- radv: disable tc-compat htile for layered images on gfx8 +- amd/ci: update radv-stoney-aco-fails.txt for depth/stencil resolve +- winsys/amdgpu: fix a race between import and destroy +- ac/surface: limit RADEON_SURF_NO_TEXTURE to color surfaces +- winsys/radeon: fix a race between bo import and destroy +- vulkan/runtime: add a helper for ETC2 emulation +- radv: use vk_tecompress_etc2 from the runtime +- vulkan/runtime: fix image type check for ETC2 emulation +- vulkan/runtime: fix a harmless typo for ETC2 emulation +- vulkan/runtime, radv: remove 1D support from ETC2 emulation +- radv: add radv_is_format_emulated +- radv: simplify view format override for emulated formats +- radv: hard code format features for emulated formats +- mesa: make astc_decoder.glsl vk-compatible +- radv, drirc: rename radv_require_{etc2,astc} +- anv: remove unused field from anv_image_view +- anv: add anv_image_view_{init,finish} +- anv: support image views with surface state stream +- anv: add anv_push_descriptor_set_{init,finish} +- anv: support alternative push descriptor sets +- anv: add anv_descriptor_set_write +- anv: add anv_cmd_buffer_{save,restore}_state +- anv: add anv_is_format_emulated +- anv: add a hidden plane for emulated formats +- anv: decompress on upload for emulated formats +- anv: fix up image views for emulated formats +- anv: fix up blit src for emulated formats +- anv: advertise emulated formats +- anv: add support for vk_require_astc driconf +- util: improve BITFIELD_MASK and BITFIELD64_MASK on clang +- anv: prep for gen9 astc workaround +- anv: add gen9 astc workaround +- radv: fix image view extent override for astc + +Chris Spencer (9): + +- radv: initialize result when pipeline cache creation fails +- anv/android: Fix importing hardware buffers with planar formats +- anv/android: Add support for AHARDWAREBUFFER_FORMAT_YV12 +- anv: Advertise Vulkan 1.3 on Android 13 +- anv: Don't reject Android image format if external props not supplied +- android: Add explanatory comment to u_gralloc +- anv/android: Enable shared presentable image support +- anv/video: use correct enum value for max level IDC +- radv/video: use correct enum value for max level IDC + +Christian Gmeiner (41): + +- nir/print: print instr pass_flags +- etnaviv: move nir texture lowerings into one pass +- nir: add enta specific intrinsic used for txs lowering +- etnaviv: nir: support intrinsic used for txs lowering +- etnaviv: nir: lower nir_texop_txs +- ci/etnaviv: update ci expectations +- etnaviv: make use of BITFIELD_BIT(..) macro +- etnaviv: name the enum used for pass_flags +- etnaviv: add is_dead_instruction(..) helper +- etnaviv: extend etna_pass_flags with source modifiers +- etnaviv: do not clear all pass_flags before RA +- etnaviv: nir: look at parent instr in lower_alu(..) +- etnaviv: nir: add etna_nir_lower_to_source_mods(..) +- etnaviv: nir: switch to etna_nir_lower_to_source_mods(..) +- etnaviv: nir: convert to new-style NIR registers +- freedreno/regs: remove double assignment of self.current_domain +- freedreno/regs: remove not used variable +- freedreno/regs: remove dead code +- freedreno/regs: python does not need ';' +- etnaviv: switch to log2f(..) +- etnaviv: switch to U_FIXED(..) macro +- etnaviv: switch to S_FIXED(..) macro +- etnaviv: fix null pointer dereference +- etnaviv: switch to float_to_ubyte(..) +- ci/etnaviv: update ci expectation +- etnaviv: unbreak cmdline compiler +- agx/lower_address: Use intrinsics_pass +- agx/lower_address: Remove not used has_offset +- isaspec: python does not need ';' +- docs: Move isaspec out of drivers/freedreno +- isaspec: Add support for templates +- isaspec: encode: Correct used regex +- isaspec: Add method to get all instrustions +- isaspec: Add support for custom meta information +- isaspec: Add BitSetEnumValue object +- spirv: Don't use libclc for rotate +- docs: update etnaviv extensions +- etnaviv: drm: Be able to mark end of context init +- etnaviv: Skip 'empty' cmd streams +- ci: Bump PyYAML to 6.0.1 +- etnaviv: Don't leak disk_cache + +Collabora's Gfx CI Team (2): + +- Uprev Piglit to ed58dfbd12be34fa3dab97a7a2987b890e0637f1 +- Uprev Piglit to f7db20b03de6896d013826c0a731bc4417c1a5a0 + +Cong Liu (2): + +- r300: Fix out-of-bounds access in ntr_emit_store_output() +- virgl:Fix ITEM_CPY macro pointer copy bug + +Connor Abbott (83): + +- afuc: Rework and significantly expand README.rst +- tu: Fix vk2tu_*_stage flag type +- tu: Fix and simplify execution dependency handling +- tu, freedreno/a6xx: Remove has_ccu_flush_bug +- ir3: Handle GS stream "mixing" with non-point output primitives +- tu: Disable transformFeedbackPreservesProvokingVertex +- isaspec: Add "displayname" for altering {NAME} when decoding +- isaspec: Add support for "absolute" branches +- isaspec: Add support for function and entrypoint labels +- isaspec: Add "custom" field type +- isaspec: Add callback after decoding an instruction +- isaspec: Rename isa_decode() to isa_disasm() +- isaspec: Add initial decoding support +- afuc: Fix xmov lexer typo +- afuc: Convert to isaspec +- afuc: Add setbit/clrbit +- afuc: Fix writing $00 +- freedreno/afuc: Initial a7xx support +- ir3: Parse (eq) flag +- ir3, freedreno, tu: Plumb through SP_FS_PREFETCH_CNTL::ENDOFQUAD +- tu: Add missing last_baryf statistic +- freedreno, tu, ir3: Add last_helper statistic +- ir3: Gather pixlod status earlier +- ir3: Implement helper invocation optimization +- vk/graphic_state, tu: Use dynamic blend count from subpass +- freedreno/a7xx: Add CP_RESET_CONTEXT_STATE +- vk/graphics_state: Fix copying MS locations pipeline state +- tu: Remove MSAA draw state +- tu: Merge SAMPLE_LOCATIONS and SAMPLE_LOCATIONS_ENABLE draw states +- tu: Merge PC_RASTER_CNTL into RAST draw state +- tu: Stop reusing base Vulkan dynamic state enums +- tu: Merge depth/stencil draw states +- tu: Rename PrimID-related registers +- tu, freedreno/a6xx: Don't use VS for PrimID passthru state +- tu: Pull entangled shader state into program config +- ir3: Add ir3_find_input_loc() helper +- tu: Split up tu6_emit_vpc() +- freedreno, ir3, tu: Constify various uses of ir3_shader_variant +- ir3: Add helper to determine when variant exceeds safe constlen +- tu: Split program draw state into per-shader states +- tu: Fix per-view viewport state propagation +- tu: Fix tu6_emit_*_fdm size call +- tu: Fix assert in FDM state emission +- tu: Actually emit patchpoint for viewports with FDM +- nir/lower_subgroups: Don't do multiple lowerings at once +- nir/spirv: Add inverse_ballot intrinsic +- amd: Use inverse ballot intrinsic if available +- tu: Create singleton "empty" shaders +- tu: Start tracking shaders independently of pipeline +- tu: Move FS-specific pipeline information to the shader +- tu: Use shader directly for VS/TCS output size and patch size +- tu: Rewrite tessellation modes handling +- tu: Rework passing shared consts +- tu: Decouple program state from the pipeline +- tu: Use pipeline feedback loop flag indirectly +- tu: Rewrite remaining pipeline LRZ handling +- tu: Don't reference pipeline for some draw states +- tu: Make compute dispatch use the shader +- tu: Don't use pipeline for dynamic draw states +- tu: Don't use pipeline for bandwidth validity +- tu: Don't use pipeline for per_view_viewport +- tu: Don't use pipeline for active stages +- tu: Remove pipeline from state +- zink: Rework color clamping and conversion +- freedreno/fdl: Use A8_UNORM HW format for sampling +- tu: Support clearing A8_UNORM +- freedreno/fdl: Support PIPE_FORMAT_R5G5B5A1_UNORM on a6xx +- tu/clear_blit: Fix staging image view layer count +- tu/clear_blit: Allow VK_REMAINING_ARRAY_LAYERS as layerCount +- tu: Allow VK_WHOLE_SIZE in tu_CmdBindVertexBuffers2EXT pSizes +- tu: Implement vkCmdBindIndexBuffer2KHR +- tu: Implement vkGetImageSubresourceLayout2KHR and vkGetDeviceImageSubresourceLayoutKHR +- tu: Implement vkGetRenderingAreaGranularityKHR +- tu: Use new buffer usage flags +- tu: Support VkPipelineCreateFlags2CreateInfoKHR +- tu: Check for DEVICE_LOST in vkGetEventStatus() +- tu: Add maintenance5 properties +- freedreno/ci: Skip dEQP-VK.info.device_extensions +- tu: Expose VK_KHR_maintenance5 +- freedreno/ci: Remove minetest trace +- v3d/ci: Remove minetest trace +- ir3/ra: Don't swap killed sources for early-clobber destination +- tu: Fix re-emitting VS param state after it is re-enabled + +Corentin Noël (16): + +- ci: Add locked flag to bindgen-cli installation +- virgl: Do not expose EXT_texture_mirror_clamp when using a GLES host +- ci: disable Collabora's LAVA lab for maintenance +- llvmpipe: make sure to initialize the lp_setup_context slots with the default values +- virgl: Cover all the formats defined in the virgl definition +- mesa: Ensure that the baselevel will never exceed the maximal supported number +- ci: Uprev virglrenderer +- freedreno/drm/virtio: Use MESA_TRACE_SCOPE instead of _BEGIN/_END +- tu: Use MESA_TRACE_SCOPE instead of _BEGIN/_END +- aux/tc: Use MESA_TRACE_SCOPE instead of _BEGIN/_END +- venus: Change the only occurrence of VN_TRACE_BEGIN/END to VN_TRACE_SCOPE +- util: Avoid the use of MESA_TRACE_BEGIN/END +- util/perf: Remove the tracing categories +- util: Remove MESA_TRACE_BEGIN/END +- mesa/bufferobj: ensure that very large width+offset are always rejected +- frontends/va: Remove wrong use of ProfileToPipe + +Daniel Schürmann (9): + +- nir/opt_move: fix handling of if-condition +- aco: append p_logical_end after monolithic RT shaders +- aco/insert_exec_mask: set Exact mode after p_discard_if when necessary +- aco: don't optimize cross-lane instructions across p_wqm +- aco: make p_wqm a marker instruction without Operands/Definitions +- aco: don't insert a copy when emitting p_wqm +- aco: insert a single p_end_wqm after the last derivative calculation +- aco/insert_exec_mask: Simplify WQM handling (1/2) +- aco/insert_exec_mask: Simplify WQM handling (2/2) + +Daniel Stone (23): + +- dri: Support 1555/4444 formats +- egl/dri2: Don't look up image extension twice +- egl/wayland: Always initialise fd_display_gpu +- egl/wayland: Add image loader extension for swrast +- egl/wayland: Never use DRI2_LOADER extension +- egl/wayland: Assume modern DRI interface versions +- egl/drm: Use IMAGE_DRIVER instead of DRI2_LOADER +- egl/drm: Assume modern DRI interface versions +- ci: Disable nouveau CI +- panfrost/vk: Use correct sampler dimensions for MSAA +- ci: Declare stages before jobs +- ci/radeonsi: Add new flake +- ci/d3d12: Add new flake +- ci/intel: Add new skqp flake +- ci/zink: Add new zink-lvp flakes +- ci/radeonsi: Skip more really slow tests +- ci/zink: Add another conversion fail on a618 +- ci: Move farm-disable rules before anything else +- ci: Always set user container jobs to manual +- ci: Use container rules for containers +- ci: Only look at file changes for MRs +- ci: Fix pre-merge pipelines with no code changes +- ci: Try really hard to print final result string + +Daniel van Vugt (1): + +- glx: Increment dpy->request before issuing an error that had no request + +Danylo Piliaiev (71): + +- freedreno/cffdec: Decode CP_DRAW_AUTO +- freedreno, turnip: Clarify some RB_CCU_CNTL fields +- freedreno,turnip: Make number of VSC pipes configurable +- freedreno,turnip: Make CS shared memory size configurable +- freedreno,turnip: Make VS input attr/binding count configurable +- freedreno: Add A605, A608, A610, A612 GPUs definition +- turnip: Make multiview support configurable per generation +- ir3: Make FS tex prefetch optimization optional +- ir3: Use NIR info to enable per sample shading +- freedreno/regs: Rename SP_FS_CTRL_REG0.DIFF_FINE into LODPIXMASK +- ir3: Fix FS quad ops returning wrong values from helper invocations +- tu,freedreno: Forbid blit event for R8G8_SRGB due to gpu faults +- radv: fix unused non-xfb shader outputs not being removed +- vulkan/nir: Add common helper to check if output is XFB +- radv: Use common nir_vk_is_not_xfb_output +- turnip: Use common nir_vk_is_not_xfb_output +- freedreno/regs: Define unknown SP_FS_PREFETCH_CNTL fields +- freedreno/registers: Refactor gen_header.py to allow more options +- freedreno/registers: Generate python files with reg offsets +- freedreno: Add a list of raw magic regs +- freedreno: Fully define a730 and a740 device properties +- ir3/tests: Use fd_dev_info to infer GPU generation +- freedreno/computerator: Fix remaining issues with A7XX +- isaspec: Make possible to obtain gpu_id in blocks +- ir3/a7xx: cat5 mode1 has swapped tex/samp ids +- ir3/a7xx: Don't multiply global mem instruction's offset by 4 +- ir3/a7xx: insert lock/unlock at the end of every compute shader +- ir3/a7xx: Add ccinv instruction +- ir3/a7xx: Use ccinv for data synchronization +- ir3/a7xx: Disable shared consts for a7xx +- tu/common: Generalize TU_GENX macro +- tu: Basic a7xx support +- freedreno/fdl: Set LOSSLESSCOMPEN for image when ubwc is enabled on a7xx +- tu/a7xx: Fix geometry shaders +- tu/a7xx: Fix tesselation shaders +- tu/a7xx: Fix multiview +- tu/a7xx: Fix flat shading +- tu/a7xx: Fix occlusion query +- tu/a7xx: Fix 3d blits after multiview usage +- tu/a7xx: Fix CmdDrawIndirectByteCountEXT +- tu/a7xx: Disable LRZ +- ir3/lower_tex_prefetch: Fix crash with lowered load_barycentric_at_offset +- tu: Exclude SP_UNKNOWN_AE73 from reg stomping +- tu: Call tu_cs_dbg_stomp_regs with appropriate GPU gen +- freedreno/replay: Add limited support for KGSL +- freedreno/rddecompiler: Update to handle a7xx +- freedreno/replay: Add "print" instr to ir3 asm to be used in replay +- freedreno/replay: Add "gpu_print" function for command streams +- tu/perfetto: Remove now unnecessary tu_perfetto_util +- tu/perfetto: Allow gpu time to be passed into tu_perfetto_submit +- tu/kgsl: Fix memory leak of tmp allocations during submissions +- tu/kgsl: Support u_trace and perfetto +- tu/a7xx: Correctly record timestamps for u_trace +- tu/virtio: Fix incorrect call to tu_perfetto_submit +- ci: Compile Turnip's virtio kmd in debian-arm64 +- freedreno/registers: Refine a7xx push consts registers +- ir3,tu: Refactor push consts info plumbing +- freedreno: Make possible to specify A7XX feature flags +- turnip,ir3: Implement A7XX push consts load via preamble +- tu: Add push_consts_per_stage debug option +- tu: Fix VK_FORMAT_A8_UNORM_KHR using UBWC when !has_8bpp_ubwc +- tu/kgsl: Fix field order in kgsl_command_object init +- tu: Fix stale tu_render_pass_attachment::store_stencil with dyn rendering +- tu: Zero init tu_render_pass and tu_subpass for dynamic rendering +- tu: Disable preamble push consts when they are not used +- ir3: Fix values of #wrmask not being compatible with ir3 parser +- tu: Count a whole push consts range in constlen for PREAMBLE push consts +- freedreno/rddecompiler: Use fd_dev_gen to pass gpu_id to ir3 disasm +- freedreno/rddecompiler: Decompile repeated IBs +- freedreno: Fix field size of A6XX_TEX_CONST[3].ARRAY_PITCH +- tu: Fix reading of stale (V)PC_PRIMITIVE_CNTL_0 + +Dave Airlie (163): + +- ci: remove binding model from the asan skips for lavapipe. +- gallivm: fix atomic global temporary storage. +- llvmpipe: fix fragdata/lastfragdata heuristic a bit more. +- nvk: add missing finish calls +- nvk: add some initial wsi framework. +- nvk: fix header guards to be less generic. +- nvk: add bind buffer memory +- nvk: Add initial queue +- nvk: add cmd buffer framework +- nvk: Reset pushbufs on command buffer reset +- nvk: reindent descriptor sets to mesa std. +- nvk: add initial descriptor pool framework. +- nvk: some boilerplate for descriptor sets +- nvk: add descriptor set bo allocation. +- nvk: implement buffer address. +- nvk: descriptor set freeing fix +- nvk: move to new command stream generator. +- nvk: port the blit and copy code to new command submission. +- nouveau/ws: drop the old push generators. +- nvk: link in codegen without gallium bits. +- nvk: Initial wiring in of the compiler +- nvk: Basic descriptor binding +- nouveau/vk: add support for compute classes to generator. +- nvk: retrieve gpc/mp counts from kernel. +- nvk: add support for preamble and tls allocation. +- nvk: add record result to cmd_buffer. +- nvk: add command stream upload buffer. +- nouveau/winsys: Add m2mf/compute objects +- nvk: add some basic format wrapping framework +- nvk: add some compute limits +- nvk: add basic nve4+ compute support. +- nvk: fix empty cmd submission. +- nouveau/ws: add a push reset just for references. +- nouveau/classes: add 906f header support. +- nvk: add initial 8/16 byte clears. +- nvk: fix pipeline pushbuf sizing +- nvk: increase graphics cpu push buffer +- nvk: fix depth emission ordering. +- nvk: add some limits/features from binary driver. +- nvk: add indexed draw support. +- nvk: assign vertex locations according to input attrib index +- nvk: lower io to temps to avoid output reads in vertex shaders +- nvk: handle NULL to destroy descriptor pool +- nvk: add basic primitive restart +- nvk: fix copy lower address extraction +- nvk: fix multiple pipelines failure allocation case. +- nvk: init dev->physical_device earlier. +- nvk/winsys: store device ptr into bo instead of ptr +- nvk: set the device fd +- nil: Fix image align and size constraints +- nvk: Report image alignments from NIL +- nouveau/winsys: allocate unique object handles across channels. +- nvk/nil: don't ask for compressed image kind +- nvk/barrier: handle host bit. +- nvk: add compute support for ampere +- nvk: add min_lod to spirv caps. +- nvk: fix r32_sint format support +- nvk: expose EXT_sampler_filter_minmax +- nvk: fix transform feedback crash when optimiser removes things. +- nvk: merge tess info between tcs/tes. +- nvk: introduce an optimisation loop. +- nvk: add support for D32_SFLOAT_S8_UINT +- nvk/query: fix push buffer size for copy pool results. +- nvk: init image fields for requirements +- nvk: handle alignments in device memory +- nvk/tess: don't emit patch control points in pipeline +- nvk: align geometry clip setting with nvc0 +- nvk: fix independent color write masks. +- nvk: enable rgb32 texel buffer support +- nvk: enable EXT_depth_clip_control +- nvk: enable EXT_depth_clip_enable +- nvk: always sync internal cmd bufs for vma lifetimes. +- nouveau/winsys: add support for the vma bind interfaces +- nvk: Add support for sparse buffers +- nvk: Add support for sparse images +- nvk/queue: add support for syncobjs and sparse binds +- nvk: Handle pre-turing indirect buffers with sparse +- nvk: enable sparse features +- nvk: enable a bunch of external fence/semaphore bits +- nvk: enable sparse residency buffer on maxwell+ +- nvk: add new internal bo allocation flag. +- docs: add two nvk exts to features.txt +- zink: use fprintf instead of printf to align the requirements warnings +- nvk: align sampler allocation counts with nvidia. +- zink: turn off threaded cpu access if not visible. +- nvk: add gart forced cmd pool side buffer. +- nvk: add cond render upload buffer. +- nvk: enable KHR_shader_clock. +- nvk: NOUVEAU_WS_BO_LOCAL is a trap. +- gallivm: drop unused info parameter +- llvmpipe/fs: drop cbuf 0 since it's lowered now. +- gallivm/nir: avoid using params->info +- llvmpipe/fs: move some tgsi checks in nir path to nir code. +- llvmpipe/cs: convert to using tgsi->nir +- llvmpipe/cs: drop tgsi for compute/mesh/task shader internals. +- lavapipe: use vk_buffer common code. +- lavapipe: use vk_buffer_range common code. +- llvmpipe/fs: switch to using tgsi->nir instead of handling tgsi +- llvmpipe/analyse: drop TGSI path. +- llvmpipe/fs: start using nir info in some places. +- llvmpipe/fs: drop the simple shader logic +- llvmpipe/fs: rewrite output finding using nir. +- nvk: add build_id linker argument. +- nir/gather: add support for fbfetch and bindless image loads. +- llvmpipe/cs: further cleanups after tgsi removal. +- llvmpipe: move to nir lowering for fquantize2f16 +- rusticl: don't store ptrs to nir_variables across opt passes. +- llvmpipe: enable f16 paths on aarch64. +- clover/llvm: move to modern pass manager. +- nir: use a _clone so users calling their variable clone don't get a warning +- nir: rename nir_inline_functions.c to nir_functions.c +- nir: use nir_function_instructions_pass in the inliner. +- nir: move the libclc lowering over to functions file. +- nir/functions: use helper to get function for a name. +- nir/functions: put link state into a struct +- nir/functions: move linker pass to new helper +- nir: add nir function clone +- nir: don't inline linked functions +- gallivm/nir: split prepasses out to make per-function work easier. +- gallivm: rework translator to allow per-impl work. +- spirv/nir: parse function control and store in nir. +- nir: add driver_functions option to avoid inlining. +- nir: add a function usage tracker +- rusticl: use cleanup funcs +- gallivm: add support for function calling +- llvmpipe/cs: add support for function calls. +- llvmpipe: enable driver functions. +- radv: don't emit event code on video queues. +- spirv: use a pointer sized int type for opencl event_t +- clover: fix parameter arguments since recent translator changes. +- radv/video: take db alignment into account when allocating images. +- ac,radeonsi: move vcn enc structs to common +- ac,radeonsi: move vcn enc av1 default cdf file to common +- nir: add a deref slot counter that handles compact +- llvmpipe/linear: drop tgsi path. +- gallivm: drop tgsi aos paths. +- llvmpipe/nir: call gather info to update inputs read properly +- llvmpipe/fs: start converting interp/input paths to nir. +- llvmpipe/fs: start converting dervied state to nir based. +- llvmpipe/linear: convert to using nir for output. +- llvmpipe/linear: move to nir inputs +- draw/mesh: reset some user state values on mesh draws. +- llvmpipe/fs: fix regression in sample mask handling from tgsi removal. +- llvmpipe: reset viewport_index_slot in fb bind +- llvmpipe/cs: migrate to generic jit texture from pipe code. +- llvmpipe/cs: migrate cs image handle to common jit code. +- lavapipe: fix some whitespace in advance of other changes. +- lavapipe: fix subresource layers asserts +- lavapipe: support host image copying on compressed texture formats +- llvmpipe: don't create texture functions for planar textures. +- lavapipe: don't emit blit src/dst for subsampled formats. +- llvmpipe: don't support planar formats for buffers. +- lavapipe: convert sampler to use vk base class. +- lavapipe: cleanup copy code to use a local region variable. +- lavapipe: start introducing planes structure. +- lavapipe: allocate image and image view planes. +- lavapipe: handle planes in copies +- lavapipe: handle planes in get image sub resource +- lavapipe: add descriptor sets bindings for planar images +- lavapipe: handle planes in texture lowering. +- lavapipe: expose planar ycbcr formats and new ycbcr features +- lavapipe + docs: update ycbcr extension enables. +- intel-clc: avoid using spirv-linker. + +David Heidelberg (82): + +- ci/freedreno: update a530 flakes +- ci: build kernel in gfx-ci/linux and just use binaries in Mesa3D CI +- ci: update kernel to 6.3.13 +- ci/freedreno: add fails introduced by upreving to 6.3.13 +- Revert "lima/ci: temporarily disable deqp-egl tests due to timeouts" +- ci/radeonsi: stoney arb_timer_query got fixed between kernel 6.3.1..13 +- ci/lima: EGL testing was disabled when fp16 fail was removed +- ci/freedreno: fix unexpectedpass flake on a630 +- ci/freedreno: add another a530 flakes +- ci: add quirk for GitLab assuming changes is always true for scheduled runs +- ci/microsoft: when re-enabling Windows Farm, always run the container +- ci/freedreno: add a530 flakes, remove one fail which recently started passing +- ci/panfrost: introduce OpenGL testing with Mali-G57 MP5 on Asurada chromebook +- ci/freedreno: cover all texture gather flakes +- ci/freedreno: add a530 flake vs-lessthanequal-uvec4-uvec4 +- ci/farms: always compare the code against main repository +- Revert "ci/farms: always compare the code against main repository" +- ci/kernel: add amd patch to prevent crashes when starting X +- ci/kdl: remove extra-verbose ls command +- ci/nouveau: add 20 minutes timeout to gk20a and align gm20b +- ci/freedreno: document another mapbuffer flake on a530 +- ci/amd: fix timeouting radeonsi-raven-va-full job +- docs/ci: default to port 80 for the caching proxy +- docs/ci: update to systemd and used version of the trace for testing +- docs/ci: remove default nginx config, which we don't need for proxy +- bin/ci: handle errors more gracefully in update_traces_checksum script +- ci/freedreno: document another flakes on Adreno 530 +- ci: add perfetto into mesa git-cache +- ci/panfrost: re-enable t760 and t860 traces as a nightly job +- CI: Re-enable G52 Vulkan testing +- ci/panfrost: t760-gles is nightly job, test also GLES 3 and 3.1 +- ci/zink: Add flake seen in the wild +- ci/build: limit debian-build-testing to 30 minutes +- ci/amd: add glx\@glx-visuals-depth flake to raven +- ci/freedreno: document vs-nested-return-sibling-loop2 flake on Adreno 530 +- ci/farms: enabled Microsoft job only when conditions are met +- ci/deqp: really remove the uncompressed results.csv file +- ci/baremetal: do not install curl, it's already there +- ci/baremetal: shorten BM_KERNEL to filename and BM_DTB to name only +- ci/freedreno: document another a530 flake batch +- ci: remove LAVA prefix from variables which can be used also elsewhere +- ci/zink: drop a630, which we currently have very low amount available +- ci/freedreno: the tag belongs to the apq8016 only +- ci/freedreno: switch references, the farm-rules takes care about this +- ci/freedreno: handle disabling farm properly for each FD/Collabora farm +- ci/freedreno: another batch of Adreno 530 flakes +- gtest: backport ansi color fix +- ci: disable Material Testers.x86_64_2020.04.08_13.38_frame799.rdc trace +- panfrost/ci: revert Disable T720 +- ci/piglit: add extra space on top to prevent single quote getting into URL +- ci/freedreno: There is only one King of Town. +- ci: switch to 6.4 kernel, improving Adreno 660 reliability +- ci/iris: add GL46.arrays_of_arrays_gl.SizedDeclarationsPrimitive timeout +- ci/panfrost: add G52 flakes +- ci/panfrost: we have enough device, parallelize Vulkan tests +- ci/virgl: flakes in functional.draw_buffers_indexed group +- ci/freedreno: add another a530 flake +- ci/panfrost: add G52 simple_tests.partial_image_pot_same_format_noclear flake +- panvk: architecture isn't invalid, just unsupported +- panvk: catch unsupported arch in the panvk_physical_device_init +- Revert "ci: disable a660 jobs" +- docs: add LAVA farm informations +- ci: disable Google Freedreno farm, currently timeouting on all jobs +- Revert "ci: disable Google Freedreno farm, currently timeouting on all jobs" +- ci/farms: no need to check RUNNER_TAG for Collabora farm +- ci/traces: extend no-output timeout by 5 minutes +- ci/venus: add fragment.32B_in_memory_with_vec4_s32 flake +- iris: do not mention specifically clover for OpenCL support +- ci/freedreno: disable broke cheza (Adreno 630) runners +- ci/bare-metal: correct workaround for R8152 issue while retrieving TFTP data +- ci/bare-metal: drop unused imports, sort, use SPDX license +- ci/lima: farm is down, disable for now +- ci: do not report failed job when flakes reporting fails +- ci/freedreno: re-enable Cheza (Adreno 630) runners +- ci/traces: upload only missing trace images +- ci/traces: keep images for every job except the performance testing +- ci/traces: rename upload function to reflect it works with S3 +- ci/traces: always export piglit EXTRA_ARGS +- ci: ci_marge_queue.py +- ci/freedreno: fix copy paste causing a618_gl being run only in manual pipeline +- ci/freedreno: disable Adreno 660 Vulkan pre-merge +- ci/traces: drop the freedoom-phase2-gl-high.trace + +David Rosca (70): + +- radeonsi: Use DIV_ROUND_UP instead of ALIGN_POT +- frontends/va: Skip processing buffers already converted with EFC +- frontends/va: Don't use EFC with scaling or filtering enabled +- radeonsi/vcn: Don't use chroma in AV1 encode with RGB input +- frontends/va: Parse H264 SPS for video signal parameters +- frontends/va: Parse HEVC SPS for video signal parameters +- frontends/va: Add postproc support for converting to full range +- radeonsi/vcn: Set H264 video signal parameters in bitstream +- radeonsi/vcn: Set HEVC video signal parameters in bitstream +- radeonsi/vcn: Enable full/limited range support for H264/HEVC/AV1 +- radeonsi/vcn: Fix setting color range in AV1 bitstream +- gallium/auxiliary/vl: Fix RGB->YCbCr full range matrix +- gallium/auxiliary/vl: Handle UV subsampling in compute_shader_yuv +- gallium/auxiliary/vl: Fix blurry output of compute_shader_yuv +- frontends/va: Add YUV420 to NV12 postproc conversion +- gallium/auxiliary/vl: Fix chroma and blurry output of cs video_buffer +- gallium/auxiliary/vl: Fix chroma offset of compute_shader_weave +- frontends/va: Also map VAImageBufferType for reading +- frontends/va: Alloc interlaced surface for interlaced pics +- frontends/vdpau: Alloc interlaced surface for interlaced pics +- radeonsi: Don't prefer interlaced for video decode +- ci/amd: Skip VAAPI CreateSurfacesWithConfigAttribs/1121 test +- frontends/va: Don't allow multi-plane derive without driver support +- frontends/va: Init view_resources array in vlVaPut/GetImage +- radeonsi: Copy all planes with multi-plane staging textures +- radeonsi: Enable PIPE_VIDEO_CAP_SUPPORTS_CONTIGUOUS_PLANES_MAP +- ci/amd: Skip all VAAPI tests that creates too many huge surfaces +- radeonsi/vcn: Update rate control when framerate changes with HEVC +- frontends/va: Ignore requested size when creating VAEncCodedBufferType +- gallium/auxiliary/vl: Set correct csc matrix in set_buffer_layer +- radeonsi/vcn: Fix leaking fences in decode +- gallium/auxiliary/vl: Add BT.709 full csc matrix +- frontends/va: Set csc matrix in postproc +- gallium/auxiliary/vl: Don't set csc matrix in video_buffer/rgb_to_yuv_layer +- frontends/va: Add BT.709 as supported postproc color standard +- Revert "radeonsi/vcn: add an exception of field case for h264 decoding" +- gallium/auxiliary/vl: Set vertex element src_stride in vl_deint_filter +- gallium/auxiliary: Fix util_compute_blit half texel offset with scaling +- gallium/auxiliary/vl: Map range when updating constants +- gallium/auxiliary/vl: Clamp coordinates in compute shaders +- gallium/auxiliary/vl: Support chroma sample location in compute shaders +- frontends/va: Support chroma sample location in postproc +- frontends/va: Flush after unmapping VAImageBufferType +- frontends/va: Parse chroma sample location in H264/HEVC SPS +- radeonsi/vcn: Set H264/HEVC chroma sample location in bitstream +- radeonsi/vcn: Don't hang GPU when using DCC surface as encoder input +- frontends/va: Track surfaces in context +- frontends/va: Destroy fences when destroying surface or context +- radeonsi/vcn: Implement destroy_fence vfunc +- frontends/va: Process VAEncSequenceParameterBufferType first in vaRenderPicture +- frontends/va: Set default rate control values once when creating encoder +- gallium/auxiliary/vl: Add RGB to YUV compute shader +- gallium/auxiliary/vl: Use chroma offset in YUV to RGB weave compute shader +- gallium/auxiliary/vl: Fix YUV to RGB bob compute shader deinterlacing +- gallium/auxiliary/vl: Only map the shader constants buffer in render +- frontends/va: Add High Quality preset mode +- radeonsi/vcn: Add High Quality encoding preset for AV1 +- radeonsi: Fix plane size in si_copy_multi_plane_texture +- frontends/va: Implement vaMapBuffer2 +- frontends/va: Fix locking in vlVaBeginPicture +- frontends/va: Parse H264 SPS for max_num_reorder_frames +- util/vl: Fix vl_rbsp parser with bitstreams without emulation bytes +- frontends/va: Fix parsing packed headers without emulation bytes +- radeonsi/vcn: Add encode support for H264 B-frames +- frontends/va: Map decoder and postproc surfaces for reading +- radeonsi: Fix offset for linear surfaces on GFX < 9 +- gallium/auxiliary/vl: Fix coordinates clamp in compute shaders +- gallium/auxiliary: Fix coordinates clamp in util_compute_blit +- gallium/auxiliary/vl: Scale dst_rect x0/y0 when rendering chroma plane +- util/rbsp: Fill bits twice if reading more than 16 bits + +Derek Foreman (2): + +- vulkan/wsi: Allow binding presentation_timing when software rendering +- vulkan/wsi: warn about unset present_mode in PresentModeCompatibilityExt + +Dmitry Baryshkov (3): + +- gallium: move kmsro definition to the bottom of the file +- gallium: unbreak kmsro/freedreno case +- tu: Pass real size of prime buffers to allocator + +Dmitry Osipenko (3): + +- util/cache_test: Re-add test for disabled cache +- util/cache_test: Fix disabled cache test using SHADER_CACHE_DISABLE_BY_DEFAULT +- util/cache_test: Add test for get/put() with disabled cache + +Dor Askayo (1): + +- nouveau: add exported GEM handles to the global list + +Dr. David Alan Gilbert (6): + +- rusticl/core: Add profiling time storage (queued) to event +- rusticl: Wire the 'queued' profiling time up +- rusticl: Wire the 'submit' profiling time up +- rusticl: Wrap pipe queries +- rusticl: Wrap pipe query reads +- rusticl: Wire the 'start' and 'end' profilng times up + +Dylan Baker (4): + +- VERSION: bump to 23.3.0-devel +- docs: Update release calendar for 23.2.0-rc1 +- docs: truncate feature list for 23.3-devel +- meson: use a single dependency call for lua + +Echo J (5): + +- nvk: Fix some cast defines +- nvk: Add A8B8G8R8_*_PACK32 format support +- nvk: Add bufferImageGranularity limit +- nvk: Reset offset value in ResetDescriptorPool +- nil: Add A4B4G4R4_UNORM format support + +Emma Anholt (111): + +- ci/radv: Clarify when the ANGLE GS failures started happening. +- ci: Uprev ANGLE to 0518a3ff4d4e ("Android: Simplify power metrics collection") +- ci/tgl: Improve the info for ANGLE's MSAA regression on TGL. +- ci/tu: Add more crash cases for the multithreading bugs caught on a630. +- ci/tu: Mark descriptor_buffer.basic.limits as failing in gmem too. +- ci/tu: Drop some xfails for !24086 +- tu: Fix data race in userspace VMA management. +- ci/a5xx: Add another GPU hanging piglit test to the skips. +- Revert "ci: Disable nouveau CI" +- nvk: Avoid strict aliasing warning in the pushbuffer encoding. +- nvk: Fix uninitialized result usage in NVK_DEBUG_ZERO_MEMORY. +- nvk: Fix unused result warnings in pushbuf resets. +- nvk: Remove duplicate (disabled) point sprite setup. +- nvk: Fix missing init of the stages to sync against. +- nvk: Use depth_clamp_enable to select PIXEL_*_Z_CLAMP. +- nouveau/winsys: Fix an undefined use in the error path. +- nvk: Quiet a compiler warning. +- nvk: Clean up redundant vendor checking for physical device creation. +- nvk: Add support for probing as a platform device. +- nvk: Disable shaderStorageImageReadWithoutFormat pre-Maxwell. +- freedreno/a5xx: Fix border color structure size. +- freedreno/a5xx: Skip emitting unused texture descriptors for images. +- freedreno/ir3: Move pvtmem per-fiber size alignment to the compiler. +- ci/freedreno: Drop a bunch of stale a530 xfails. +- ci/freedreno: Sort another a530 xfail with its friends. +- ci/freedreno: Update comments for some a530 xfails. +- ci/freedreno: Add some more db820c xfails. +- freedreno/devices: Move fibers_per_sp to the common info struct. +- freedreno/devices: Set num_sp_cores explicitly for pre-gen6. +- freedreno/a6xx: Move pvtmem allocation to ir3_gallium. +- freedreno/a3xx: Add the shift for MEMSIZEPERITEM according to db410c docs. +- freedreno/a5xx: Refactor SHADER_OBJ emit to a helper function. +- freedreno/a5xx: Set num_sp_cores and set PC/VFD_POWER_CNTL accordingly. +- freedreno/a5xx: Add private mem support. +- freedreno/cffdec: Fix decode on pixel 2 blob's COMPUTE_CHECKPOINT +- ci/freedreno: Add a regression test for decoding a540 blob's compute shaders. +- freedreno: Fix crashdec pre-a6xx. +- freedreno/a5xx: Skip SSBO emit when none are enabled. +- vulkan/util: Make multialloc succeed with 0 allocations. +- turnip: Track the first/last subpass an attachment is used in. +- turnip: Skip emitting empty CP_COND_REG_EXEC. +- turnip: Save the renderpass's clear values in the cmdbuf state. +- turnip: Move gmem clears and loads to the first subpass that uses them. +- turnip: Move sysmem clears to the first subpass that uses them. +- ci/freedreno: Skip some tests on a5xx that destabilize other tests. +- freedreno/a3-5xx: Don't try to emit ISAM for SSBO loads. +- ci/turnip: Add a660 VK coverage. +- disk_cache: Disable the "List" test for RO disk cache. +- blorp: Disable unaligned partial HIZ fast clears for HIZ_CCS too. +- intel/fs: Move defin/defout setup to the start of the loop. +- intel/fs: Move the defin[]/defout[] screening up to livein[]/liveout[] setup. +- intel/fs: Simplify compute_start_end(). +- ci/freedreno: Add another excessive-constlen UBO skip. +- ci/anv: Drop DEQP_VER:vk setting. +- ci/anv: Drop "-vk" from the job name. +- ci/anv: Add a manual full VK run for TGL. +- ci/anv: Add testing on JSL. +- freedreno: Build drm subdir before perfcntrs, which uses it. +- ci/intel: Add various updates from our nightly runs. +- ci/virgl: Disable virgl-iris-traces. +- ci/zink: Add a few updates for anv/tgl from the nightly runs. +- ci/fastboot: Use a case insensitive match for a fastboot line. +- ci/etnaviv: Skip some tests that hang the GPU and knock out other tests. +- ci/etnaviv: Drop some gc2k flakes that I think are resolved. +- ci/anv: Drop incorrect xfail addition for TGL +- ci/anv: Drop the 16bit.scalar.13 skip. +- ci/etnaviv: Minor xfail/flake polishing. +- ci/etnaviv: Skip a GLES2 test that times out the asan job. +- ci/zink: Skip more doubles tests on anv that flake at 3 minute timeouts. +- ci/docker: Clear the results file before starting a new deqp test run. +- ci/crocus: Add a related flake to a known one. +- ci/etnaviv: return gl-1.4-tex1d-2dborder as a known flake +- ci/crocus: Add known piglit flakes +- ci/hasvk: Add a bunch of new CTS border color fails. +- i915: Re-clang-format and enforce it in CI. +- i915: Print the relevant counts vs limits when throwing errors. +- i915: Don't log I915_DEBUG=fs output for blit shaders. +- i915: Save fragment program compile error messages in the fragment shader. +- i915: Do a test compile at glLinkShader() time. +- i915: Make exceeding tex indirect count fatal. +- i915: Use nir_group_loads() to reduce texture indirection phases. +- ci/crocus: Generalize the drawarrays-vertex-count flakes. +- ci/zink: Skip 3-minute-long glx-visuals timeouts. +- ci/zink: Skip dmat[34] op tests in general, as well +- ci/crocus: Disable flaky unvanquished-ultra trace +- nir/print: Decode system values in the variable declarations. +- ci/zink: Add a TGL flake that's showed up in nightlies recently. +- ci/radeonsi: Drop an xfail for vangogh. +- i915: Make I915_DEBUG=fs log shaders that fail to link due to CF. +- nir: Flatten ifs with discards in nir_opt_peephole_select for HW without CF. +- glsl: Remove lower_discard(). +- ci/zink: Only test half of piglit pre-merge on anv. +- ci: Stop doing internal retries in bare-metal. +- ci/bare-metal: Drop the 2 vs 1 exit code from poe_run. +- ci/bare-metal: Default our boards to a 20-minute timeout for the whole job. +- ci/iris: Drop parallel on kbl piglit to 2. +- ci/freedreno: Fold a630_egl into a630_gl. +- ci/freedreno: Move skqp testing to a618. +- ci/zink: Cut zink-lvp coverage in half. +- ci/freedreno: Generalize the implicit_unmap timeouts. +- ci_run_n_monitor: Poll mesa/mesa and user/mesa for pipelines at the same time. +- glx: Delete support for GLX_OML_swap_method. +- ci: drop skip for glx-swap-copy. +- dri: Drop a duplicate mesa vs pipe format table. +- docs/ci: Drop old instructions for farm disabling +- docs/ci: Add some links in the CI docs to how to track job flakes +- glsl: Remove int64 div/mod lowering. +- llvmpipe: Set nir_lower_dround_even. +- nir: Add nir_lower_dsign as 64-bit fsign lowering. +- glsl: Retire dround lowering. +- ci_run_n_monitor: Always resolve --rev arguments for looking up pipelines. + +Eric Engestrom (194): + +- ci: avoid running hardware jobs if lint fails - now on LAVA too! +- ci: avoid running hardware jobs if lint fails - now on Windows too! +- ci: replace copy of nouveau rules with reference +- ci: drop leftover kernel configs +- ci: use !reference for scheduled_pipeline retry rule +- ci: add .llvmpipe-manual-rules and use it +- ci: add .gallium-core-rules and use it instead of gallium_core_file_list anchor +- ci: replace llvmpipe_file_list anchor with reference +- ci: replace softpipe_file_list anchor with reference +- ci: replace lavapipe_file_list anchor with reference +- ci: replace iris_file_list anchor with reference +- ci: replace radv_file_list anchor with reference +- ci: replace radeonsi_file_list anchor with reference +- ci: replace virgl_file_list anchor with reference +- ci: move etnaviv files rules to src/etnaviv/ci/gitlab-ci.yml +- ci: move freedreno files rules to src/freedreno/ci/gitlab-ci.yml +- ci: move nouveau files rules to src/gallium/drivers/nouveau/ci/gitlab-ci.yml +- ci: move panfrost files rules to src/panfrost/ci/gitlab-ci.yml +- ci: move broadcom files rules to src/broadcom/ci/gitlab-ci.yml +- ci: move lima files rules to src/gallium/drivers/lima/ci/gitlab-ci.yml +- ci: move amd files rules to src/amd/ci/gitlab-ci.yml +- ci: move microsoft files rules to src/microsoft/ci/gitlab-ci.yml +- ci: move zink files rules to src/gallium/drivers/zink/ci/gitlab-ci.yml +- ci: move virtio files rules to src/virtio/ci/gitlab-ci.yml +- ci: move intel files rules to src/intel/ci/gitlab-ci.yml +- ci: move virgl files rules to src/gallium/drivers/virgl/ci/gitlab-ci.yml +- ci: move llvmpipe files rules to src/gallium/drivers/llvmpipe/ci/gitlab-ci.yml +- ci: move softpipe files rules to src/gallium/drivers/softpipe/ci/gitlab-ci.yml +- ci: move lavapipe files rules to src/gallium/drivers/lavapipe/ci/gitlab-ci.yml +- ci: delete install.tar after extracting it to avoid re-uploading it +- docs: add release notes for 23.1.4 +- docs: add sha256sum for 23.1.4 +- docs: update calendar for 23.1.4 +- asahi: drop unused include paths +- ci/lint: deduplicate formatting check jobs +- ci/lint: also print a diff for rust format issues +- ci: allow hw jobs even if lint jobs fail for non-Marge pipelines +- ci: print rustfmt's version +- ci: print clang-format's version +- bin/ci_run_n_monitor: get git sha from pipeline if specified, instead of requiring --rev to match +- lavapipe/ci: use tighter changes: rules +- ci: add a 10min job timeout to formatting checks +- ci: reduce bare-metal retries of poe_run to only 3 attempts +- broadcom/ci: reduce vc4-rpi3-gl timeout to 30min (instead of 1h) +- broadcom/ci: reduce v3d-rpi4-gl timeout to 30min (instead of 1h) +- broadcom/ci: reduce v3d-rpi4-traces timeout to 30min (instead of 1h) +- broadcom/ci: reduce v3dv-rpi4-vk timeout to 30min (instead of 1h) +- ci: add .core-rules to .gallium-core-rules +- ci: drop rule for non-existent src/include/ +- docs: add release notes for 23.1.5 +- docs: add sha256sum for 23.1.5 +- docs: update calendar for 23.1.5 +- ci: include some timing information in the git cache download script +- docs/ci: stop trying to enumerate drivers that are tested using VK-GL-CTS +- docs/ci: in paragraph about the CI being overwhelmed, mention our tool to help with that +- docs/ci: drop mention of build systems variants in the CI +- docs/ci: expand the description of test suites +- bin: add wrapper to run scripts in a python venv +- bin/ci/ci_run_n_monitor: use venv wrapper +- bin/ci/gitlab_gql: use venv wrapper +- bin/ci/update_traces_checksum: use venv wrapper +- bin/pick-ui: use venv wrapper +- ci: include mold in x86_64_test-base & rootfs images +- ci: use mold to build deqp +- zink/ci: set the default timeout for zink jobs to 30min instead of 1h +- egl: make _eglFilterConfigArray static +- egl: fixup _eglFilterConfigArray() params and drop _eglFallbackMatch() wrapper +- ci: build nvk +- ci: document max image tag length +- docs/radv: mark VK_EXT_tooling_info as implemented +- docs/radv: mark VK_INTEL_shader_integer_functions2 as implemented +- git-blame-ignore-revs: repeat instruction on how to enable to avoid having to look for it +- git-blame-ignore-revs: add radv formatting commit +- git-blame-ignore-revs: add pvr formatting commit +- meson: fix indentation +- docs/v3dv: mark direct display extensions as implemented +- ci: reorder vk drivers alphabetically in debian-vulkan job +- ci: build hasvk in debian-vulkan job +- ci/zink+radv: set a timeout of 2x the normal runtime +- amd/ci: drop duplicate test expectations +- panfrost: upcast uint8/uint16 before shifting them beyond their range +- ci/a530: document piglit flake +- docs: add release notes for 23.1.6 +- docs: add sha256sum for 23.1.6 +- docs: update calendar for 23.1.6 +- docs: add one more 23.1.x release +- ci: rename \*.log to \*.txt to work around gitlab bug +- ci/freedreno: reuse freedreno_gl_file_list instead of re-definining it +- egl: bump extension string length +- vc4: drop duplicate .lower_ldexp +- zink: fix format in zink_make_{image,texture}_handle_resident() +- v3dv: fix VK_PIPELINE_ROBUSTNESS_{BUFFER,IMAGE}_BEHAVIOR_DEVICE_DEFAULT_EXT copy/paste typo +- v3dv: fix copy/pasted type of \`sample` +- v3dv: fix shader stage name in error message +- v3d/qpu: fix type of function argument +- ci/deqp: backport fix for dEQP-EGL.functional.wide_color.*_888_colorspace_* +- ci/farm-rules: fix missing valve-infra jobs in scheduled pipelines +- bin/ci_run_n_monitor: error out if both --project and --pipeline-url are passed +- ci: document farm rules +- ci/b2c: skip install.tar extraction if the tarball is not present +- ci/b2c: don't allow failures in test script preparation +- ci/b2c: assert that install folder is present whether or not the tarball was extracted +- ci/amd: split the polaris10 rules into one for each farm +- ci: skip containers & build jobs when disabling a farm +- docs: add release notes for 23.1.7 +- docs: add sha256sum for 23.1.7 +- docs: update calendar for 23.1.7 +- docs: add one more 23.1.x release +- ci: taking igalia farm offline +- ci/b2c: drop logic to remove install.tar +- ci: drop clover leftover +- Revert "ci: taking igalia farm offline" +- bin/ci_run_n_monitor: print in which repo we're looking for the pipeline +- bin/ci_run_n_monitor: automatically pick MR pipelines when they exist +- ci: remove duplicate fork pipeline in MRs +- ci_run_n_monitor: add comment to explain "MR > fork" logic +- ci: don't run everything just because a farm gets re-enabled +- ci/windows: centralize definition of windows runners tags +- ci/windows: add windows docker runner tags to .windows-docker-vs2019 +- ci/windows: drop build rules from test jobs +- ci: document which image tags need to be bumped when updating piglit +- ci: document which image tags need to be bumped when updating {alpine,debian,fedora}/x86_64 +- ci/farm-rules: rename .disable-farm-mr-rules to make it clear it's only about MRs +- ci/farm-rules: re-add "run every container and build job when a farm gets re-enabled" +- ci/zink: drop redundant \`MESA_LOADER_DRIVER_OVERRIDE: zink` +- docs: add release notes for 23.1.8 +- docs: add sha256sum for 23.1.8 +- docs: update calendar for 23.1.8 +- docs: add another 23.1.x +- ci: limit build jobs to 30min so that they can retry when they go wrong +- docs: drop outdated and redundant note about the minimum meson version +- ci/zink+radv: specify that zink-radv-navi10-valve should run in the mupuf farm +- ci/zink+radv: bump the timeout of zink-radv-navi10-valve by 10 minutes +- docs: add calendar for 23.3 +- ci: unify container and build jobs rules +- docs/meson: drop mention that our meson is ready +- ci/docs: drop extra overwritten rules +- ci/zink+radv: document flake +- docs: document the merging process and what is allowed or not +- ci: drop unused shader-db clone + build from alpine image +- ci: drop unused shader-db clone + build from fedora image +- ci: move shader-db clone/build into its own script +- ci/deqp-runner: fix indentation +- ci/deqp-runner: restore exit-on-error after getting deqp-runner's exit code +- ci: fix shebang in build-deqp-runner.sh +- docs: add release notes for 23.1.9 +- docs: add sha256sum for 23.1.9 +- docs: update calendar for 23.1.9 +- ci: drop unused ephemeral packages in alpine image +- docs/ci: rewrite the "farm maintenance ^ other change" rule to mean what we actually meant +- ci: skip dEQP-VK.api.driver_properties.conformance_version for everyone +- pick-ui: use assignment expressions +- pick-ui: use more expressive variable names +- pick-ui: add \`Backport-to: XX.Y` nomination +- v3d/ci: move traces job to wayland +- ci: print deqp version in the job log +- ci/b2c: move to the shiny new \`gfx-ci/ci-tron` repo +- ci/b2c: use latest mesa-trigger image +- include/dri_interface.h: restore define mistakenly removed in !25587 +- ci_run_n_monitor: dependency jobs must always be started +- util/xmlconfig: drop driInjectDataDir() now that DRIRC_CONFIGDIR is always supported +- util/xmlconfig: inline datadir +- ci/b2c: change artifacts path to match baremetal and LAVA +- VERSION: bump for rc1 +- .pick_status.json: Update to e64a97694ac9dc97f65e1a8e91a5c9789109fd2c +- .pick_status.json: Update to 4cdd094ae1e97d857a6b9dbc291d7bbe6ea266ac +- .pick_status.json: Update to e4a1bc70dd739ca8addddc940af08312b038e288 +- .pick_status.json: Update to faed5d647f2416bb0ce3a9d33a3955169c70dc52 +- VERSION: bump for 23.3.0-rc2 +- .pick_status.json: Update to 1f1ec1c6bcc2a32a3c1df8c2cc7a2f4e7139b7ec +- .pick_status.json: Mark 8dda860f83ac30d042dc6beb4438cc925d1fd130 as denominated +- .pick_status.json: Update to 7d6f9ccfbeab050c26775d5e03578a01526cbfcb +- .pick_status.json: Update to aa33ca0a52591961f8ae01dc253354462ed17c18 +- .pick_status.json: Update to a77ea9555aa00cc12f3d1c440252e940ff552500 +- .pick_status.json: Mark 227300345ed38377190b0eaf08694d5c42ee7e60 as denominated +- VERSION: bump for 23.3.0-rc3 +- .pick_status.json: Update to 56451ce773c11094a8c08fdc6b500bb8bdcf37e1 +- .pick_status.json: Mark fa7ec4226bdf48bf63438e303af83ecd58ec95f2 as denominated +- .pick_status.json: Update to 08f851f4361cfbdb211dc70d03cf3ebff331c3ee +- .pick_status.json: Update to 03a7cb261828b350dd9b56bd74850197ca9eba33 +- .pick_status.json: Mark fcfa68a632e5711cc657b103c9a0384928e9bf49 as denominated +- VERSION: bump for 23.3.0-rc4 +- .pick_status.json: Update to f05688aa3299a27430119b27e45181a6f415bff8 +- egl/dri2: increase NUM_ATTRIBS to fit all the attributes +- .pick_status.json: Update to f39ed0063b4cd3e5a71efad2d43ce31f574c698d +- .pick_status.json: Update to b07a58157d0b110dbc09a42cffe7046c3200dd3b +- VERSION: bump for 23.3.0-rc5 +- .pick_status.json: Update to f843b14c171299e1696ca6d971ccaa496f60c3ab +- intel/perf: fix regex escaping +- intel/ci: fix .hasvk-manual-rules +- VERSION: bump for 23.3.0 +- Revert "VERSION: bump for 23.3.0" +- docs: add release notes for 23.3.0 +- Revert "docs: add release notes for 23.3.0" + +Erico Nunes (10): + +- lima/ppir: don't optimize loads with different block successors +- lima/ppir: convert to nir_legacy +- lima/gpir: switch to register intrinsics +- egl/drm: fix EGL_EXT_buffer_age with gbm contexts +- lima: fix plbu block stride calculation +- ci: disable lima LAVA lab for maintance +- Revert "ci: disable lima LAVA lab for maintance" +- v3dv: allow headless device without display device +- Revert "ci/lima: farm is down, disable for now" +- v3dv: Rework to remove drm authentication for wsi + +Erik Faye-Lund (30): + +- meson: report with_glvnd in summary +- docs: upgrade bootstrap to 5.3.1 +- docs: expand mobile-menu without js +- panfrost: delete stale editorconfig file +- docs/panfrost: link to lima +- docs/panfrost: use code-blocks with wrapping for long blocks +- docs/panfrost: use math-role to denote powers of two +- docs: fix linkcheck +- docs: update a few links to https +- docs: update anchor for link +- docs: update link to git-wiki +- docs: link to upstream etnaviv +- docs: apply some trivial redirects +- docs: use doc-role when linking to lists article +- docs: keep up with intels ever-moving documentation +- docs: mark some redirects as allowed +- docs: only link to old docs from html +- docs: use html_static_path for static files +- ci/etnaviv: update ci expectation +- ci/etnaviv: allow failure on failing test +- zink: fix wording of warning +- ci/etnaviv: move failure to flake +- meson: add wayland-protocols from meson wrapdb +- util/xmlconfig: add an env-var for overriding drirc search dir +- meson: add src/util to the drirc search path +- docs/relnotes: remove cruft from end of lines +- docs/ci: escape at-symbols +- docs/relnotes: escape some at-symbols +- bin/gen_release_notes: escape at-symbols +- panfrost: use perf_debug instead of open-coding + +Faith Ekstrand (809): + +- nv50/ir: Convert to new-style NIR registers +- nv50/ir: Support vector movs +- intel/fs: Add support for new-style registers +- intel/vec4: Assume get_nir_dest() provides a sane write-mask +- intel/vec4: Add support for new-style registers +- intel: Switch to intrinsic-based registers +- intel/fs: Drop support for nir_register +- intel/vec4: Drop support for nir_register +- anv,hasvk,iris: sampler_prog_key::swizzles is only used on crocus +- nir: Properly handle divergence for load_reg +- nir/trivialize: Maintain divergence information +- nir/trivialize: Trivialize cross-block loads +- vc4: Convert to new-style NIR registers +- nir/schedule: Support load/store_reg +- broadcom/compiler: Convert to new-style NIR registers +- intel/fs: Use write masks from store_reg intrinsics +- intel/fs: Rework the overlapping mov/vec case +- intel/fs: Assume NIR is in SSA form +- nir: Add a backend_flags field to nir_tex_instr +- intel/fs: Add a parameter to speed up register spilling +- nir/builder: Allow tex helpers on image types +- nir/builder: Add a nir_txs_deref() helper +- vulkan: Add a core vk_buffer_view struct +- vulkan: Add a more direct way to use a NIR shader +- vulkan: Add a vk_query_pool base object +- vulkan: Add common vkCmdBegin/EndQuery wrappers +- vulkan/format: Add the remaining 1-plane YCbCr formats +- vulkan: Add a core vk_sampler struct +- nv50/nir: Lower to scratch AFTER optimization +- nouveau: Allow GLSL_SAMPLER_DIM_SUBPASS* +- nouveau/nir: Implement support for compact arrays +- nouveau/codegen: Handle/indirect goes before sample index +- nouveau/codegen: Use a NULL format for PIPE_FORMAT_NONE for images +- nouveau/codegen: Don't convertSurfaceFormat for unknown formats +- nv50/ir: Run nir_divergence_analysis before out-of-SSA +- anv: Use vk_sampler +- anv: Use vk_buffer_view +- vulkan: Add init/finish helpers for vk_query_pool +- anv: Use vk_query_pool +- anv: Use the common versions of vkBegin/EndQuery() +- nir/builder: Don't assume we have compiler options +- Revert "mesa, compiler: Move gl_texture_index to glsl_types.h" +- Revert "compiler: Combine duplicated implementation of is_gl_identifier into glsl_types.h" +- vulkan: Use VkBufferUsageFlags2 in vk_buffer +- clang-format: Set ColumnLimit to 78 +- nvk: Implement EnumerateInstanceVersion +- nvk: Add stub implementations of VkImage and VkImageView +- nvk: Add stub implementation of VkSampler +- nvk: Add a stub implementation of VkBuffer +- nvk: Implement VkDescriptorSetLayout +- nvk: Implement VkPipelineLayout +- nvk: Add initial descriptor set lowering +- nvk: Implement vkUpdateDescriptorSets +- nvk: Expose nvk_descriptor_stride_align_for_type +- nvk: Re-format descriptor set layouts +- nvk: Re-format pipeline layouts +- nvk: Re-format descriptor sets some more +- nvk/buffer: Take an offset in nvk_buffer_address +- nvk/buffer: Add a push_buffer_ref helper +- nvk/copy: Use nvk_buffer_address in CmdCopyBuffer +- nvk/image: Add image address helpers +- nvk/copy: Use nvk_image_base_address() +- nvk: Add an nvk_device_physical helper +- nvk: Add a skeleton for pipelines +- nvk: Re-arrange nvk_descriptor_set.h a bit +- nvk: Reformat nvk_nir_lower_descriptors +- nvk: Add a couple descriptor set address helpers +- nvk: Move nvk_cmd_pool cast definitions +- nvk: Rework whitespace in nvk_cmd_buffer.c +- nvk: Add a root descriptor table +- nvk: Fetch descriptor set addresses from the root table +- nvk: Re-arrange nir_lower_explicit_io a bit +- nvk: Lower load_global_constant_offset +- nvk: Drop image_view_init +- nvk: Stop returning VK_ERROR_FORMAT_NOT_SUPPORTED for non-blitable +- nvk: Allow R32_UINT +- nvk: Mark nvk_push_descriptor_set_ref() inline +- nvk: Add a descriptor table data structure +- nvk: Copy in the nouveau TIC format table +- nvk/image_view: Reformat and fix Create/DestroyImageView +- nvk: Add an image descriptor table to the device +- nvk: Fill out TIC table entries for image views +- nvk: Set b->cursor when lowering image intrinsics +- nvk: Unify descriptor loading in lower_descriptors +- nvk: Re-format nvk_image_view.h a bit +- nvk: Re-format nvk_buffer.c a bit +- nvk: Add a stub implementation of buffer views +- nvk: Make texture descriptors a bit more acceptable to codegen +- nvk: GART os host-cache-coherent +- nvk: Reserve a null image descriptor +- nvk: Rework descriptor writes +- nouveau: Add stubs for an image layout library called NIL +- nil: Create images +- nil: Add the TIC format table from nouveau +- nil: Add a nil_view and code to fill out TIC entries +- nvk: Add an nvk_get_format helper +- nvk: Use helpers for push_ref +- nvk: Align arguments consistently in copy/blit code +- nvk: Move Fill/UpdateBuffer to nvk_cmd_copy +- Revert "nvk: Stop returning VK_ERROR_FORMAT_NOT_SUPPORTED for non-blitable" +- nvk: Manually offset for array layers in copy/blit +- nvk: Convert to using NIL for image layout +- nvk: Re-indent image entrypoints +- nvk: Implement VkGetImageSubresourceLyout +- nvk: Reset and properly clean up command buffer upload areas +- nvk: Rework format features queries +- nvk: Add a more competent GetPhysicalDeviceImageFormatProperties +- nvk: Support compressed images in copy commands +- nvk: Drop vk_sync BO refs after push_submit +- nil: Drop miptail support for now +- nil: Don't minify image dimensions when setting up TIC +- nil: Refactor TIC image extent setup +- nil: Fix image array layer alignments +- nvk: Teture pool sizes are maximums not sizes +- nvk: Re-format nvk_sampler.c +- nvk: Implement samplers +- nil: Add a helper for filling out buffer TIC entries +- nvk: Move is_storage_image_format to nvk_format.c +- nvk: Implement buffer views +- nvk: Advertise KHR_dedicated_allocation +- nvk: Use the correct root descriptor table size for CmdDispatch +- nvk: Add support for dynamic buffers +- nvk: Better advertise image format features +- nvk: Advertise descriptor array indexing +- nvk: Advertise non-zero descriptor set limits +- nvk: Use a descriptor type instead of a hand-rolled thing +- nvk: Handle cube storage images properly +- nvk: Load the requested descriptor size +- nvk: Implement push constants +- nvk: Properly indent a comment +- nvk: Fix descriptor offset alignment +- nvk: Use a switch for descriptor types in load_descriptor +- nvk: Support inline uniform blocks +- nvk: Delete the storage TIC in nvk_image_view_destroy +- nvk: Assert that we don't double-free descriptors +- nvk: Initial vkCmdClearImage support +- nvk: Unconditionally zero image format properties +- nvk: No-op sparse image format properties +- nvk: Advertise minUniformBufferOffsetAlignment +- nvk: Rework OOM handling for descriptor pools +- nvk: Bind immutable samplers on descriptor set creation +- nvk: Padd shader BOs by 4K to avoid I-cache overflow +- nvk: Include nvk_private.h in everything +- nvk: Make image/buffer address helpers const +- nouveau/push: Add a P_INLINE_FLOAT helper +- nvk: Init WSI after setting up supported_sync_types +- nouveau/parser: Fix an integer overflow and a typo +- nouveau/parser: Properly dump most arrays used by 3D +- nouveau/parser: Better dump float data +- nouveau/parser: Handle arrays properly in P_IMMD() +- nouveau/push: Make P_IMMD more versatile +- nouveau: Null terminate the debug flag list +- nouveau: Generate 3D headers +- nvk: Add graphics state to command buffers +- nvk: Split pipeline binding into helpers +- nvk: Switch to vk_pipeline_shader_stage_to_nir +- nvk: Don't free the NIR in nvk_compile_nir +- nvk: Add an nvk_shader_address helper +- nvk: Free pipeline shader BOs +- nvk: Expose pipeline alloc/free functions +- nvk: Make shader_upload take an nvk_device +- nvk/shader: Assign I/O locations and gather info +- nvk/shader: Populate headers for vertex and fragment shaders +- nvk: Add a nvk_cmd_buffer_device() helper +- nvk: Import 3D context init code from nouveau +- nil/format: Add helpers for render formats +- nvk: Add boilerplate for Begin/EndRendering +- nvk: Misc. additional state setup +- nvk: Emit dynamic graphics state +- nvk: Implement push constants and descriptors for graphics +- nouveau: Add CPU push buffers +- nvk: Graphics pipelines +- nvk: Implement vkCmdDraw() +- nvk: Color attachments clears via image clears +- vulkan/meta: Add the start of a meta framework +- vulkan/meta: Add an object tracking list +- vulkan/meta: Add a concept of rect pipelines +- vulkan/meta: Implement attachment clears +- vulkan/meta: Implement start-of-rendering clears +- vulkan/meta: Add implementations of Clear*Image +- nvk: Add an attachment format even for secondaries +- nvk: Add an addr field to nvk_buffer +- nvk: Expose a bind_vertex_buffer helper +- nvk: Use vk_meta for CmdClearAttachments +- nvk: Stop using vk_cmd_set_dynamic_graphics_state in meta_end() +- nvk: Enable all the dynamic state features +- nouveau: Fix pushbuf ref reset for user command buffers +- nvk: add linear image creation support. +- nvk: Use max alignment for descriptor pool sizes +- nil: Switch to using the new headers for TIC entries +- nvk: Use meta for CmdClear*Image +- nvk: Zero client memory objects +- nvk: Bind texture and sampler header pools for 3D +- nvk: Use the new headers for samplers +- nvk: Implement nir_intrinsic_load_frag_coord +- vulkan/meta_clear: Populate VkRenderingInfo::renderArea +- nvk: Don't assert when there are no attachments +- nvk: Track and reference all device memory objects +- vulkan: Allow scissors or viewports to be set without counts +- nvk/copy: Mape bpp part of nouveau_copy_buffer +- nvk: Implement copies for D24_UNORM_S8_UINT images +- nvk: Drop sample locations structs +- nvk/meta: Save and restore VI state +- nvk: Re-initialize dynamic_graphics_state.vi when recycling +- nvk: Move the vertex format table into nvk_format.h +- nvk: Advertise vertex buffer format featues +- nvk: Clean up try_create_physical_device error handling +- nouveau/parser: Dump more fields as float +- nvk: Depth bounds need fui() +- nouveau: Add class information to nouveau_ws_device +- nil: Properly depend on nouveau winsys and nvidia-headers +- nil: Use nvidia headers for texture format enums +- nil: Use the nvidia headers for render target format enums +- nil: Use nvidia headers for ZS format enums +- nil: Rename rt to czt in the format info struct +- nil: Rename rendering to color_target +- nil: Re-introduce the format capabilities +- nil: Add more format support helpers +- nvk: Advertise more format features +- nvk: Clear dynamic state dirty after flushing it all +- vulkan/meta: Make stencil reference dynamic for clears +- nvk: Depth buffers don't allow Z-tiling +- nvk: Disable sparse Z on Maxwell+ +- nil: Compute PTE kinds and tile modes for images +- nouveau: Add a function to allocate a tiled buffer +- nvk: Add internal helpers for device memory allocation +- nvk: Do internal dedicated allocations for ZS images +- nvk: Fix depth/stencil render pass clears +- nvk: Fix viewport Z scale +- nvk: Enable two-sided stencil +- nvk: Flip the front-face setting +- nvk: Advertise depth/stencil support +- nvk: Don't destroy NULL descriptor pool BOs +- nvk: Call nir_lower_input_attachments +- nvk: Set GEOMETRY_SHADER_SELECTS_LAYER properly +- nvk: Return OUT_OF_DEVICE_MEMORY if bo_new fails +- nil: Add a PTE kind for Z32_FLOAT +- nvk: Add nvk_queue_init/finish() helpers +- nvk: Align descriptor buffers to NVK_MIN_UBO_ALIGNMENT +- nvk: Re-flow a couple function prototypes +- nvk: Assert samples == 1 +- nvk: Allocate descriptors for input attachments +- nvk: Wire up early z and post depth coverage +- nvk: Save/restore push constants around meta ops +- nouveau/parser: Add array and float tags for clear values +- nvk: Use hardware clears for attachment clears +- nvk: Add image_view_init/finish functions +- nvk: Implement vkCmdClear*Image directly +- nvk: Use a UINT format to clear non-renderable images +- nvk: Don't advertise tiling on non-power-of-two formats +- nvk: Fix max anisotropy +- nvk: Assert on CmdExecuteCommands +- nvk: VkSamplerCreateInfo::mipLodBias is signed +- nvk: Fix border color alpha +- nil/format: Depth/stencil formats appear as red +- nil: Fix max mip level +- nil: Fix nonnormalized coordinates +- nvk: Set up clip and cull distances +- nvk: Fix dynamic buffer descriptor copies +- nvk: Inline nouveau_copy_linear +- nvk/copy: Rename push to p +- nvk/blit: Rename push to p +- nvk/dispatch: Rename push to p +- nvk: Drop most buffer tracking +- nvk: Rework TLS/SLM and image/sampler table handling +- nvk: Invalidate texture header and sampler caches each submit +- nvk/sampler: Free descriptor table entries +- nvk: Rework nvk_descriptor_table_add/remove +- nvk: Implement descriptor table growing +- nvk: Zero unused descriptors +- nvk: Add some asserts for nv50 compiler image restrictions +- nvk: Update to the new command buffer infrastructure +- nvk: Split nvk_queue into its own file +- nvk: Start every command buffer with a nop +- nvk: Initialize fixed draw/default state once +- nouveau/parser: Convert to mako +- nouveau/parser: Use more idiomatic python +- nouveau/parser: Put the dump helpers in C files +- nvk: Use f for extension features +- nvk: Drop a TODO +- nvk: Use VK_IMAGE_USAGE_*_ATTACHMENT_BIT for image clears +- nvk: Increase the graphics pipeline push space +- nil: Don't claim texture support for 2-bit SNORM +- nouveau/push: Fix a void pointer arithmetic bug +- nouveau/parser: Add more arrays +- nouveau/mme: Add basic structures for the Turing+ MME +- nouveau/mme: Add isaspec XML for the Turing+ MME +- nouveau/mme: Add an assembler and disassembler for the Turring+ MME +- nouveau/mme: Add a builder for the Turing+ MME +- nouveau/mme: Add a tiny simulator for the Turing+ MME +- nouveau/mme: Add an isaspec-based dumper +- nouveau/mme: Make the winsys headers C++ safe +- nouveau/mme: Add unit tests for the Turing+ MME simulator +- nvk: Add MME infrastructure +- nvk: Use MME for clears +- nouveau/mme: Add helper macros for setting fields +- nvk: Use MME for vkCmdDraw[Indexed]() +- nvk: Implement vkCmdDraw[Indexed]Indirect() +- nvk: Use p for the nouveau_ws_push_buffer in zero_vram +- nouveau: Add an nv_push struct +- nouveau: Rename the fields of vk_push +- nouveau: Move nv_push and helpers to their own header +- nouveau/parser: Take a FILE* in DUMP_*_MTHD_DATA +- nouveau: Move push validate to nv_push.c +- nouveau: Move push dumping to nv_push.c +- nvk: Use nv_push directly for graphics pipelines +- nouveau: Add a nouveau_ws_bo_new_mapped helper +- nvk: Use bo_new_mapped for the zero page +- nvk: Always allocate empty_push +- nvk: Move queue_sumbit to nvk_queue_drm_nouveau.c +- nvk: Submit pushbufs directly +- nvk: Use a regular BO for the empty push +- nvk: Use a regular BO for the queue state push +- nvk: Add an nvk_queue_submit_simple helper +- nvk: Initialize the queue later in device setup +- nvk: Use submit_simple for draw state init +- nvk: Use queue_submit_simple for zero_vram +- nvk: Break nvk_cmd_pool into its own file +- nvk: Use cmd instead of cmd_buffer +- nvk: Add BO recycling to the command pool +- nvk: Return VkResult from nvk_cmd_buffer_upload_alloc +- nvk: memcpy root descriptors for compute instead of doing a DMA +- nvk: Fully populate QMDs before uploading +- nvk: Constant buffer alignment is actually 64B +- nvk: Rework side-band data upload +- nvk: Add an nvk_cmd_buffer_push helper +- nvk: Add an nvk_cmd_buffer_ref_bo helper +- nvk: Allocate upload buffers from the command pool +- nvk: Use nvk_cmd_bo for push bufs +- nvk: Implement vkCmdExecuteCommands() +- nvk: Remove remaining references to nouveau_push.h +- nouveau: Use DRM interfaces directly in MME tests +- nouveau: Drop nouveau_ws_push +- nvk: Re-indent vk_instance.c +- nvk: Use vk_object_zalloc/free for descriptor pools/sets +- nvk: Fix up whitespace in nvk_descriptor_set.c +- nvk: Implement VK_KHR_push_descriptor +- nvk: Reference descriptor set layouts in the sets themselves +- nvk: Embed a nv_device_info in nvk_physical_device +- nvk: Add an nvk_queue_submit wrapper +- nvk: Also store the push BO map in nvk_queue_state +- nvk: Bring back push sync and dumping +- nvk: drop nvk_nir.h +- nvk: Add lowering for load_global_constant_bounded +- nvk: Properly implement robustBufferAccess +- vulkan/meta: Add key types +- vulkan/meta: Add a helper for image view types +- vulkan/meta: Add a create_sampler helper +- vulkan/meta: Fixes for clear +- vulkan/meta: Implement vkCmdBlitImage() +- nvk: Support load_layer_id +- nvk/meta: Save/restore descriptor set 0 +- nvk: Use meta for doing blits with the 3D hardware +- nvk: WFI in pipeline barriers +- util/vma: Allow initializing zero-size heaps +- nvk: Rework nvk_queue_submit_simple() +- nvk: Add a heap data structure +- nvk: Return a VkResult from nvk_shader_upload() +- nvk: Add a shader heap to nvk_device +- nvk: Allocate shaders from a heap +- nvk: Rework whitespace in nvk_device_memory.c +- nvk: Style fixes in nvk_physical_device.c +- nvk: Reset semaphore syncs on wait +- nvk/wsi: Style fixes +- nvk/wsi: Use the common present implementation +- nouveau/parser: Parse all fields in each method +- nvk: Add a query pool object +- nvk: Implement timestamp queries +- nvk: Implement pipeline statistics and occlusion queries +- nouveau/mme: Allow ZERO as the destinatio nof mme_load_to +- nouveau/mme: Assert on OOB registers +- nouveau/mme: Add support for freeing registers +- nouveau/mme: Add a couple helpers for working 64-bit addresses +- nouveau/mme: Add a helper for MME_DMA_READ_FIFOED +- nvk: Use mme_tu104_read_fifoed() +- nvk: Implement vkCmdCopyQueryPoolResults() +- nvk: Handle large command buffer uploads better +- nvk: Use a normal DMA for CmdUpdateBuffer +- nouveau/parser: Handle 6F methods +- nvk: Use mme_load_addr64() +- nvk: Use poll for BO waits +- nvk: Events +- nvk: Don't crash if we fail to allocate a push BO +- nvk: Stop leaking command pool BOs +- nvk: Enable VK_KHR_create_renderpass2 +- nvk: Advertise VK_KHR_imageless_framebuffer +- nvk: Flush the current pushbuf before allocating a new one +- nvk: Advertise VK_KHR_separate_depth_stencil_layout +- nvk: Tell WSI we don't support legacy scanout +- nouveau: Add PCI information to nv_device_info +- nvk: Implement VK_EXT_pci_bus_info +- nvk: Bind 3D images as 3D for clears +- nvk: Support copies between 3D and 2D images +- nil: Add a helper for getting 2D views of 3D images +- nvk: Support 2D views of 3D images +- nvk: Advertise VK_KHR_maintenance1 +- nvk: Use 2D array views for 3D storage images +- nil: Fix include guards in nil_image.h +- nvk: Advertise custom border color features +- vulkan: Add a helper for swizzling color values +- nvk: Implement VK_EXT_border_color_swizzle +- nvk: Advertise VK_EXT_extended_dynamic_state3 +- nvk: Move more states to dynamic +- nvk: Advertise VK_KHR_storage_buffer_storage_class +- nvk: Add a helper for pushing descriptors +- nouveau/headers: Add generated headers to dependencies +- nvk: Implement VK_EXT/KHR_buffer_device_address +- nvk: Break the guts of CmdDispatch into a helper +- nvk: Implement DispatchIndirect +- nouveau/mme: Add a mul64 helper +- nvk: Implement CS invocations statistics queries +- nil: Use ONE for the anixotropic coarse spread function +- nil: Properly support MSAA +- nil: Add an offset4d struct and some helpers +- nouveau/parser: Sort METHOD_ARRAY_SIZES +- nouveau/parser: Handle SET_ANTI_ALIAS_SAMPLE_POSITIONS +- nvk: Stop asserting on MSAA +- nvk: Handle zero color attachments better +- nvk: Handle multisampled render targets properly +- nvk: Support copies of MSAA images +- nvk: Use the right view format for stencil texturing +- nvk: Pass through a shader key for fragment shaders and MSAA +- nvk: Set correct multisample regs for graphics pipelines +- nvk: Stop creating a new upload BO every time +- nvk: Fill out sample locations on Maxwell B+ +- vulkan/meta: Bind whole LODs of 3D blit destinations +- vulkan/meta: Add a helper for building texture ops +- vulkan/meta: Break the guts of blit into a helper +- vulkan/meta: Support writing stencil as iterative discard +- vulkan/meta: Rename vk_meta_blit.c to vk_meta_blit_resolve.c +- vulkan/meta: Add support for MSAA resolves +- nvk/meta: Fix restore for descriptor set 0 +- nvk: Use meta for MSAA resolves +- nvk: Replace gl_SamplePosition with fract(gl_FragCoord.xy) +- nvk: Stop advertising higher framebufferNoAttachmentsSampleCounts +- nvk: Advertise MSAA via image format properties +- nvk: Advertise VK_KHR_depth_stencil_resolve +- nvk: Assert that descriptor buffer access stays in-bounds +- nvk: Add a bo size to nvk_descriptor_set +- nvk/format: Style fix for VkFormatProperties3KHR +- nvk: Support VK_FORMAT_B10G11R11_UFLOAT_PACK32 for vertex buffers +- nvk: Add a devenv ICD json file +- nvk: Advertise EXT_vertex_attribute_divisor +- nvk: Lower image_size to txs +- nvk: Fix a comment +- nvk: Add an nvk_buffer_addr_range helper +- nvk: Use nvk_buffer_addr_range for buffer descriptors +- nvk: Re-order Vulkan 1.0 feature bits +- nvk: Enable inheritedQueries +- nvk: Enable VK_EXT_provoking_vertex +- nvk: Advertise samplerMirrorClampToEdge via 1.2 features +- nvk: Advertise VK_KHR_bind_memory2 +- nvk: Enable KHR_dynamic_rendering +- nvk: Advertise KHR_uniform_buffer_standard_layout +- nvk: Advertise EXT_index_type_uint8 +- nvk: Advertise VK_EXT_separate_stencil_usage +- nvk: Capitalize NVK in user exposed strings +- nvk: Rename grid_size to group_count +- nvk: Lower load_num_workgroups ourselves +- nvk: Drop block_size from the root descriptor table +- nvk: Add a helper for loading resource_index-based descriptors +- nvk: Set maxMemoryAllocationCount +- nouveau/winsys: Take a drmDevicePtr in nouveau_ws_device_new() +- nouveau/winsys: Add an info to nouveau_ws_device +- nouveau/winsys: Move device type into nv_device_info +- nouveau/nil: Take an nv_device_info for image functions +- nouveau/nil: Use nv_device_info for format queries +- nouveau/mme: Invoke SET_OBJECT in the tests +- nouveau/mme: Make alu_op_to_str static +- nouveau/mme: Move mme_value into its own header +- nouveau/mme: Add a mme_reg_alloc struct +- nouveau/mme: Add an intermediate MME_ALU_OP enum +- nouveau/mme: Add an intermediate MME_CMP_OP enum +- nouveau/mme: Use mme_mov() for temp copies of register IMM32 sources +- nouveau/mme: Make helpers less Turing specific +- nouveau/mme: Break the Turing builder guts into a separate header +- nouveau/mme: Move the guts of mme_merge_to() into mme_tu104_builder.c +- nouveau/mme: Move the guts of mme_state_arr_to() into mme_tu104_builder.c +- nouveau/mme: Drop the implicit_imm parameter from mme_alu_to() +- nouveau/mme: Move the cf_stack struct to mme_builder.h +- nouveau/mme: Prepare the builder for multiple GPU generations +- nouveau/mme: Take an nv_device_info in mme_builder_init +- Support immediates in MERGE +- Add add immediate optimizations +- nvk: Add support for contiguous heaps to nvk_heap +- nvk: Use a contiguous shader heap pre-Volta +- nvk: Disable indirect draw/dispatch and query copy MMEs for now +- nvk: Free a couple regs in nvk_mme_build_draw_*() +- nvk: Properly align root descriptor tables for pre-Pascal +- nvk: Compile all NIR before running codegen +- vulkan/meta: Insert a geometry shader when needed +- nvk: Use a GS for layerered rendering pre-MaxwellB +- nvk: Handle zero-size index and vertex buffers pre-Turing +- nvk: Cosmetic clean-ups to Create/DestroyDevice +- nil: Only choose a PTE kind for tiled images +- nouveau/mme: Fix is_int18 for negative numbers +- nouveau/mme: Don't swap x and y in mme_fermi_merge_to() +- nouveau/mme: Take a const nv_device_info in mme_builder_init +- nouveau/mme: Unify some of the test framework +- nouveau/mme: Add some generic builder tests +- nouveau/mme: Add builder tests for SUB +- nouveau/mme: Use a uint32_t for size in mme_fermi_bfe() +- nouveau/mme: nouveau/mme: Add builder tests for SLL and SRL +- nvk/drm: Take a byte offset/range in push_add_push +- nvk: Rework nvk_cmd_push a bit +- nvk: Add a helper for pushing indirect data +- nvk: Make some MME builder names more consistent +- nouveau/mme: Don't allow WaW dependencies in the same Turing instruction +- nvk: Reduce register pressure in nvk_mme_build_draw*() +- nouveau/push: Add an NV_PUSH_MAX_COUNT #define +- nvk: Implement Draw*Indirect on pre-Turing +- vulkan/meta: Use the new NIR texture helpers +- nvk: Add a build test for MMEs +- nvk: Don't over-size push descriptor sets +- nvk: Return VK_ERROR_INCOMPATIBLE_DRIVER if the PCI vendor isn't NVIDIA +- nvk: Bump init context batch size +- nouveau/mme: Fix nested while instructions on Turing+ +- nouveau/mme: Add a helper to dump instructions +- nvk: Rework extension enables +- nvk: Rework features enables +- nvk: Advertise shaderImageGatherExtended +- nouveau/mme: Add a bfe helper +- nouveau/mme: Ensure that zero-initizlied mme_value is ZERO +- nvk: De-duplicate MME code for setting draw params +- nvk: Clamp viewport clip to max range +- nvk: Use the same lock for the submit and the memory objects list +- nvk: Advertise ICD/loader interface version 4 +- nvk: Add instace WSI entrypoints +- nouveau/mme: Use ADD for ine with an immediate +- nouveau/mme: Fix while loops pre-Turing +- nvk: Add begin to mme_scratch +- nvk: Use the new load/store_scratch helpers for DRAW_PAD_DW +- nouveau/mme: Add a helper for re-allocating registers +- nvk: Rework spill helpers and DRAW_COUNT spilling +- nvk: Spill DRAW_IDX pre-Turing +- nvk: Break the inner MME draw loop into a helper +- nvk: Increase the push runout to 512 dwords +- nil: Add a nil_image_for_level helper +- nil: Add an image_level_as_uncompressed helper +- nvk: Implement uncompressed views of compressed images +- nvk: Set pointClippingBehavior +- nvk: Expose VK_KHR_maintenance2 +- nvk: Add a separate #define for SSBO alignment +- nvk: Set spirv_to_nir_options::min_*_alignment +- nvk: Use vk_device_memory +- nvk: Implement VK_KHR_map_memory2 +- nvk: Sort SPIR-V caps +- nvk: Advertise EXT_shader_viewport_index_layer on MaxwellB+ +- nvk: Only use view_id for layer in multiview +- nvk/heap: Set the right pitch for heap resize copies +- nvk: Advertise shaderStorageImageReadWithoutFormat +- nvk: Fix the NO_PREFETCH assert for CmdDrawIndirect +- nvk: Advertise KHR_spirv_1_4 +- nvk: s/device/dev in nvk_image.c +- nvk: Add helpers for binding image planes +- nvk: Take an nvk_image_plane in nouveau_copy_rect_image +- nvk: Use the max descriptor alignemtn in GetDescriptorSetLayoutSupport +- nvk: Use NVIDIA_VENDOR_ID in pdev try_create() +- nvk: Use abbreviated names in nvk_device_memory.c +- nvk: Add device and driver UUIDs +- nvk: Add external memory queries +- nvk: Dedicated allocations override internal +- nvk: Require dedicated allocations for external images +- nouveau/winsys: Add dma-buf import support +- nvk: Support dma-buf import +- nvk: Support dma-buf export +- nvk: Enable external memory extensions +- nvk: Reformat nvk_buffer.c +- nvk: Add a buffer alignment helper +- nvk: Add an addr field to nvk_image_plane +- nvk: Use canonical variable names in nvk_physical_device.c +- nvk: Use canonical variable names in nvk_shader.c +- nvk: Use canonical variable names in nvk_bo_sync.c +- nvk: Use canonical variable names in nvk_sampler.c +- nvk: Drop nvk_physical_device::instance +- nvk: Only advertise EXT_pci_bus_info on discrete GPUs +- nouveau: Put PCI info in a pci substruct in nv_device_info +- nouveau: Stop using hex for SM numbers +- nvk: Set deviceType based on nv_device_info::type +- nouveau: Move more stuff into nv_device_info +- nouveau: Move gart_size to nv_device_info +- nvk: Use nv_device_info for class checks +- nvk: Rename nvk_device::ctx to ws_ctx +- nvk: Add a ws_dev to nvk_device and use it +- nvk: Move the winsys device to nvk_device +- nvk: Don't enumerate pre-Kepler GPUs +- nvk: Implement VK_EXT_physical_device_drm +- nvk: Require an environment variable for poorly tested hardware +- nvk: Use the new core vk_sampler struct +- Revert "vulkan: Allow scissors or viewports to be set without counts" +- vulkan/meta: Add a get_pipeline_layout helper +- vulkan/meta: Use vk_meta_get_pipeline_layout in blit/resolve +- nvk: Bind 3D depth/stencil images as 2D arrays +- nvk: Flush more state on VI_BINDINGS_VALID dirty +- nvk: Don't skip zero-size bindings in GetDescriptorSetLayoutSupport +- docs: Add a docs page for NVK +- docs: Add NVK to features.txt +- docs/relnotes: Stick something about NVK in new_features.txt +- nouveau: Drop GART size from nv_device_info +- nil: Add a nil_image_level_extent_px() helper +- nvk: Use the new NIL helper for image level extents for copies +- nvk: Improve image format properties and limits +- nvk: Rework multi-plane format features a bit +- nvk: Use nvk_root_descriptor_offset for drawInfoBase +- nvk: Add a root_desc_addr to the root descriptor table +- nvk: Add support for variable pointers +- nvk: Enable the SPIR-V DeviceGroup capability +- nvk: Separate the MME query copy code out a bit +- nvk: Implement CopyQueryPoolResults with a compute shader +- nvk: Misc. style nits +- nvk: Rework memory requirements to handle aspects correctly +- nvk: Implement the maintenance5 image layout queries +- nvk: Use VkBufferUsageFlags2 +- nvk: Implement CmdBindIndexBuffer2KHR +- nvk: Implement GetRenderingAreaGranularityKHR +- nvk: Decorate CmdBegin/EndRendering entrypoints +- nouveau: Move shader topology info to nv_device_info +- drm-uapi: Import nouveau_drm.h +- nouveau/winsys: Use the imported nouveau_drm.h headers +- nvk: Use the imported nouveau_drm.h headers +- nouveau/shim: Use the imported nouveau_drm.h headers +- nouveau/mme: Support the new UAPI +- nvk: Use an empty EXEC for the empty submit case +- nouveau/winsys: Allow nouveau_ws_device_new() without VM_BIND +- nvk: Print an error message if VM_BIND support is missing +- nvk: Enable the new UAPI +- nvk: Use more consistent device variable names +- nvk: Call nir_lower_int64 +- nir/gl: Move glsl_type::sampler_target() into a helper in its one caller +- nvk: Remove plane sources from tex instructions +- nvk: Use common physical device properties +- nv50/ir: Rework conversions for texture array indices +- clang-format: Add nir_foreach_reg_* +- clang-format: nir_foreach_src is not a foreach macro +- clang-format: Set the default ColumnLimit to 0 +- nir: Re-align a couple enums and add clang-format comments +- nir: Don't clang-format const_value helpers +- nir: Don't clang-format a couple typedefs +- nir: Don't clang-format debug print setup +- nir: More manual formatting +- nir: Pretty format type mapping helpers +- nir: Wrap pass macros in braces +- nir: Add a do to the do/while in nir_const_value_t_array() +- nir: Add a .clang-format file +- nir: clang-format src/compiler/nir/\*.[ch] +- nvk: Don't use nir_ssa_for_src() +- nir: Drop most instances of nir_ssa_dest_init() +- nir: Drop more instances of nir_ssa_dest_init() +- nir/clone: Clone nir_def nor nir_dest +- nir/serialize: [De]serialize nir_def nor nir_dest +- nir: Drop nir_ssa_dest_init() +- nir: Drop nir_ssa_dest_init_for_type() +- nir: nir_foreach_ssa_def() -> nir_foreach_def() +- st,zink,sfn: Use nir_foreach_def instead of nir_foreach_dest +- dxil: Use nir_foreach_def() instead of nir_foreach_dest() +- nir/from_ssa: Use nir_foreach_def() instead of nir_foreach_dest() +- nir: Drop nir_foreach_dest() +- intel/vec4: Stop passing around nir_dest +- intel/fs: Stop passing around nir_dest and nir_alu_dest +- broadcom: Stop using nir_dest directly +- vc4: Stop passing around nir_dest +- nir,ntt,a2xx,lima: Stop using nir_dest directly +- lima: Stop using nir_dest directly +- etnaviv: Stop passing around nir_dest +- r600/sfn: Stop passing around nir_dest and nir_alu_dest +- nv50/ir: Stop passing around nir_dest and nir_alu_dest +- nir/gather_types: Stop passing around nir_dest +- nir/dce: Stop passing around nir_dest +- nir/propagate_invariant: Stop passing around nir_dest +- nir/validate: Replace all dest validation with validate_def +- nir/print: Replace all dest printing with print_def +- nir: Get rid of nir_dest_bit_size() +- nir: Get rid of nir_dest_num_components() +- nir: Get rid of nir_dest_is_divergent() +- nir: Drop nir_alu_dest +- nir: Drop nir_dest +- util/format: 8-bit interleaved YUV formats are UNORM +- gallivm: Support G8B8_G8R8_422_UNORM and B8G8_R8G8_422_UNORM +- blorp: Use R8G8_UINT for YCRCB_* formats with CCS +- anv: Disable CCS_E for ISL_FORMAT_YCRCB_* +- vulkan/format: Use correct swizzle for 1-plane YCbCr formats +- gallivm: Drop the Vulkan YUV format hacks +- nir: Rename nir_instr_type_ssa_undef to nir_instr_type_undef +- nir s/nir_get_ssa_scalar/nir_get_scalar/ +- nir: s/live_ssa_def/live_def/ +- nir: s/nir_instr_ssa_def/nir_instr_def/ +- nir: Rework nir_scalar_chase_movs a bit +- nir: Fix nir_op_mov handling in nir_collect_src_uniforms +- nir: Handle nir_op_mov properly in opt_shrink_vectors +- nir: Don't handle nir_op_mov in get_undef_mask in opt_undef +- nir: Clean up nir_op_is_vec() and its callers +- nir/large_constants: Use nir_component_mask_t +- nir/large_constants: Add read/write_const_values helpers +- nir/opt_large_constants: Add Small constant handling +- spirv: Re-emit constants at their uses +- nir: Take a nir_def * in nir_tex_instr_add_src() +- nir: Take a nir_def * in nir_phi_instr_add_src() +- nir/opt_undef: Don't rewrite a bcsel to mov +- nir: Add a nir_instr_clear_src() helper and use it +- nir: Add and use a nir_instr_init_src() helper +- nir: Drop nir_if_rewrite_condition() +- nir: Drop most uses of nir_instr_rewrite_src_ssa() +- nir: Drop nir_instr_rewrite_src_ssa() +- nir: Drop most uses if nir_instr_rewrite_src() +- nir: Drop nir_instr_rewrite_src() +- nir: Drop nir_push_if_src() +- nir: Fix metadata in nir_lower_is_helper_invocation +- nir: Use nir_shader_intrinsic_pass() a few places +- drm-uapi: Sync nouveau_drm.h +- nvk: Plumb no_prefetch through to the DRM back-end +- nouveau/mme: Fix a compile warning +- intel/isl: Rename ISL_TILING_Yf/s to ISL_TILING_SKL_Yf/s +- intel/isl: Add ICL variants of Yf and Ys tiling +- intel/isl: Implement correct tile size calculations for Ys/Yf +- intel/isl: Use the depth field of phys_level0_sa for GFX4_2D 3D surfaces +- intel/isl: Fill out the correct phys_total_extent for Ys/Yf/Tile64 +- intel/isl: Indent uncompressed surface code +- intel/isl: Support Ys, Yf & Tile64 in isl_surf_get_uncompressed_surf +- intel/isl: Support Yf/Ys tiling in surf_fill_state +- intel/isl: Support Yf/Ys tiling in emit_depth_stencil_hiz +- intel/isl: Add initial data-structure support for miptails +- intel/isl: Add support for computing offsets with miptails +- intel/isl: Support miptails in isl_surf_get_uncompressed_surf +- intel/isl: Start using miptails +- intel/isl: Disallow CCS on 3D surfaces with miptails +- intel/isl: Allow Ys tiling +- anv: Align memory VA to support for Ys, Tile64 tiled images +- nvk: Clean up includes +- nvk: Add include guards to nvk_bo_sync.h +- nvk: SPDX everything +- nouveau/nil: SPDX everything +- nouveau/mme: SPDX everything +- nvk: Don't add a dummy attachment when gl_SampleMask is written +- nvk: Set the discard bit for Z/S self-deps +- nvk: Invalidate the texture cache in PipelineBarrier +- nvk: Lower interp_at_sample to interp_at_offset +- nvk: Disable statistics around meta ops +- nvk: Clean up viewport math +- nvk: Fix depth clipping parameters +- nvk: Enable dynamic clip/clamp enable +- nvk: Set GUARDBAND_Z_SCALE_1 when Z-clipping +- r600: Use more auto-generated nir_builder helpers +- r600: Use nir_builder helpers for load/store_shared_r600 +- nvk: Re-order physical device limits +- nvk: Advertise maxMemoryAllocationCount = 4096 +- nvk: Advertise discreteQueuePriorities = 2 +- nvk: Rip out old UAPI support +- nvk/drm: Drop the push_add_push_bo() helper +- nvk/drm: Drop the push_add_bo() helper +- nvk: Drop command buffer BO tracking +- nvk: Drop memory object tracking +- nvk: Drop the device-level mutex +- nvk: Get rid of the tiled memory allocation helpers +- nvk/drm: Restructure nvk_queue_submit_drm_nouveau() +- nvk/drm: Split exec as needed for large command buffers +- nvk: Don't store the descriptor pool BO in the set +- nvk: Store a 20-bit driver_build_sha in nvk_instance +- nvk: Hook up the disk cache +- nvk: Re-structure early shader compilation a bit +- nvk: Add a default pipeline cache +- nvk: Cache NIR shaders +- nvk: Init pipelineCacheUUID +- drm-uapi: Sync nouveau_drm.h +- nvk: Take GETPARAM_EXEC_PUSH_MAX into account +- nvk: Handle zero-sized sparse buffers +- nvk: Use align() and align64() instead of ALIGN_POT +- nouveau: Generate headers for Maxwell B compute +- nvk: Add a nvk_cmd_buffer_compute_cls() helper +- nvk: Invalidate sampler/texture header caches in BeginCommandBuffer() +- nvk: Invalidate SKED caches at the top of command buffers +- nvk: Advertise more inline uniform block limits +- nvk: Emit MME_DMA_SYSMEMBAR before indirect draw/dispatch +- nvk: Set max descriptors to 2^20 for most descriptor types +- nvk: Reset descriptor pool allocator when all sets are destroyed +- nil/format: Use A for alpha blend +- nil/format: Advertise R10G10B10A2_UINT texture buffer support +- nvk: Disable depth or stencil tests when unbound +- nvk: Always emit at least one color attachment +- nvk: Improve address space and buffer size limits +- nvk: Always set pixel_min/max_Z to CLAMP +- nvk: Use nouveau_ws_bo_unmap() instead of munmap() +- nvk: Free the disk cache +- nvk: Add an nvk_shader_finish() helper +- nvk: Handle unbinding images and buffers +- nvk: Clean up the disk cache on physical device create fail path +- vulkan/wsi: Allow for larger linear images +- nvk: Add a nvk_cmd_buffer_dirty_render_pass() helper +- nvk: Re-sort device features +- nvk: Implement VK_EXT_depth_bias_control +- nvk: Advertise VK_KHR_workgroup_memory_explicit_layout +- nvk: Implement VK_EXT_image_sliced_view_of_3d +- nvk: Advertise VK_EXT_primitive_topology_list_restart +- nvk: Advertise VK_EXT_attachment_feedback_loop_layout +- features: Mark VK_EXT_attachment_feedback_loop_layout done for NVK +- nvk: Re-arrange Vulkan 1.2 features to match the header +- nvk: Advertise shaderOutputLayer and shaderOutputViewportIndex +- nvk: Enable descriptorIndexing +- nvk: Implement VK_EXT_dynamic_rendering_unused_attachments +- nir: Add a nir_ssa_def_all_uses_are_fsat() helper +- nir: Add convert_alu_types to divergence analysis +- nir/lower_tex: Add a lower_txd_clamp option +- nir: Add a load_sysval_nv intrinsic +- nir: Add NV-specific texture opcodes +- nir: Add an load_barycentric_at_offset_nv intrinsic +- nir: Add a range to most I/O intrinsics +- nir: Add NVIDIA-specific I/O intrinsics +- nir/lower_bit_size: Fix subgroup lowering for floats +- nir: add deref follower builder for casts. +- nir: Handle wildcards with casts in copy_prop_vars + +Felix DeGrood (12): + +- anv: save a shader source uint32_t hash in gfx/compute pipelines +- anv: Add Source hash field to VkPipelineExecutableStatisticKHR +- iris: save shader source sha1 in ish +- mesa: propagate shader source sha1 from gl_shader to nir_shader +- intel: use shader source hash in INTEL_MEASURE +- intel/compiler: use shader source hash in shader dump code +- anv: add fake sparse support +- anv: enable fake sparse for Elden Ring +- anv: debug messaging for sparse texture usage +- anv: fix frame count reporting in INTEL_MEASURE +- anv: set ComputeMode.PixelAsyncComputeThreadLimit = 4 +- anv: remove CS_FLUSH from query regression + +Feng Jiang (9): + +- virgl: Only PIPE_BUFFER with VIRGL_BIND_CUSTOM flag is considered busy during creation +- meson: Export winsys function symbols for target va +- frontends/va: Add slice_count to AV1 slice_parameter +- virgl/video: Add definition of virgl_av1_picture_desc +- virgl/video: Add support for AV1 decoding +- virgl/video: Enable AV1 decoding +- meson: Rename dri-vdpau.dyn to dri.dyn +- CODEOWNERS: Add \@flynnjiang for VirGL video +- meson: Move video to separate section in meson configuration summary + +Filip Gawin (1): + +- crocus: Avoid fast-clear with incompatible view + +Flora Cui (1): + +- radeonsi: limit CP DMA to skip holes in sparse bo + +Francisco Jerez (29): + +- intel/fs/ra: Define REG_CLASS_COUNT constant specifying the number of register classes. +- intel/vec4/ra: Define REG_CLASS_COUNT constant specifying the number of register classes. +- intel/compiler: Make MAX_VGRF_SIZE macro depend on devinfo and update it for Xe2. +- intel/fs/ra/xe2: Scale up register allocation granularity by 2x on Xe2+ platforms. +- intel/eu/xe2+: Fix encoding of various message descriptors for change in register size. +- intel/fs: Fix signedness of payload_node_count argument of calculate_payload_ranges(). +- intel/fs/xe2+: Fix payload node live range calculations for change in register size. +- intel/fs/xe2+: Fix grf_count in post-RA scheduling for updated register file size. +- intel/fs/xe2+: Fixes for increased accumulator register width. +- intel/fs/xe2+: Scale MAX_SAMPLER_MESSAGE_SIZE by native register size. +- intel/eu/xe2+: Update validation of GRF region size to account for Xe2 reg size +- intel/fs/xe2+: Allow increased SIMD width for various get_fpu_lowered_simd_width() restrictions. +- intel/compiler/xe2+: Represent dispatch_grf_start_reg in native GRF units. +- intel/fs/xe2+: Update encoding of FB write message payload. +- intel/fs/xe2+: Round up fs_builder::vgrf() size calculation to HW register unit. +- intel/fs/xe2+: Scale BRW_MAX_MSG_LENGTH by native register size. +- intel/fs/xe2+: Fix payload layout of sampler messages for Xe2 reg size +- intel/fs/xe2+: Update GS payload setup for Xe2 reg size. +- intel/fs/xe2+: Update TCS payload setup for Xe2 reg size. +- intel/fs/xe2+: Update TES payload setup for Xe2 reg size. +- intel/fs: Lower unsupported regioning with non-trivial 2D regions on FIXED_GRFs. +- intel/fs/xe2+: Update regioning lowering offset alignment checks for Xe2 regs. +- intel/fs/xe2+: Fix execution width of SHADER_OPCODE_GET_BUFFER_SIZE for SIMD16 EU. +- intel/fs/xe2+: Fix calculation of spill message width for Xe2 regs. +- intel/xe2+: Round up size to reg_unit() in fs_reg_alloc::alloc_spill_reg(). +- intel/fs/xe2+: Fix URB writes with 0 data components. +- intel/fs: Specify number of data components of logical URB writes via control immediate. +- intel/fs: Delete manual 'inst->mlen' calculations from all uses of logical URB writes. +- intel/fs: Delete manual 'inst->mlen' calculations from all uses of logical URB reads. + +Frank Binns (10): + +- pvr: clang-format fixes +- pvr: skip setting up SPM consts buffer when no const shared regs are used +- pvr: cleanup SPM EOT dynarray after upload +- pvr: treat VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT as not supported +- pvr: remove pvr_pbe_get_src_pos() +- pvr: fix attachments segfault in pvr_is_stencil_store_load_needed() +- pvr: fix allocation size of clear colour consts shared regs buffer +- pvr: change a few places to use PVR_DW_TO_BYTES() +- pvr: fix setup of load op unresolved msaa mask +- pvr: emit PPP state when vis_test dirty bit is set + +Friedrich Vock (19): + +- radv/ci: Set DRIVER_NAME in LAVA raven vkcts jobs +- radv: Handle VK_SUBOPTIMAL_KHR in trace layers +- ac/msgpack: make fixstrs a const char +- ac/sqtt,radv: Split internal and API hash in PSO correlations +- ac/rgp: Write lds_size metadata +- ac/rgp: Add metadata for separate-compiled RT stages +- radv/sqtt: Move record filling to helper function +- radv/sqtt: Unregister records based on hash +- radv/sqtt: Write LDS size metadata in code objects +- radv/sqtt: Handle separately-compiled RT pipelines +- ac/sqtt,radv/sqtt: Add and use marker for separate RT compilation +- nir/load_store_vectorize: Handle intrinsics with constant base +- radv/rt: Pre-initialize instance address +- radv: Initialize shader freelist on allocation +- radv: Fix check in insert_block +- radv/rt: Reject hits within 10ULP of previous hits in emulated RT +- radv/rra: Recognize LPDDR memory +- radv/rmv: Recognize LPDDR memory +- vulkan: Don't use set_foreach_remove when destroying pipeline caches + +Ganesh Belgur Ramachandra (5): + +- radeonsi: stores bottom_edge_rule option in the rasterizer state +- radeonsi: sets OPTIMAL_BIN_SELECTION to 0 if using bottom_edge_rule +- radeonsi: "clear_render_target" shader in nir +- radeonsi: "clear_render_target_1d_array" shader in nir +- radeonsi: "clear_12bytes_buffer" shader in nir + +Georg Lehmann (39): + +- aco/gfx11: fix get_gfx11_true16_mask with v_cmp_class_f16 +- aco: improve get_gfx11_true16_mask description +- aco: combine a & ~b to bfi(b, 0, a) +- aco/gfx11: use v_cmp_class_f16 with opsel for bitnz/bitz +- aco: fix non constant 16bit bitnz/bitz +- ac/nir: handle more special cases in ac_nir_unpack_arg +- aco: use s_bitreplicate_b64_b32 to set exec to 0xffff0000ffff0000 +- nir/opt_intrinsics: optimize (exclusive_scan(op, a) op a) to inclusive scan +- aco: always use rtne for fquantize2f16 +- nir/opt_if: also rewrite uniform uses for read_invocation +- nir: unify lower_bitfield_insert with has_{bfm,bfi,bitfield_select} +- nir: unify lower_bitfield_extract with has_bfe +- nir: unify lower_find_msb with has_{find_msb_rev,uclz} +- aco: fix u2f16 with 32bit input +- aco: combine a | ~b to bfi(b, a, -1) +- aco: use v_cvt_f32_ubyte for signed casts too +- nir: add nir_scalar intrinsic helpers +- nir: add nir_scalar_equal +- aco: implement some exclusive scans with inclusive scans +- aco/gfx11: don't use bfe for local_invocation_id if the others are always 0 +- nir/opt_algebraic: remove broken fddx/fddy patterns +- aco: simplify masked swizzle dpp selection by removing or_mask first +- aco: fix p_extract with v1 dst and s1 operand +- aco: implement 64bit div find_lsb +- nir: scalarize masked_swizzle_amd created from shuffle_xor +- aco/optimizer: check if we can use omod before labeling it +- aco/optimizer: copy propagate to output modifier instructions +- aco: remove -0.0 for 32 bit fsign with mul_legacy/omod when denorms are flushed +- nir: make quad intrinsic dst bit size match src0 +- nir/lower_subgroups: use intrinsic builder more +- aco: assume new generations are unsupported by clrx +- aco: assume newer generation will use GFX11 wait_imm packing +- aco: print final ir instead if printing asm is unsupported +- aco/gfx11: optimize dual source export +- aco/gfx11: apply clamp/omod to vinterp +- aco: support v_fma_f32_dpp as fma_mix +- aco/gfx11: support vinterp as fma_mix +- aco: add missing scc def for SALU quad broadcast +- aco/sched: treat p_dual_src_export_gfx11 like export + +George Ouzounoudis (38): + +- nouveau/codegen: Support compact clip distances with arrayed_io +- nouveau/codegen: Handle nir op amul +- nouveau/codegen: Fix compact patch varyings in case of NIR +- nouveau/codegen: Add capability to pre-specify tessellation domain +- nvk: Do not increment instance id across draws +- nvk: Add a macro for root descriptor table byte offsets +- nvk: Set base vertex state in sequential mme draw +- nvk: Support base instance in instanced draw calls +- nvk: Switch point rasterization to point sprites +- nvk: Support large points +- nvk: Compile geometry shaders +- nouveau/mme: Keep device info in mme_builder +- nvk: Simplify mme build function argument +- nvk: Support VK_KHR_shader_draw_parameters +- nvk: Support for vertex shader transform feedback +- nvk: Support transform feedback indirect draws +- nvk: Support transform feedback geometry streams +- nvk: Support transform feedback queries +- nvk: Support vertex shader transform feedback on Fermi +- nvk: Disable PRIMITIVE_RESTART_VERTEX_ARRAY by default +- nvk: Fix geometry shader active stream mask +- nvk: Support geometry shaders +- nvk: Basic tessellation shader support +- nvk: Assign locations correctly for arrayed IO +- nvk: Enable multiview with tessellation shader +- nvk: Fix cases where execution mode is specified in the tesc shader. +- nvk: Respect tessellation domain origin state +- nvk: Lower io to temporaries for tessellation evaluation nir +- nvk: Support VkDescriptorSetVariableDescriptorCountLayoutSupport +- nvk: Handle cases of descriptor bindings with variable counts +- nvk: Add nir non-uniform optimization pass +- nvk: Enable descriptor indexing +- nvk: Do not keep redundant info for tessellation domain +- nouveau/codegen: Do not keep redundant info for tessellation domain +- nvk: Enable dynamic line rasterization mode state +- nvk: Fix support for VK_EXT_sample_locations +- nvk: Support dynamic state for enabling sample locations +- nouveau/codegen: Add a 4th optimization level for MemoryOpts + +Gert Wollny (63): + +- r600/sfn: Switch to register intrinsics +- r600/sfn/tests: add simple copy-prop test with register source +- r600/sfn: Allow for larger ALU CF's +- r600/sfn: Handle indirect array load/store dependencies better +- r600/sfn: Increase LDS fetch schedule priority +- r600/sfn: Add peephole optimization to move a dest to the previous op +- r600/sfn: reorder the value factory class member declaration a bit +- r600/sfn: Add some tests for proper register access +- r600/sfn: Print more info if scheduling fails +- r600/sfn: remove debug output leftovers +- r600/sfn: Fix use of multiple IDX with kcache +- r600/sfn: Always check arrays writes before allowing copy propagation +- r600/sfn: set block sizes based on chip class +- r600/sfn: Fix typo with block type +- r600/sfn: override slot count for IfInstr +- r600/sfn: Add method to convert to AluGroup directly +- r600/sfn: Add flags to check whether a group starts CF and can do that +- r600/sfn: make remaining slots a signed value +- r600/sfn: on Cayman loading an index register needs only one slot +- r600/sfn: Splizt ALU blocks in scheduler to fit into 128 slots +- r600/sfn: rework checks for ALU CF emission +- r600/sfn: Schedule AR uses befor possible groups +- r600: Explicitly force new CF in gs copy shader +- r600: Assert when backend wants to create a new ALU CF +- r600: don't check possible size of ALU CF +- r600: don't use sb disasm to disassamble copy shader +- r600: Force CF when emitting a NOP on R600 in gs copy shader +- r600/sfn: Don't try to propagate to vec4 with more than one use +- r600/sfn: Only switch to other CF if no AR uses are pending +- r600/sfn: AR loads should depend on all previous non ALU instructions +- r600/sfn: Renumber shader blocks in scheduler +- r600/sfn: Track whether a register is ALU clause local +- r600/sfn: Use clause local registers in RA +- r600/sfn: Take source uses into account when switching channels +- r600/sfn: take number of dest values into account +- r600: retire SB optimizer +- r600/sfn: work around injecting extra CF's to handle hardware bugs +- r600: use correct cso pointer for fetch shader +- r600/sfn: Make use of four clause local registers +- r600/sfn: drop unused ControlFlowInstr type enum +- r600/sfn: factor out resource as extra class +- r600/sfn: Simplify dependency chain for index loads on EG +- r600: print texture resource index mode separately +- r600/sfn: Make address split pass obligatory +- r600/sfn: rename method resource_base to resource_id +- r600/sfn: Add old address to update_indirect_addr +- r600/sfn: Sepeate resource and sampler in texture instructions +- r600/sfn: get rid of the method to get the index mode +- r600/sfn: sort the uniforms of the right shader +- r600/sfn: Fix use of scheduled_shader vs shader +- virgl: report MIRROR_CLAMP features better +- ci: Upref virglrenderer +- copyimage: check requested slice early when cube maps are involved +- mesa: check numlevels and numlayers when creating a texture view +- virgl: Use common clear_texture if host doesn't support the feature +- r600/sfn: don't remove texture sources by using the enum value +- r600: drop egcm_load_index_reg +- r600/sfn: Don't override a chgr pinning during copy propagation +- r600/sfn: When simplifying src vec4 pinnings, also check all uses +- virgl: Fix logic for reporting PIPE_MIRROR_CLAMP +- r600: Add callbacks for get_driver_uuid and get_device_uuid +- r600: Link with libgalliumvl, when enabling rusticl this is needed +- r600/sfn: Fixup component count only if intrinsic has it + +Guilherme Gallo (5): + +- bin/ci: Ensure that all jobs have nodes in DAG +- ci/radeonsi: Update flake list +- ci/freedreno: Add a new flake +- ci/zink: Found some flakes +- ci/anv: Catch some flakes + +Hannes Mann (1): + +- vulkan/wsi/wayland: Fix detection of tearing control protocol + +Hans-Kristian Arntzen (2): + +- wsi/x11: Fix potential deadlock in present ID. +- wsi/x11: Don't allow signal_present_id to rewind. + +Helen Koike (21): + +- ci: re-add EXTRA_LOCAL_PACKAGES to rootfs +- ci: add EXTRA_LOCAL_PACKAGES to apt-get install +- docs/ci: Add docs for EXTRA_LOCAL_PACKAGES +- ci: disable duplicated pipelines triggered by marge +- ci: add --project option to ci_run_n_monitor.py +- ci/android: remove strace output from cuttlefish-runner.sh +- ci: add locked flag to bindgen-cli on x86_64_build.sh +- ci: separate hiden jobs to -inc.yml files +- ci/ci_run_n_monitor: add docs for multiple targets +- ci/ci_run_n_monitor: print stress test results per job +- ci/ci_run_n_monitor: simplify with defaultdict +- ci/ci_run_n_monitor: merge print_job_status_change with print_job_status +- ci/ci_run_n_monitor: make --target mandatory +- ci/ci_run_n_monitor: merge enable_job with retry_job +- ci/ci_run_n_monitor: simplify enable/cancel logic in monitor_pipeline() +- ci/ci_run_n_monitor: allow / in --project +- ci/ci_run_n_monitor: limit repetitions on --stress +- ci/marge_queue: add missing python-dateutils to requirements.txt +- ci/ci_run_n_monitor: keep monitoring if a job is still running +- ci/marge_queue: add pretty_dutation() +- ci/ci_run_n_monitor: print job duration time + +Honglei Huang (7): + +- virgl/video: Add support for mpeg12 decoding +- virgl/video: Add support for vc1 decoding +- virgl/video: Add support for jpeg decoding +- virgl/video: Add support for hevc10bit decoding. +- virgl/video: Add more pipe type in virgl formats convert table +- virgl/video: Add jpeg buf start code check +- virgl: Enable vp9 hardware decode + +Hyunjun Ko (3): + +- anv: use ycbcr_info for P010 format +- anv: don't use cmd_buffer after destroyed. +- anv: don't flush_llc on gen9 + +Iago Toral Quiroga (100): + +- nir/trivialize: Move decl_reg to the start of the block +- v3dv: stop incrementing UBO indices by one +- nir/lower_robustness: drop skip_ubo_0 option +- v3dv: fix incorrect key setup +- broadcom/compiler: stop asserting on Vulkan environment +- broadcom/compiler: use NIR's lowering for dispatch base +- broadcom/compiler: move uniform offset lowering from compiler to GL driver +- broadcom/compiler: move vulkan's point coord lowering to the driver +- v3dv: don't set lower_wpos_pntc for Vulkan +- broadcom/compiler: always clamp results from logic ops +- broadcom/compiler: drop execution environment from the shader key +- v3dv: drop cpu path for buffer to image copies +- v3dv: remove unused code +- nir/lower_tex: copy backend_flags field when copying a tex instruction +- nir/lower_tex: use a callback to check sampler return size packing +- squash! v3dv,broadcom/compiler: don't abuse sampler index +- v3dv: assert that only tex instructions with sampler state have a sampler src +- v3d: fix texture packing lowering +- v3d,v3dv: use fquantize2f16 lowering in NIR +- v3dv: be more precise in vkGetImageSubresourceLayout +- v3dv: handle pPlaneLayouts in VkImageDrmFormatModifierExplicitCreateInfoEXT +- v3dv: bump up MAX_UNIFORM_BUFFERS to 16 +- v3dv: add support for sampling simple 2D linear textures +- v3dv: expand sampling from linear image hack to support multi-planar images +- v3dv: don't assume that bound descriptors have been written +- v3dv: only handle Android Hardware Buffer on Android +- v3dv: we can sample from 1D array too +- broadcom/compiler: add a couple of shader key helpers +- v3d: compute nir sha1 for uncompiled shader state +- v3d: use pre-computed shader sha1 for disk cache +- v3d: fix RAM shader cache +- v3d: get rid of shader_state pointer in v3d_key +- broadcom/simulator: reset CFG7 for compute dispatch in v71 +- broadcom/common: retrieve V3D revision number +- broadcom/compiler: update node/temp translation for v71 +- broadcom/compiler: implement "reads/writes too soon" checks for v71 +- broadcom/compiler: implement read stall check for v71 +- broadcom/compiler: add a v3d71_qpu_writes_waddr_explicitly helper +- broadcom/compiler: prevent rf2-3 usage in thread end delay slots for v71 +- broadcom/qpu: add new ADD opcodes for FMOV/MOV in v71 +- broadcom/qpu: fix packing/unpacking of fmov variants for v71 +- broadcom/compiler: make vir_write_rX return false on platforms without accums +- broadcom/compiler: rename vir_writes_rX to vir_writes_rX_implicitly +- broadcom/compiler: only handle accumulator classes if present +- broadcom/compiler: don't assign rf0 to temps across implicit rf0 writes +- broadcom/compiler: CS payload registers have changed in v71 +- broadcom/compiler: don't schedule rf0 writes right after ldvary +- broadcom/compiler: allow instruction merges in v71 +- broadcom/qpu: add MOV integer packing/unpacking variants +- broadcom/qpu: fail packing on unhandled mul pack/unpack +- broadcom/compiler: generalize check for shaders using pixel center W +- broadcom/compiler: v71 isn't affected by double-rounding of viewport X,Y coords +- broadcom/compiler: update peripheral access restrictions for v71 +- broadcom/qpu: add packing for fmov on ADD alu +- broadcom/compiler: handle rf0 flops storage restriction in v71 +- broadcom/compiler: enable ldvary pipelining on v71 +- broadcom/compiler: try to use ldunif(a) instead of ldunif(a)rf in v71 +- broadcom/compiler: don't assign rf0 to temps that conflict with ldvary +- broadcom/compiler: convert mul to add when needed to allow merge +- broadcom/compiler: implement small immediates for v71 +- broadcom/compiler: update thread end restrictions for v7.x +- broadcom/compiler: update ldvary thread switch delay slot restriction for v7.x +- broadcom/compiler: lift restriction for branch + msfign after setmsf for v7.x +- broadcom/compiler: start allocating from RF 4 in V7.x +- broadcom/compiler: validate restrictions after TLB Z write +- broadcom/compiler: lift restriction on vpmwt in last instruction for V3D 7.x +- broadcom/compiler: fix up copy propagation for v71 +- broadcom/compiler: don't allocate spill base to rf0 in V3D 7.x +- broadcom/compiler: improve allocation for final program instructions +- broadcom/compiler: don't assign registers to unused nodes/temps +- broadcom/compiler: only assign rf0 as last resort in V3D 7.x +- v3dv: expose V3D revision number in device name +- v3dv/device: handle new rpi5 device (bcm2712) +- v3dv: setup render pass color clears for any format bpp in v71 +- v3dv: setup TLB clear color for meta operations in v71 +- v3dv: fix up texture shader state for v71 +- v3dv: handle new texture state transfer functions in v71 +- v3dv: implement noop job for v71 +- v3dv: handle render pass global clear for v71 +- v3dv: GFX-1461 does not affect V3D 7.x +- broadcom/compiler: update thread end restrictions validation for v71 +- v3dv: handle early Z/S clears for v71 +- v3dv: handle RTs with no color targets in v71 +- v3dv: don't convert floating point border colors in v71 +- v3dv: handle Z clipping in v71 +- v3dv: make v3dv_viewport_compute_xform depend on the V3D version +- v3dv: fix depth clipping then Z scale is too small in V3D 7.x +- v3d/v3dv: fix texture state array stride packing for V3D 7.1.5 +- v3d,v3dv: support up to 8 render targets in v7.1+ +- v3d,v3dv: don't use max internal bpp for tile sizing in V3D 7.x +- v3d,v3dv: propagate NaNs bits in shader state records are reserved in v7.x +- v3dv: use new texture shader state rb_swap and reverse fields in v3d 7.x +- v3dv: fix color write mask for v3d 7.x +- v3d,v3dv: fix depth bias for v3d 7.x +- v3d,v3dv: fix compute for V3D 7.1.6+ +- v3dv: expose fullDrawIndexUint32 in V3D 7.x +- v3dv: expose depthClamp in V3D 7.x +- v3dv: expose scalarBlockLayout on V3D 7.x +- v3dv: fix confusing nomenclature about DRM nodes +- v3d,v3dv: fix MMU error from hardware prefetch after ldunifa + +Ian Douglas Scott (1): + +- egl/wayland: Don't segfault if \`create_wl_buffer` returns \`NULL` + +Ian Romanick (38): + +- intel/fs: Always do opt_algebraic after opt_copy_propagation makes progress +- intel/fs: Constant fold SHL +- intel/fs: Constant fold OR and AND +- util/rb-tree: Return the actual first node from rb_tree_search +- util/rb-tree: Fix typo in comment +- nir/builder: Add nir_extract_i8_imm and nir_extract_u8_imm helpers +- nir/algebraic: Remove redundant pack / unpack lowering patterns +- intel/fs: Completely re-write the combine constants pass +- intel/fs: Combine constants for SEL instructions too +- intel/fs: Combine constants for integer instructions too +- intel/fs: New VGRF packing scheme for constant combining +- intel/compiler: Combine control barriers with identical memory semantics +- intel/compiler: Don't evict for workgroup-scope fences +- glsl/list: Clean up an inappropriate comment +- util/rb-tree: Work around C++'s dislike of offsetof +- util/rb-tree: Inline rb_tree_init +- intel/fs: Don't continue fixed point iteration just because liveout changes +- intel/fs: Don't try to copy propagate into a source again after progress is made +- intel/fs: Make try_constant_propagate and try_copy_propagate file private +- intel/fs: Move src.file checks out of try_constant_propagate and try_copy_propagate +- intel/fs: Don't loop in try_constant_propagate +- intel/fs: Simplify check in can_propagate_from +- intel/fs: Make opt_copy_propagation_local file private +- intel/fs: Encapsulate per-block ACP in a structure +- intel/fs: Use rb_tree to store ACP entries by source +- intel/fs: Use rb_tree to store ACP entries by destination +- intel/fs: Use rb_tree for copy prop dataflow +- intel/fs: Merge copy prop dataflow loops +- intel/compiler/xe2: Update fs_visitor::setup_vs_payload to account for Xe2 reg size +- intel/compiler/xe2: Use SIMD16 for nir_intrinsic_image_size +- intel/compiler/xe2: TXD is lowered to SIMD16 in SIMD32 mode +- nir/rematerialize: Rematerialize ALUs used only by compares with zero +- intel/compiler/xe2: Handle new URB read messages +- intel/compiler/xe2: Handle new URB write messages +- intel/compiler/xe2: Update fs_visitor::emit_urb_writes to not assume SIMD8 +- spirv: Track when a shader has a cooperative matrix +- intel/fs: Add DP4A to get_lowered_simd_width +- nir/split_vars: Don't split arrays of cooperative matrix types + +Igor Torrente (4): + +- zink: Fix enumerate devices when running compositor +- zink: Removes \`disable_xcb_surface` +- zink: Fix one addicional case when running a compositor +- zink: fix for startup crash of weston running on top of zink + venus + +Illia Abernikhin (2): + +- state_tracker: moving initialisation of whandle out from if statement whandle initialization inside if statement but used also outside +- i915: change format in dbg string Actually, uintptr_t is of type unsigned long, but the debug line uses the %d format specifier, which expects an int. + +Illia Polishchuk (7): + +- iris: remove NULL check for already dereferenced pointer earlier +- s/Intel: fix/anv: fix: potentially overflowing expression in genX +- glx: fix dead code when gc var cannot be null due to earlier check +- state_tracker: fix dereference before null check +- anv, drirc: Add workaround to speed up Cyberpunk 2077 reg allocation +- zink: move find_sampler_var from zink to nir core +- nir: fix invalid sampler search by texture id + +Italo Nicola (24): + +- mesa/main: account for RTT samples when updating framebuffer +- mesa/main: allow readpix/teximage to read from implicitly multisampled fbos +- panfrost/genxml: fix Surface With Stride descriptor alignment +- panfrost/genxml: add Multiplanar Surface descriptor +- panfrost: refactor (un)packing of surface descriptors +- pan/decode: decode Multiplanar Surface descriptors +- panfrost: prepare pan_image_view for multiplanar formats +- panfrost: prepare the driver to support YUYV and variants +- panfrost: advertise support for YUYV and variants +- panfrost: mandate proper alignment requirement depending format and arch +- panfrost: add PAN_MESA_DEBUG=yuv for debugging yuv sampler +- gallium/st: add non-CSC lowering of I420 as PIPE_FORMAT_R8_G8_B8_420 +- gallium/st: add non-CSC lowering of YV12 as PIPE_FORMAT_R8_B8_G8_420 +- pan/bi: add support for I420 and YV12 sampling +- gallium/st: lower NV21 to R8_B8G8 instead of G8_B8R8 +- panfrost: fix invalid memory access in get_equation_str() +- pan/decode: handle more than one panfrost_device +- panfrost/ci: updated CI expectations +- egl: reenable partial redraw with a warning when using gallium hud +- pan/genxml: add Width/Height fields to v9+ Plane descriptor +- panfrost: rename _needs_multiplanar_descriptor to _is_yuv +- panfrost: prepare v9+ to support YUV sampling +- panfrost: use centered YUV chroma siting +- panfrost: advertise YUV formats for valhall + +Iván Briano (23): + +- anv: ensure CFE_STATE is emitted for ray tracing pipelines +- iris: ensure mesh is disabled on context init +- anv: ensure mesh is disabled on context init +- anv: implement Wa_14019750404 +- intel/compiler: call brw_nir_adjust_payload from brw_postprocess_nir +- anv,hasvk: respect provoking vertex setting on geometry shaders +- anv: fix missing 3DSTATE_SBE_CLIP emission +- anv: ensure pipelines have all state +- anv: tell blorp to do mesh stuff only if it's enabled +- blorp: fix hangs with mesh enabled +- anv: use a simpler MUE layout for fast linked libraries +- anv: track what kind of pipeline a fragment shader may be used with +- intel/fs: read viewport and layer from the FS payload +- intel/fs: handle URB setup for fast linked mesh pipelines +- anv: enable VK_EXT_mesh_shader where supported +- intel/fs: use ffsll so we don't explode on 32 bits +- vulkan/runtime: add internal parameter to vk_spirv_to_nir +- nir/lower_int64: respect rounding mode when casting to float +- intel/compiler: round f2f16 correctly for RTNE case +- util: add double_to_float16 helpers +- nir: round f2f16{_rtne/_rtz} correctly for constant expressions +- anv: advertise VK_KHR_global_priority_queue +- anv: use the right vertexOffset on CmdDrawMultiIndexed + +Jani Nikula (1): + +- docs/vulkan: fixup some typos + +Janne Grunau (4): + +- asahi: toggle more barrier bits after transform feedback +- asahi,agx: Fix stack buffer overflow in agx_link_varyings_vs_fs +- asahi,agx: Upload constant buffers immediately +- asahi: decode: Fix uint64_t format modifiers in agxdecode_stateful() + +Jesse Natalie (2): + +- nir_lower_mem_access_bit_sizes: Fix write-mask-constrained 3-byte stores as atomics +- d3d12: Fix multidimensional array ordering + +Jianxun Zhang (1): + +- intel/common: Only set op mask on instructions in decoder + +Jonathan Marek (2): + +- freedreno: move redump.h to common code + cleanup +- tu: add a TU_DEBUG=rd option for cmdstream dumping + +Jordan Justen (73): + +- isl: Add ISL_SURF_USAGE_STREAM_OUT_BIT +- anv,iris,hasvk: Use ISL_SURF_USAGE_STREAM_OUT_BIT for setting stream-out MOCS +- genxml/hsw: Add additional MOCS field enumerations +- genxml/chv: Add MEMORY_OBJECT_CONTROL_STATE_CHV to document compared to BDW +- isl/dev: Add uncached MOCS value +- isl: Set MOCS to uncached for MTL stream-out +- intel/isl: Use intel_needs_workaround() for MTL CCS WA +- intel/compiler: Use nir SUBGROUP_INVOCATION for RT TOPOLOGY_ID +- intel/dev: Add LNL platform enum +- intel/dev: Support xe2 device init (for intel_device_info_test) +- intel/tools: Use 'env bash' to find bash executable +- intel/decoder: Fix xml filename when verx10 % 10 is not 0 +- intel/decoder: Add intel_spec_load_common() +- intel/decoder: Make intel_spec_load_filename() have separate dir and name strings +- intel/genxml: Align "Texture Coordinate Mode" naming +- intel/genxml: Split some genxml sorting code into a intel_genxml module +- intel/genxml: Convert gen_bits_header to use ElementTree +- intel/genxml: Convert gen_pack_header to use ElementTree +- intel/genxml: Add GenXml class into intel_genxml module +- intel/genxml: Add filter_engines() to GenXml class +- intel/genxml: Move sorting & writing into GenXml class +- intel/genxml: Don't rewrite sorted xml if the contents didn't change +- intel/genxml: Add final newline to output when saving xml +- intel/genxml: Update xml with gen_sort_tags.py output +- intel/dev: Use RPL-U name on RPL-U devices +- intel/dev: Add more RPL PCI IDs +- anvil,hasvk: Rename need_clflush to need_flush +- intel/common: Move intel_clflush.h to intel_mem.h/intel_mem.c +- anvil,hasvk: Replace intel_clflush_range with intel_flush_range +- intel/common: Add intel_flush_range_no_fence +- anvil,hasvk: Use intel_flush_range_no_fence to flush command buffers +- util/u_cpu_detect: Drop unused has_tsc +- util/u_cpu_detect: Detect clflushopt support +- meson: Check for the __builtin_ia32_clflushopt function +- intel/clflush: Add support for clflushopt instruction +- intel/dev/xe: Move placeholder subslice info into XEHP_FEATURES +- intel/genxml: Ignore tail leading/trailing whitespace in node_validator() +- intel/genxml: Fix comparing xml when node counts differ +- intel/dev: Update device string for MTL PCI ID 0x7d55 +- intel/genxml: Support importing from another genxml file +- intel/genxml: Add support for excluding items when importing +- intel/genxml: Add all xml files as pack dependencies +- intel/genxml: Add GenXml.optimize_xml_import() +- intel/genxml: Drop assertion to allow for importing +- intel/genxml: Add GenXml.add_xml_imports method +- intel/genxml: Add GenXml.flatten_xml() method +- intel/genxml: Add genxml_import.py script +- intel/decoder: ralloc_steal() values from spec context for fields and enums +- intel/decoder: Implement support for importing genxml +- intel/genxml: Start Xe2 support +- intel/genxml: Auto-import genxml files using genxml_import.py +- intel/common: Add sse2_args for 32-bit build when -Dsse2=false was set +- intel/compiler/fs: Support Xe2 reg size in assign_curb_setup +- intel/compiler: Update opt_split_sends() for Xe2 reg size +- intel/compiler: Update emit_rt_lsc_fence() for Xe2 +- intel/compiler: Update lower_trace_ray_logical_send() for Xe2 +- intel/compiler: Update ray-tracing intrinsic lowering for Xe2 +- intel/compiler: Update RT stack_id access for Xe2 +- intel/fs: Update SSBO & shared uniform block loads for Xe2 +- intel/genxml: Build with gen20.xml +- intel/isl: Build for Xe2 +- iris: Build for Xe2 +- anv/blorp: Use anv_genX to set device->blorp.exec +- anv: Disable Ray Tracing on xe2 until our compiler supports Xe2 RT +- anv: Build for Xe2 +- anv: Print warning that Xe2 is not supported rather than failing +- intel/compiler: Add enum xe2_lsc_cache_store +- intel/compiler: Use enum xe2_lsc_cache_store on xe2 +- intel/compiler: Add enum xe2_lsc_cache_load +- intel/compiler: Use enum xe2_lsc_cache_load on xe2 +- anv/batch: Check if batch already has an error in anv_queue_submit_simple_batch() +- anv/batch: Assert that extend_cb is non-NULL if the batch is out of space +- intel/dev: Add 0x56ba-0x56bd DG2 PCI IDs + +Jose Maria Casanova Crespo (2): + +- vc4: mark buffers as initialized at vc4_texture_subdata +- vc4: Fix mask RGBA validation at YUV blit + +José Expósito (3): + +- zink: Fix crash on zink_create_screen error path +- zink: fix dereference before NULL check +- zink: allow software rendering only if selected + +José Roberto de Souza (51): + +- anv: Use workaround framework to Wa_14016118574 +- intel/aux_map: Nuke format_enum +- intel/aux_map: Use get_aux_entry() in remove_mapping() +- intel/aux_map: Replace magic number by INTEL_AUX_MAP_ENTRY_VALID_BIT +- intel/aux_map: Rename some variables to improve readability +- intel/aux_map: Mask out bits above index 47 in intel_aux_get_meta_address_mask() +- intel/aux_map: Convert l1_entry_addr_out to canonical +- intel/aux_map: Drop magic sub table size number +- intel/aux_map: Add function and macro to return l2 and l1 table masks +- anv: Add gem_create_userptr() to KMD backend +- anv: Replace handle by anv_bo in the gem_close() +- anv: Add support for userptr in Xe KMD +- intel: Sync xe_drm.h +- intel/dev/xe: Add support for small-bar setups +- anv: Request Xe KMD to place BOs to CPU visible VRAM when required +- iris: Request Xe KMD to place BOs to CPU visible VRAM when required +- iris/xe: Call iris_lost_context_state() when batch engine is replaced +- intel/dev: Port intel_dev_info tool to Xe KMD +- iris: Replace I915_EXEC_FENCE_SIGNAL by IRIS_BATCH_FENCE_SIGNAL in common code +- intel: Move i915_drm.h specific code from common/intel_gem.h to common/i915/intel_gem.h +- intel/common: Move functions inside of C++ ifdef +- intel: Rename intel_gem_add_ext() to intel_i915_gem_add_ext() +- iris: Move i915_gem_set_domain() call to i915 backend +- iris: Move iris_bufmgr_bo_close() to kmd backend +- iris: Add gem_create_userptr() to KMD backend +- iris: Add support for userptr in Xe KMD +- intel/genxml/gen125: Add missing fields in MI_MATH +- iris: Set MI_MATH MOCS field +- anv: Set MI_MATH MOCS field +- intel/tests/mi_builder: Set MI_MATH MOCS field +- intel/genxml/gen125: Set MI_MATH MOCS field as non-zero +- anv: Nuke unused READ_ONCE() from anv_batch_chain.c +- anv: Remove VkAllocationCallbacks parameter from reloc functions +- anv: Return earlier in anv_reloc_list functions +- intel: Sync xe_drm.h and rename engine to exec_queue +- anv: Override vendorID for Hogwarts Legacy +- intel/isl: Remove unknown workaround +- intel/isl: Remove Wa_22011186057 +- anv: Update Wa_16014390852 for MTL +- intel: Sync xe_drm.h +- anv: Move i915 specific gem_set_caching to backend +- anv: Move i915 specific code from common anv_gem.c +- anv: Move bo_alloc_flags_to_bo_flags() to backend +- anv: Move i915 handling of imported bos bo_flags +- anv: Remove i915_drm.h include from common code +- iris: Lock bufmgr->lock before call vma_free() in error path +- iris: Nuke useless flags from iris_fine_fence_new() +- intel: Prepare implementation of Wa_18019816803 and Wa_16013994831 for future platforms +- intel: Sync xe_drm.h +- anv: Switch Xe KMD vm bind to sync +- anv: Add missing ANV_BO_ALLOC_EXTERNAL flags when calling anv_device_import_bo() + +Juan A. Suarez Romero (7): + +- broadcom/ci: update expected results +- vc4/ci: update expected results +- v3d/shim: include new ioctl parameters +- v3dv/ci: update expected list +- broadcom: add performance counters for V3D 7.x +- broadcom/simulator: add per-hw version calls +- v3d/vc4/ci: add new fails/timeout + +Julia Tatz (10): + +- gallium/dri: fix dri2_from_names +- aux/trace: skip multi-line comments in enums2names +- aux/trace: deduplicate enum dump macro work +- aux/trace: move trace_sample_view logic +- aux/trace: fix set_hw_atomic_buffers method name +- aux/trace: add screen video methods +- aux/trace: add context video methods +- aux/trace: wrap video_codec & video_buffer +- aux/trace: unwrap refrence frames in picture_desc +- aux/trace: trace video_buffer method return vals + +Julia Zhang (1): + +- radeonsi: modify algorithm of skipping holes of sparse bo + +Julian Hagemeister (1): + +- Gallium: Fix shared memory segment leak + +Juston Li (10): + +- zink: remove venus from renderpass optimizations +- venus: sync protocol for VK_EXT_vertex_input_dynamic_state +- venus: implement VK_EXT_vertex_input_dynamic_state +- venus: set lvp queries as saturate on overflow +- venus: add helper function to get cmd handle +- venus: refactor out common cmd feedback functions +- venus: support deferred query feedback recording +- venus: track/recycle appended query feedback cmds +- venus: append query feedback at submission time +- venus: switch to unconditionally deferred query feedback + +Kai Wasserbäch (3): + +- fix: clover: LLVM 18 renamed/moved CGFT_*, update compat layer +- fix: clover: LLVM 18: s/CodeGenOpt::/CodeGenOptLevel::/ +- fix: clover: warning: ignoring return value of ‘int posix_memalign(…)’ [-Wunused-result] + +Karmjit Mahil (29): + +- pvr: Remove mrt setup from SPM EOT +- pvr: Compile SPM EOT shader +- pvr: Use the SPM EOT on barrier stores +- pvr: Remove some magic numbers and increments from km stream +- pvr: Restructure \`rogue_kmd_stream.xml` +- pvr: Submit PR commands +- pvr: Use the correct size for the unified store allocation +- pvr: Allow query stage for barrier sub cmds +- pvr: Fix occlusion query unaccounted for user fences +- pvr: Fix writing query availability write out +- pvr: Fix packing issue with max_{x,y}_clip +- pvr: Fix csb relocation status assert on \`pvr_csb_finish()` +- pvr: Fix \`for` loop itarator usage +- pvr: Fix dynamic desc offset storage +- pvr: Fix cubemap layer stride +- pvr: Use the render passes' attachments array to setup ISP state +- pvr: Adjust EOT PBE state to account for the iview's base array layer +- pvr: Fix MRT index in PBE state +- pvr: Fix pbe_emit assert +- pvr: Fix OOB access of pbe_{cs,reg}_words +- pvr: Order tile buffer EOT emits to be last +- pvr: Fix subpass sample count on ds attachment only +- pvr: Refactor subpass ds and sample count setup +- pvr: Fix SPM load shader sample rate +- pvr: Fix PPP_SCREEN sizes +- vulkan: Add \`vk_subpass_dependency_is_fb_local()` helper +- tu: Use common \`vk_subpass_dependency_is_fb_local()` +- pvr: Don't merge subpasses on framebuffer-global dependancy +- pvr: Only setup the bgobj to load if we have a load_op + +Karol Herbst (213): + +- nvc0: initial Ada enablement +- rusticl/mesa: make svm_migrate optional +- llvmpipe: enable system SVM +- nvc0: fix num_gprs for Volta+ +- rusticl: fix warnings with newer rustc +- gm107/ir: fix SULDP for loads without a known format +- nv50/ir/nir: fix txq emission on MS textures +- nv50/ir/nir: Fix zero source handling of tex instructions. +- rusticl/kernel: only handle function_temp memory before lowering printf +- meson,ci: bump meson req for rusticl to 1.2 +- rusticl/nir: add helper functions we need for a NIR_PASS macro +- rusticl/nir: add a nir_pass macro +- rusticl/nir: use the new nir_pass macro +- rusticl/kernel: rename res to internal_args inside lower_and_optimize_nir_late +- rusticl/kernel: merge lower_and_optimize_nir_pre_inputs and lower_and_optimize_nir_late +- rusticl/kernel: move things around in lower_and_optimize_nir +- rusticl/kernel: get rid of initial function_temp type lowering +- rusticl/kernel: mark can_remove_var as unsafe and document it +- n50/compute: submit initial compute state in nv50_screen_create +- nvk: add vulkan skeleton +- nouveau/winsys: add the new winsys implementation +- nvk: use winsys lib +- nvk: fix nvk_buffer include guards +- nouveau/headers: add script to sync in-tree headers with open-gpu-doc +- nouveau/headers: initial sync of headers +- nvk: implement GetPhysicalDeviceQueueFamilyProperties2 to make the CTS happy +- nvk: advertize memory heaps and types +- nouveau/ws: reorganize a little +- nouveau/ws: dup the fd +- nouveau/ws: add a field for the SM version +- nvk: set nonCoherentAtomSize as the CTS divides with this value +- nouveau/ws: add bo API +- nvk: add basic device memory support +- nouveau/headers: add nvtypes.h +- nouveau/headers: typedef Nv void types +- nouveau/headers: add host classes +- nouveau/ws: add context support +- nouveau/ws: add a cmd buffer +- novueau/bo: refcount it +- novueau/bo: add nouveau_ws_bo_wait +- nvk: allocate a GPU context for each VkDevice +- nvk: add nvk_bo_sync +- nvk: add nvk_CmdPipelineBarrier2 stub +- nvk: impl nvk_CmdCopyBuffer +- nouveau/ws: fix setting push bo domains +- nouveau/ws: PUSH_IMMD only works with 16 bit values +- nouveau/ws: set GPU object class +- nouveau/ws: bind 2D class +- nvk: use fermi class definitions +- nvk: add basic support for images +- nvk: simple format table +- nvk: add support for blits +- nvk: report maxMipLevels as 1 +- nvk: optimize blit command buffer gen +- nvk: implement CmdFillBuffer +- nvk: implement CmdUpdateBuffer +- nvk: implement CmdCopyBuffer2 +- nvk: advertise VK_KHR_copy_commands2 +- nvk: implicitly reset the command buffer +- nouveau/ws: handle 0inc inside nvk_push_val as well +- nvk: reduce pitch even further in CmdFillBuffer +- nvk: support multiple miplevels +- nvk: support array blits over multiple layers +- nvk: tiling prep work for VK_EXT_image_2d_view_of_3d +- nouveau/ws: make sure we don't submit nonsense +- nouveau/ws: assert on broken channel +- nvk/blit: assert that formats are supported +- nouveau/headers: Generate parser functions +- nouveau/ws: initial debugging options for command submissions +- nouveau/ws: depend on generated class header files +- nouveau/ws: get rid of libdrm +- nouveau/ws: use new NVIF interface to query oclasses +- nvk: set deviceName +- nouveau/headers: add path for 3D headers +- nouveau/headers: initial 3D headers import +- nouveau/ws: allocate 3D subchan +- nouveau/ws: allocate copy subchan as well +- nouveau/ws: add API to query if the context was killed +- nouveau/ws: add a bo unmap helper function +- nvk: clean up bo mappings +- nouveau/ws: bound check nouveau_ws_push_append +- nouveau/ws: rework refing push buffer bos +- nouveau/ws: push chaining +- nvk: fix OOB read inside nvk_get_va_format +- nvk: alloc a zero page and use it for vertex runouts +- nvk: fix zero page refing +- nvk: support exporting buffers +- nvk: fix some class version checks +- nvk: properly align shaders pre Turing +- nvk: rework QMD handling to support pre Turing +- nvk: align desc root table +- nvk: Use SET_PIPELINE_PROGRAM pre-Volta +- nvk: properly align slm size +- nvk: use remaps for image copies +- nvk: reduce pitch for FillBuffer +- nvk: bind more subchans in init_context_state +- nvk: support pre Maxwell Texture Headers +- nvk/device: fix order of error handling +- nvk: allocate VAB memory area +- nvk: wire up M2MF for Fermi +- nouveau/mme: add test for BEQ with magic exit offset +- nouveau/mme: add a macro exit helper +- nvk: Add a macro to set MMIO registers via falcons +- nouveau/winsys: fix SM value for Ada +- nvk: fix num_gprs for Volta+ +- nvk: replace mp with tpc +- nvk: properly calculate SLM region by taking per arch limits into account +- nouveau: fix max_warps_per_mp_for_sm for builds with asserts disabled +- nvk: enable fp helper invocations loads on more gens +- nv50/ir: use own info struct for sys vals +- nv50/ir: convert system values to gl_system_value +- nouveau/mme: fix OOB access inside while_ine builder test +- nouveau/mme: fix OOB inside tu104 simulator +- clc: use CLANG_RESOURCE_DIR for clang's resource path +- nv50: fix code uploads bigger than 0x10000 bytes +- nouveau: take glsl_type ref unconditionally +- rusticl/kernel: optimize nir between lowering io and explicit types +- nv50: limit max code uploads to 0x8000 +- zink: fix source type in load/store scratch +- zink: fix global stores +- zink: update some compute caps +- rusticl: add debug option to sync every event +- rusticl/device: _MAX_CONST_BUFFER0_SIZE is unsigned +- ci: disable a660 jobs +- nir: make workgroup_id 32 bit only +- nir: make num_workgroups 32 bit only +- ac: drop 64 bit handling for cl workgroup intrinsics +- gallivm/nir: drop 64 bit handling for cl workgroup intrinsics +- intel/compiler: drop 64 bit handling for cl workgroup intrinsics +- panfrost: drop 64 bit handling for cl workgroup intrinsics +- rusticl: reduce global_invocation_id_zero_base to 32 bit +- panfrost: drop pan_nir_lower_64bit_intrin +- rusticl/disk_cache: fix stack corruption +- rusticl/query: fix use-after-free, but also fix incorrect usage of unsafe +- rusticl/event: disable profiling for devices without timestamps +- rusticl/queue: properly implement clCreateCommandQueueWithProperties +- rusticl/memory: do not verify pitch for IMAGE1D_BUFFER +- rusticl/memory: only specify PIPE_BIND_SHADER_IMAGE where supported +- asahi: fetch available system memory +- asahi: lower hadd +- asahi: handle kernels +- asahi: handle load_workgroup_size +- asahi: handle load_global_invocation_id_zero_base +- asahi: implement get_compute_state_info +- asahi: implement set_global_binding +- asahi: implement clear_buffer +- asahi: gracefully handle allocating linear images +- asahi: handle images in is_format_supported +- rusticl/memory: fallback if allocating linear images fails +- rusticl: enable asahi +- rusticl/mesa: create contexts with PIPE_CONTEXT_NO_LOD_BIAS +- docs/features: cl_khr_3d_image_writes needs driver support +- rusticl/mesa: fix \`set_constant_buffer` when passing an empty buffer +- rusticl/kernel: skip adding global id offsets if not used +- meson/rusticl: add sha1_h +- rusticl/mesa/context: fix clear_sampler_views +- nir: add nir_lower_alu_vec8_16_srcs pass +- zink: lower vec8/16 +- rusticl/mesa: create COMPUTE_ONLY contexts +- rusticl: fix clippys bool_to_int_with_if +- rusticl/memory: fix potential use-after-free in clEnqueueSVMMemFill +- nir/load_libclc: fix libclc memory leak +- rusticl/kernel: Fix creation from programs not built for every device +- ci: add half-life 2 freedreno flake +- zink: implement get_compute_state_info +- zink: copy has_variable_shared_mem cs property +- zink: pass entire pipe_grid_info into zink_program_update_compute_pipeline_state +- zink: refactor spec constant handling +- zink: variable shared mem support +- zink: support more nir opcodes +- zink: make spirv_builder_emit_*op compatible with spec constants +- zink: support samplers with unnormalized_coords +- zink: implement remaining pack ops via bitcast +- zink: fix RA textures +- zink: fix load/store scratch offsets +- rusticl/mesa/screen,device: add driver_name +- rusticl: enable zink +- pipe-loader: allow to load multiple zink devices +- rusticl: bump rustc version to 1.66 +- rusticl/mesa/nir: mark more methods as mut +- rusticl/mesa/nir: Mark NirShader and NirPrintfInfo as Send and Sync +- rusticl/mesa: mark PipeResource as Send and Sync +- rusticl/mesa: mark PipeTransfer as Send +- rusticl/cl: mark _cl_image_desc as Send and Sync +- rusticl/queue: get rid of pointless Option around our worker thread handle +- rusticl/queue: make it Sync +- rusticl/kernel: get rid of Arcs in KernelDevStateVariant +- rusticl/memory: use get_mut instead of lock in drop +- zink: implement PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS +- rusticl/api: remove cl_closure macro +- zink: implement load_global_constant +- zink: properly emit PhysicalStorageBufferAddresses cap +- nir/lower_mem_access_bit_sizes: fix invalid shift bit_size +- rusticl/device: restrict 1Dbuffer images for RGB and RGBx +- rusticl/memory: use PIPE_BUFFER for IMAGE1D_BUFFER images +- rusticl/format: disable all sRGB formats +- asahi: flush denorms on exact fmin/fmax +- zink: wrap shared memory blocks in a struct +- zink: properly alias shared memory +- zink: fix zink_destroy_screen for early screen creation fails +- docs/features: remove empty lines confusing mesamatrix +- rusticl/device: restrict image_buffer_size +- rusticl/device: restrict param_max_size further +- rusticl/mem: properly set pipe_image_view::access +- zink: lower fisnormal as it requires the Kernel Cap +- radv: fix buffers in vkGetDescriptorEXT with size not aligned to 4 +- rusticl/queue: Only take a weak ref to the last Event +- rusticl/mesa: pass PIPE_BIND_LINEAR in resource_create_texture_from_user +- zink: deallocate global_bindings array +- rusticl/mesa/screen: do not derefence the entire pipe_screen struct +- nvc0: implement PIPE_CAP_TIMER_RESOLUTION +- rusticl/queue: do not send empty lists of event to worker queue +- rusticl/queue: fix implicit flushing of queue dependencies + +Kenneth Graunke (21): + +- iris: Re-emit 3DSTATE_DS for each primitive (workaround 14019750404) +- intel/compiler: Fix sparse cube map array coordinate lowering +- intel/compiler: Respect NIR_DEBUG_PRINT_INTERNAL for DEBUG_OPTIMIZER +- intel/fs: Account for payload GRFs when calculating register pressure +- intel/compiler: Move SCHEDULE_NONE handling into schedule_instructions() +- intel/fs: Index scheduler mode string table by mode enum +- intel/fs: Make helpers for saving/restoring instruction order +- intel/fs: Pick the lowest register pressure schedule when spilling +- intel/fs: Dump IR for pre-RA scheduler modes in DEBUG_OPTIMIZER +- iris: Check prog[] instead of uncompiled[] for BLORP state skipping +- nir: Fix function parameter indentation in nir_opt_barriers.c +- nir: Add an optimization pass to reduce barrier modes +- nir: Reduce the scope of shared memory barriers +- lavapipe: Don't delete control barriers +- virgl, nir_to_tgsi: Add a hack for promoting partial memory barriers +- dxil: Set UAV_FENCE_THREAD_GROUP any time global isn't required +- glsl: Use nir_opt_barrier_modes() to drop unnecessary barriers +- anv: Use nir_opt_barrier_modes() to drop unnecessary barriers +- mesa: Fix zeroing of new ParameterValues array entries when growing +- intel/fs: Fix Xe2 URB read/lowering with per-slot offsets +- anv: Add support for a transfer queue on Alchemist + +Kevron Rees (1): + +- Force vk vendor for spider-man remastered + +Konrad Dybcio (5): + +- freedreno: Set magic writes per-GPU, using existing data +- freedreno: Include speedbin fallback in 740 chipid to fix probing +- freedreno: Include speedbin fallback in 730 chipid to fix probing +- freedreno: Include speedbin fallback in 690 chipid to fix probing +- freedreno: Add Adreno 643 + +Konstantin Seurer (95): + +- radv: Stop using the misleading round_up_u* functions +- radv/meta_buffer: Stop setting RADV_META_SAVE_DESCRIPTORS +- radv/meta_buffer: Rename size_minus16 to max_offset +- llvmpipe: Fix compiling with LP_USE_TEXTURE_CACHE +- nir/tests: Refactor boilerplate into a common header +- nir/tests: Use a single binary +- draw: Do not restart the primitive_id at 0 +- gallivm: Fix subsampled format sampling under Vulkan +- gallivm: Ignore nir_tex_src_plane +- lavapipe: Remove dummy sampler ycbcr conversion +- lavapipe: Store immutable_samplers as lvp_sampler array +- lavapipe: Fix binding immutable samplers with desc buffers +- lavapipe: Implement samplerYcbcrConversion +- lavapipe: Advertise samplerYcbcrConversion +- llvmpipe: Zero extend vectors in widen_to_simd_width +- vulkan: Add a generated vk_properties struct +- radv: Use common physical device properties +- clang-format: Disable formatting by default +- lavapipe: Use common physical device properties +- nir/from_ssa: Don't insert store_reg instructions before phis +- gallivm: Run nir_convert_to_lcssa before nir_convert_from_ssa +- lavapipe/ci: Remove descriptor_indexing fails +- radv/rt: Rename shader_pc and next_shader +- radv/rt: Rename traversal_shader to traversal_shader_addr +- nir/opt_large_constants: Handle small float arrays +- bin: Update spirv sources +- vulkan: Allow beta extensions for physical device features +- vulkan: Allow beta extensions for physical device properties +- vulkan Add enqueue entrypoint for CmdDispatchGraphAMDX +- nir: Add shader enqueue data structures and handling +- spirv: Update headers and grammer JSON +- spirv: Implement SPV_AMDX_shader_enqueue +- lavapipe: Add lvp_pipeline_type +- lavapipe: Implement exec graph pipelines +- lavapipe: Implement AMDX_shader_enqueue commands +- lavapipe: Advertise AMDX_shader_enqueue +- radv: Add internal_nodes_offset to scratch_layout +- radv: Remove leaf_args::dst_offset +- radv/rt: Remove some dead code +- radv/rt: Do not apply stack_ptr for non-recursive stages +- radv/rt: Add and use radv_build_traversal +- radv/rt: Insert rt_return_amd before lowering shader calls +- radv/rt: Split stage initialization and hashing +- aco: Do not fixup registers if there are no shader calls +- radv: Stop updating the stack_size in insert_rt_case +- lavapipe: Lock around CSO destroys +- vulkan/wsi/x11: Implement capture hotkey using the keymap +- venus: Use the common GetPhysicalDeviceFeatures2 implementation +- nir/lower_shader_calls: Limit the remat chain length +- lavapipe: Avoid lowering shaders twice +- lavapipe: Fix the locking around cso destruction +- aco/validate: Handle p_wqm like p_parallelcopy +- aco: Use bytes() instead of size() in emit_wqm +- aco: Unify demote and demote_if selection +- radv: Only generate debug info if required +- aco/lower_to_cssa: Fix typo +- radv: Don't use the depth image view for depth bias emission +- radv/rt: Store NIR shaders separately +- radv/rt: Add monolithic raygen lowering +- radv/rt: Enable monolithic pipelines +- radv/ci: Document new flake +- vulkan/properties: Handle unsized arrays properly +- radv: Remove dead radix_sort_vk_get_memory_requirements call +- radv/radix_sort: Vendor the radix sort dispatch code +- radv: Perform multiple sorts in parallel +- radv/ci: Improve ray tracing skips +- ac/llvm: Fix typed loads with 16bit formats +- ac/llvm: Use the correct return type for uadd_carry and usub_borrow +- ac/llvm: Use float types for float atomics +- radv: Don't advertise features requiring PS epilogs with LLVM +- radv: Update navi21 llvm fails +- radv/rt: Handle stages without nir properly +- radv: Remove ray tracing shader module identifier skips +- radv/bvh: Treat instances with mask == 0 as inactive +- radv/ray_queries: Skip cull_mask handling if it is FF +- radv/rt: Skip cull_mask handling if it is FF +- aco/spill: Make sure that offset stays in bounds +- nir: Add nir_cf_node_cf_tree_prev +- nir: Add nir_foreach_block_in_cf_node_reverse +- nir: Add nir_rematerialize_deref_in_use_blocks +- nir/lcssa: Fix rematerializing derefs +- nir/deref: Layer rematerialization helpers +- lavapipe/ci: Fix asan expectations +- hasvk: Use the common GetPhysicalDeviceFeatures2 implementation +- vulkan: Remove vk_get_physical_device_core_1_*_feature_ext +- radv/bvh/ploc: Load child bounds from LDS +- radv: Merge the sync_data and header initialization +- radv: Do not sync after radv_update_buffer_cp +- zink: Initialize primitive types to an invalid value +- nir/passthrough_gs: Support edge flags with points +- zink: Enable edge flags with points +- mesa: Fix glBegin/End when LINE_LOOP is not supported +- llvmpipe: Compile a nop texture function for unsupported configurations +- radv/rt: Use nir_shader_instructions_pass for lower_rt_instructions +- radv/sqtt: Fix tracing acceleration structure commands + +Lang Yu (5): + +- amd/common: add AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32 property +- radeonsi: use AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32 to determine wave size +- radeonsi: use wave size to determine index stride +- amd/common: add missing stuff for gfx11.5 +- amd/radeonsi: add missing stuff for gfx11.5 + +Leandro Ribeiro (13): + +- egl: rewrite outdated comment in _eglFindDevice() +- egl: remove unused parameter from _eglAddDRMDevice() +- egl: simplify _eglAddDRMDevice() +- egl: make explicit that we don't support render nodes for software EGLDevice +- egl: move is_render_node flag to platform_wayland +- loader: rename loader_open_render_node() to loader_open_render_node_platform_device() +- loader: add driver list as parameter in loader_open_render_node_platform_device() +- pipe-loader: add pipe_loader_get_compatible_render_capable_device_fd() +- dri: add queryCompatibleRenderOnlyDeviceFd() to __DRI_MESA extension +- kmsro: try to use only compatible render-capable devices +- loader: add loader_is_device_render_capable() +- egl/drm: get compatible render-only device fd for kms-only device +- egl: error out if we can't find an EGLDevice in _eglFindDevice() + +Leo Liu (4): + +- radeonsi: add AV1 profile to supported profile +- radeonsi/vcn: fix the incorrect dt_size +- Revert "frontends/va: Also map VAImageBufferType for reading" +- ac/gpu_info: override ib_size_alignment for VCN_DEC and JPEG + +Lina Versace (14): + +- docs: Add row for VK_KHR_maintenance5 +- intel/pci_ids: Consistently use lowercase +- venus: Sync protocol for VK_EXT_graphics_pipeline_library +- venus: Erase pViewports and pScissors in fewer cases +- venus: Fix crash when VkGraphicsPipelineCreateInfo::layout is missing +- venus: Fix subpass attachments +- venus: Drop incorrectly-used always-true pipeline vars +- venus: Use VkImageAspectFlags in vn_subpass +- venus: Add enum vn_pipeline_type +- venus: Renames for VkGraphicsPipelineCreateInfo fixes +- venus: Refactor pipeline fixup into two stages +- venus: Do pipeline fixes for VK_EXT_graphics_pipeline_library +- venus: Enable VK_EXT_graphics_pipeline_library behind debug flag +- venus: Fix -Wmaybe-uninitialized + +LingMan (22): + +- rusticl/memory: fix potential use-after-free in clEnqueueSVMFree +- rusticl: Rename XyzCB aliases to FuncXyzCB +- rusticl: add structs to hold the C callbacks +- rusticl: use CreateContextCB +- rusticl: use DeleteContextCB +- rusticl: use EventCB +- rusticl: use MemCB +- rusticl: use ProgramCB +- rusticl: use SVMFreeCb +- rusticl: Make EventSig take ownership of its environment +- rusticl: add a safe abstraction to execute a DeleteContextCB +- rusticl: add a safe abstraction to execute an EventCB +- rusticl: add a safe abstraction to execute a MemCB +- rusticl: add a safe abstraction to execute an SVMFreeCb +- rusticl: add a safe abstraction to execute a CreateContextCB +- rusticl: add a safe abstraction to execute a ProgramCB +- rusticl/api: drop a few include paths +- rusticl: mark the fields of callback structs private +- rusticl: drop an \`#[allow(dead_code)]` marker +- rusticl/core: don't take a lock while dropping \`Context` +- rusticl: Show an error message if the build is attempted with an outdated bindgen version +- rusticl: Show an error message if the version of bindgen can't be detected + +Lionel Landwerlin (169): + +- anv: hide exec_flags selection inside the i915 backend +- isl: add a tool to query surface parameters +- intel/fs: fix missing predicate on SEL instruction +- intel/compiler: rework input parameters +- ci/a530: switch a few tests to flakes to unblock CI +- vulkan: bump header register to 1.3.258 +- intel/fs: don't try to rebuild sequences of non ssa values +- intel/vec4: fix log_data pointer +- intel/fs: consider UNDEF as non-partial write +- intel/fs: add more UNDEFs around SEND messages +- isl: add ability to store buffer size in unused RENDER_SURFACE_STATE fields +- anv: simplify buffer address+size loads from descriptor buffer +- intel/fs: add support for sparse accesses +- intel/nir: handle image_sparse_load in storage format lowering +- intel/nir: add lower for sparse images & textures +- anv: wire image sparse loads +- blorp: switch blorp_update_clear_color to early return +- blorp: update and move fast clear PIPE_CONTROLs to drivers +- anv: fix 3DSTATE_RASTER::APIMode field setting +- anv: enable EDS3 ConservativeRasterizationMode +- vulkan: skip non required extension structures +- vulkan/runtime: add a layered implementation of vkCmdBindIndexBuffer +- anv: enable INTEL_DEBUG=nofc +- anv: fake non intel vendorID for Death Stranding +- hasvk: fix null descriptor handling with A64 messages +- anv: remove descriptor array bounds checking +- hasvk: remove descriptor array bounds checking +- anv/hasvk: track robustness per pipeline stage +- anv: implement VK_EXT_pipeline_robustness +- intel/fs: track more steps with INTEL_DEBUG=optimizer +- intel/fs: add variable for output of debug backend optimizer +- intel/decoder: constify some input parameters +- blorp: drop programming of 3DSTATE_(MESH|TASK)_SHADER +- anv: emit 3DSTATE_GS only once per pipeline +- intel/decoder: add options to decode surfaces/samplers +- anv: get rid of genX(emit_multisample) +- anv: move genX(rasterization_mode) to gfx8_cmd_buffer.c +- anv: don't try to access dynamic buffers from surface states +- iris: ensure stalling pipe control before fast clear +- intel/compiler: disable per-sample interpolation modes with non-per-sample dispatch +- intel/compiler: fix dynamic alpha-to-coverage handling +- intel/fs: implement dynamic interpolation mode for dynamic persample shaders +- intel/fs: move lower of non-uniform at_sample barycentric to NIR +- zink+anv: add regression testing with pipeline libraries +- anv: implement vkCmdBindIndexBuffer2KHR +- anv: handle new VkBufferViewUsageCreateInfoKHR +- anv: add vkGetRenderingAreaGranularityKHR() +- anv: implement GetDeviceImageSubresourceLayoutKHR/GetImageSubresourceLayout2KHR +- anv: add maintenance5 A8_UNORM/A1B5G5R5_UNORM support +- anv: deal with new pipeline flags +- anv: enable KHR_maintenance5 +- anv: add missing ISL storage usage +- genxml/gfx11: remove Tiled Resource Mode field from HIER_DEPTH_BUFFER +- genxml/gfx12: rename Tiled Resource Mode +- isl: program 3DSTATE_HIER_DEPTH_BUFFER_BODY::TiledMode as documented +- intel/isl: Disallow Yf, Ys and Tile64 for 3D depth/stencil surfaces +- isl: disable Yf/Ys/Tile64 tilings for 1D images +- isl: add a usage flag to request 2D/3D compatible views +- isl: disallow TileYs/Yf on 3D storage images on Gfx9/11 +- intel/isl: Add a max_miptail_levels field to isl_tile_info +- isl: make isl_surf_get_uncompressed_surf robust to argument accesses +- isl: add Gfx12/12.5 restriction on 3D surfaces & compression +- isl: disallow miptails on planar formats +- isl: disable miptails on gfx12 with yuv formats +- isl: disable CCS on Ys/Yf +- blorp: allow 3D blits/copies on Ys/Yf/Tile64 tiling +- intel/aux_map: correctly program tiling mode for Ys +- isl: reorder tiling selection +- anv: enable standard Y tiles +- isl/tilememcpy_test: add multiple tile testing +- anv: rename total_batch_size +- anv: reuse cmd_buffer::total_batch_size +- intel/measure: track batch buffer sizes +- intel/nir: rerun lower_tex if it lowers something +- intel/fs: limit register flag interaction of FIND_*LIVE_CHANNEL +- hasvk: add state cache invalidation back before fast clears +- blorp: remove unused variable +- anv: remove ReorderMode from pipeline 3DSTATE_GS emission +- anv: change anv_batch_emit_merge to also do packing +- intel/anv: batch stats util +- intel/decoder: implement accumulated prints +- anv: move all dynamic state emission to cmd_buffer_flush_dynamic_state +- anv: rename files to represent their usage +- anv: categorize partial/final pipeline instruction +- anv: split 3DSTATE_TE packing between static & dynamic parts +- anv: split 3DSTATE_VFG emission +- anv: add a flag tracking occlusion query count change +- anv: split pipeline programming into instructions +- vulkan/runtime: add helper to name dirty states +- anv: add new low level emission & dirty state tracking +- anv: remove unused state emission +- anv: split BLEND_STATE packing from BLEND_STATE_POINTERS emit +- docs: update Anv documentation about dynamic state emission +- anv: create individual logical engines on i915 when possible +- anv: Copy/Clear MSAA images over companion RCS while we are on compute +- pps-producer: add ability to select device with DRI_PRIME +- anv: remove aux checking asserts +- anv: bound image usages to the associated queue family +- anv: fix 3DSTATE_VFG emission +- anv: emit 3DSTATE_URB_ALLOC_(MESH|TASK) only when mesh shaders are enabled +- anv: ensure mesh pipeline have all pre-rasterization stages disabled +- anv: ensure partially packed instructions are emitted in the pipeline +- anv: fix missing 3DSTATE_SBE_MESH emission +- anv: fix utrace timestamp buffer copies +- anv: add a memcpy compute internal kernel +- anv: add simple shader support without a command buffer +- anv: move simple shaders code to its own object +- anv: move utrace flush out of backends +- anv: enable utrace timestamp buffer copies on compute engine +- intel: don't assume Linux minor dev node +- intel/ds: lock submissions to u_trace_context +- util/u_trace: count number of tracepoints +- intel/ds: track number of tracepoint timestamp copies +- anv/utrace: trace CPU on timestamp buffer readiness +- intel/ds: avoid dropping traces when running out of shared memory +- anv/iris: widen Wa_14015946265 to Gfx11+ +- anv: add missing workaround for 3DSTATE_LINE_STIPPLE +- iris: add missing workaround for 3DSTATE_LINE_STIPPLE +- intel/fs: handle ishl in surface/sampler rematerialization +- intel/fs: handle add3 in surface/sampler rematerialization +- intel/fs: switch from SIMD 1 to 8 instructions surface/sampler rematerialization +- anv: fix internal compute copy shader build +- anv: reduce working temporary memory for BVH builds +- anv: move bo_pool allocation flags to init caller +- anv: use buffer pools for BVH build buffers +- intel/ds: track acceleration RT commands +- anv: fix index buffer size programming +- anv: implement INTEL_DEBUG=reemit +- anv: add missing workaround handling in simple shader +- anv: fix a couple of missing input for 3DSTATE_RASTER programming +- anv: flag 3DSTATE_RASTER as dirty after simple shader primitive +- vulkan: bump headers/registry to 1.3.267 +- anv: rename primary in container in ExecuteCommands() +- anv: add support for VK_EXT_nested_command_buffer +- anv: simplify push descriptors +- anv: fixup spirv cap for ImageReadWithoutFormat on Gfx12.5 +- Revert "intel/fs: limit register flag interaction of FIND_*LIVE_CHANNEL" +- anv: update batch chaining to Gfx9 commands +- anv: workaround Gfx11 with optimized state emission +- u_trace: generate tracepoint index parameter in perfetto callbacks +- u_trace: generate tracepoint name array in perfetto header +- intel/ds: provide names for different events of a timeline's row +- anv: reuse local variable for gfx state +- anv: track render targets & render area changes separately +- anv: don't uninitialize bvh_bo_pool is not initialized +- anv: uninitialize queues before utrace +- anv: move generation shader return instruction to last draw lane +- anv: fix generated draws gl_DrawID with more than 8192 indirect draws +- anv: extract out draw call generation +- anv: identify internal shader in NIR +- anv: avoid MI commands to copy draw indirect count +- anv: move generation batch fields to a sub-struct +- util/glsl2spirv: add ability to pass defines +- anv: factor out host/gpu internal shaders interfaces +- anv: index indirect data buffer with absolute offset +- anv: add ring buffer mode to generated draw optimization +- anv: merge gfx9/11 indirect draw generation shaders +- anv: document the draw indirect optimization ring mode +- anv: fixup 32bit build of internal shaders +- anv: fix uninitialized use of compute initialization batch +- intel/fs: fix dynamic interpolation mode selection +- anv/meson: add missing dependency on the interface header +- anv: fix corner case of mutable descriptor pool creation +- isl: disable MCS compression on R9G9B9E5 +- intel/fs: rerun divergence analysis prior to convert_from_ssa +- intel/nir/rt: fix reportIntersection() hitT handling +- anv: fix CC_VIEWPORT pointer dirty after blorp/simple-shaders +- anv: fix dirty state tracking for 3DSTATE_PUSH_CONSTANT_ALLOC +- intel/perf: fix querying of configurations + +Louis-Francis Ratté-Boulianne (15): + +- panfrost: Fix error in comment +- panfrost: Add methods to determine slice and body alignment +- panfrost: Add method to get size of AFBC subblocks +- panfrost: Precalculate stride and nr of blocks for AFBC layouts +- panfrost: Add panfrost_batch_write_bo +- panfrost: Make panfrost_resource_create_with_modifier public +- panfrost: Split out internal of \`panfrost_launch_grid` +- panfrost: Add infrastructure for internal AFBC compute shaders +- panfrost: Add method to get size of AFBC superblocks valid data +- panfrost: Add support for AFBC packing +- panfrost: Legalize resource when attaching to a batch +- panfrost: Don't force constant modifier after converting +- panfrost: Add debug flag to force packing of AFBC textures on upload +- panfrost: Add some debug utility methods for resources +- panfrost: Add env variable for max AFBC packing ratio + +Lucas Stach (33): + +- ci/etnaviv: update ci expectation +- etnaviv: move resource seqnos to level +- etnaviv: flush destination before executing blit +- etnaviv: optimize resource copies by skipping clean levels +- etnaviv: add helper to mark resource level as flushed +- etnaviv: add helper to mark resource level as changed +- etnaviv: add helper to transfer resource level age to another +- etnaviv: add helper to get TS validity +- etnaviv: add helper to set TS validity +- etnaviv: move TS meta into etna_resource_level +- etnaviv: add tile status buffer status into TS metadata +- etnaviv: optimize sampler source update +- etnaviv: allow sampler TS even if the resource is flushed +- etnaviv: keep blit destination tile status valid if possible +- etnaviv: optimize render resource update +- etnaviv: optimize transfers when whole resource level is discarded +- etnaviv: split etna_copy_resource_box levels parameter in src/dst +- etnaviv: don't allocate full resource as transfer staging +- etnaviv: check for valid TS as condition to create the staging resource +- etnaviv: reword comment about staging resource usage +- etnaviv: remove huge outdated comment +- etnaviv: move buffer range tracking into the PIPE_MAP_WRITE clause +- etnaviv: remove superfluous braces +- etnaviv: remove always true assert in etna_transfer_unmap +- etnaviv: remove bogus comment about replacing resource storage +- etnaviv: initialize VIVS_GL_BUG_FIXES +- etnaviv: fix read staging buffer leak +- Revert "ci/etnaviv: allow failure on failing test" +- mesa: enable NV_texture_barrier in GLES2+ (again) +- etnaviv: use correct blit box sizes when copying resource +- etnaviv: zero shared TS metadata block +- Revert "etnaviv: use correct blit box sizes when copying resource" +- mesa: add GL_APPLE_sync support + +Luigi Santivetti (1): + +- pvr: do not claim support for ASTC texture compression + +M Henning (31): + +- nv50/ir: Drop nir_jump_return handling +- nv50/ir: Remove ArgumentMovesPass +- nv50/ir: Remove Function.stackPtr +- nv50/ir: Remove dead loop from assignSlot +- nv50/ir: Remove SpillSlot +- nvc0: Keep nir directly in nvc0_program +- nv50: Keep nir directly in nv50_program +- nouveau: Delete nv50_ir_from_tgsi.cpp +- nouveau: Drop tgsi support from nv50_ir_prog_info +- nouveau: Drop ConverterCommon::Subroutine +- nouveau: Drop BuildUtil::DataArray +- nouveau: Drop BuildUtil::Location +- nouveau: Delete the nouveau_compiler tool +- nv/codegen: Call nir_shader_gather_info +- nv/codegen: Implement nir_op_fquantize2f16 +- nvk: Remove reference to genUserClip +- nv/codegen: Use nir_lower_clip +- nv50_ir_from_nir: Use nir's lower_fpow +- nv/codegen: Delete OP_POW +- nv/codegen: Fix an uninitialized variable warning +- nv/codegen: Delete OP_WRSV +- nv/codegen: Delete OP_EXP, OP_LOG +- nv/codegen: Remove fragCoord variable. +- nv/codegen: Merge from_common into from_nir +- nv/codegen: Remove unused clipVertexOutput var +- nv50_ir_ra: Delete unused functions +- nv/codegen: Delete unused OP_CONSTRAINT +- nv/codegen: Delete periodicMask32 +- nv/codegen: Remove Function::buildDefSets +- nv/codegen: Change copy-constructor call to assign +- nv/codegen: Delete copy and assign + +Maaz Mombasawala (2): + +- svga: Make surfaces shareable at creation. +- svga: Unify gmr and mob surface pool managers + +Marcin Ślusarz (16): + +- iris: avoid duplicating validation entries +- hasvk: remove dead code & comments related to mesh shading +- anv: drop support for VK_NV_mesh_shader +- intel/compiler: remove NV_mesh_shader support +- intel/compiler: remove redundant code +- anv: drop unused function +- anv: merge cases leading to the same code +- intel/compiler/mesh: compactify MUE layout +- intel/compiler,anv: put some vertex and primitive data in headers +- intel/compiler: load debug mesh compaction options once +- intel/compiler/test: fix crashes when TEST_DEBUG is set +- intel/compiler: add lsc_msg_desc_wcmask +- intel/compiler: add initial support for URB_LOGICAL_SRC_CHANNEL_MASK to lower_urb_write_logical_send_xe2 +- intel/compiler/mesh: fix position of output URB handle for xe2 +- intel/compiler/mesh: implement IO for xe2 +- intel/compiler: mask GS URB handles at thread payload construction + +Marek Olšák (125): + +- Revert "ac/nir/ngg: Follow intrinsic sources when analyzing before culling." +- glthread: determine global locking once every 64 batches to fix get_time perf +- mesa: fix 38% decrease in display list performance of Viewperf2020/NX8_StudioAA +- freedreno,lima,zink: update CI fixes and flakes +- util/u_queue: fix util_queue_finish deadlock by merging lock and finish_lock +- util/u_queue: always enable UTIL_QUEUE_INIT_SCALE_THREADS, remove the flag +- radeonsi: fix a CDNA regression breaking compute +- glthread: sync for VDPAU sync functions +- radeonsi: turn sh_base[PIPE_SHADER_VERTEX] into a constant in emit_draw_packets +- radeonsi: restructure the loop for non-indexed multi draws +- radeonsi: cosmetic changes to radeon_opt_* macros +- radeonsi: handle draw user SGPRs as tracked registers +- radeonsi: update obsolete comments about compiler queues +- radeonsi: remove si_compute.h, move the contents into si_pipe.h +- radeonsi: move si_update/emit_tess_io_layout_state into si_state_shaders.cpp +- radeonsi: move si_emit_spi_map into si_state_shaders.cpp +- radeonsi: move si_emit_rasterizer_prim_state out of si_emit_all_states +- radeonsi: remove splitting IBs that use too much memory +- radeonsi: add padding to si_resource to fix Viewperf2020/catiav5test1 perf +- radeonsi: remove unused check_mem parameter from si_sampler_view_add_buffer +- radeonsi: remove the draw counter with primitive restart from the HUD +- radeonsi: always inline si_prefetch_shaders +- radeonsi: specialize si_draw_rectangle using a C++ template +- radeonsi: add index parameter into si_atom::emit +- radeonsi: split direct pm4 emission from si_pm4_emit +- radeonsi: move code around si_pm4_emit_state into si_pm4_emit_state +- radeonsi: merge pm4 state and atom emit loops into one +- radeonsi: add a simple version of si_pm4_emit_state for non-shader states +- radeonsi: handle deferred cache flushes as a state (si_atom) +- radeonsi: remove render condition logic from si_draw by reordering atoms +- radeonsi: abort when failing to upload descriptors instead of skipping draws +- radeonsi: rename shader_pointers state -> gfx_shader_pointers +- radeonsi: merge si_upload_*_descriptors into si_emit_*_shader_pointers +- radeonsi: convert si_gfx_resources_add_all_to_bo_list to a state atom +- radeonsi/ci: update gfx11 failures +- radeonsi: move GE_CNTL emission from si_draw into si_emit_vgt_pipeline_state +- radeonsi: use num_patches_per_workgroup directly in si_get_ia_multi_vgt_param +- radeonsi: enable shader culling by default because it helps Viewperf +- radeonsi: rewrite how occlusion query precision is determined for performance +- radeonsi: set PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET on aux_context explicitly +- radeon_winsys: move allow_context_lost from cs_create to ctx_create +- winsys/amdgpu: rework how SW reset status is generated and reported +- radeon_winsys: add a ctx_set_sw_reset_status callback +- radeonsi: don't abort for descriptor failures, let the winsys handle it +- radeonsi: don't use threadID.yz/blockID.yz for copy_image if those are always 0 +- radeonsi: don't use threadID.yz/blockID.yz for compute_blit if they're always 0 +- nir: fix constant evaluation of fddx/fddy sourcing Inf & NaN constant +- nir/algebraic: collapse ALU opcodes sourcing NaN +- ac/gpu_info: add the /dev/dri/ filename into radeon_info +- Revert "ac: don't call ac_query_pci_bus_info from ac_query_gpu_info" +- ac: implement AMD_FORCE_FAMILY properly, remove SI_FORCE_FAMILY +- ac: document ac_shader_args::gs_vtx_offset +- ac: minor updates to packet documentation and definitions +- ac: change offsets of DMA_DATA dwords to prevent reg offset conflicts +- ac: improve the IB parser +- ac: update gfx11 shadowed register tables +- ac: add a standalone IB parser program +- ac/surface: trivial non-functional changes +- ac/surface: add radeon_surf::u::gfx9::uses_custom_pitch +- radeonsi: allow setting any index in radeon_set_sh_reg_idx +- radeonsi: rename uses_subgroup_info to uses_tg_size +- radeonsi: improve the heuristic when to use Wave32 for compute shaders +- radeonsi: simplify/merge emit_shader_ngg functions +- radeonsi: don't pass gl_Layer to PS for blit shaders +- radeonsi/gfx11: pass attribute ring addr via SGPR instead of memory for blits +- radeonsi: fix templated si_draw_rectangle callback for Navi14 +- nir: replace undef only used by ALU opcodes with 0 or NaN +- nir: remove nir_op_unpack_64 handling from nir_opt_undef +- ac/llvm: don't convert undef to 0 because nir_opt_undef does it now +- meson: use llvm-config instead of cmake to fix linking errors with meson 1.2.1 +- gallivm: fix build with LLVM 18 +- amd/llvm: fix build with LLVM 18 +- radeonsi: fix compute-only contexts +- ac/llvm: replace removed amdgcn.ldexp for LLVM 18 +- ac/perfcounter: remove a bogus assert to fix an assertion failure on gfx11 +- ac/llvm: set !fpmath 3.0 for llvm.sqrt +- ac/gpu_info: don't align IBs to the GL2 cache line size +- ac/llvm: fix flat PS input corruption +- amd: rename GFX110x to NAVI31-33 +- ac/gpu_info: replace ib_alignment with per-IP IB base and size alignments +- ac/gpu_info: pad IBs according to ib_size_alignment +- winsys/amdgpu: pad gfx and compute IBs with a single NOP packet +- Revert "radeonsi: specialize si_draw_rectangle using a C++ template" +- radeonsi/ci: update navi10 results +- gallium/util: fix GALLIUM_TESTS=1 by using cso_set_vertex_buffers_and_elements +- gallium/util: add more tests for compute-only contexts +- radeonsi: add another aux context for uploading shaders +- radeonsi: upload shaders via a staging buffer so as not to map VRAM directly +- ac/surface: don't require exact pitch for gfx6-8 tiled imports +- Revert "ac/gpu_info: override ib_size_alignment for VCN_DEC and JPEG" +- Revert "radv/amdgpu: fix alignment of command buffers" +- Revert "radv: fix alignment of DGC command buffers" +- Revert "winsys/amdgpu: pad gfx and compute IBs with a single NOP packet" +- Revert "ac/gpu_info: pad IBs according to ib_size_alignment" +- Revert "ac/gpu_info: replace ib_alignment with per-IP IB base and size alignments" +- nir: sort variables by location in nir_lower_io_passes to work around a bug +- nir: recompute IO bases after DCE in nir_lower_io_passes +- nir: add dual-slot input information into load_input intrinsics +- nir: take dual slot input info into account when computing IO driver locations +- nir: gather dual slot input information +- nir: expose reusable linking helpers for cloning uniform loads +- nir: handle nir_var_mem_ubo in nir_clone_uniform_variable +- ac/gpu_info: split ib_alignment as ip[type].ib_alignment +- ac/gpu_info: move ib_pad_dw_mask into ip[] +- ac/gpu_info: drop the hack unifying all IB alignments +- ac/gpu_info: conservatively decrease IB alignment and padding to 256B +- ac/gpu_info: set gfx and compute IB padding to only 8 dwords +- winsys/amdgpu: properly pad the IB in amdgpu_submit_gfx_nop +- winsys/amdgpu: correctly pad noop IBs for RADEON_NOOP=1 +- winsys/amdgpu: pad gfx and compute IBs with only 1 NOP +- ac/gpu_info: don't allow register shadowing with SR-IOV due to bad performance +- radeonsi: disable register shadowing without SR-IOV to fix bad performance +- winsys/amdgpu: don't send CP_GFX_SHADOW chunk if shadow address is not set +- radeonsi/ci: update gfx1100 results +- nir: split FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP* flags +- nir/algebraic: use only signed_zero_preserve_* for addition by 0 patterns, etc. +- mesa: don't pass Infs to the shader via gl_Fog.scale +- radeonsi/ci: update the runner for new build scripts +- radeonsi/ci: enable GTF tests in the runner +- radeonsi/ci: enable GLES CTS in the runner +- radeonsi/ci: update failures and flakes +- amd/common: update DCC for gfx11.5 +- radeonsi: initialize perfetto in the right place +- radeonsi/gfx11: don't set OREO_MODE to fix rare corruption +- nir: fix gathering TESS_LEVEL_INNER/OUTER usage with lowered IO + +Marek Vasut (1): + +- etnaviv: Fully replicate back stencil config + +Mark Collins (10): + +- tu/a7xx: Adapt r3d blits for A7xx +- freedreno/rnn: Remove %n usage in fprintf +- freedreno: Only add drm/computerator when system_has_kms_drm +- freedreno/decode: Support building replay for multiple KMDs +- freedreno+meson: Add lua+libarchive+libxml from Meson WrapDB +- meson: Warn about side-effects from DRM for FD KMDs +- meson: Update libarchive to v3.7.2-2 +- freedreno/common: Add max_sets property to A6xxGPUInfo +- tu: Support higher descriptor set count for A7XX +- tu,util/driconf: Add option to not reserve descriptor set + +Mark Janes (1): + +- intel: allow reduced memory usage for INTEL_MEASURE + +Martin Roukala (né Peres) (22): + +- radv/ci: drop the auto-reboot-on-hang for vkcts-navi10 +- radv/ci: use the default kernel on vkcts-navi10 +- zink/ci: automatically reboot when hitting a kernel BUG on vangogh +- zink/ci: document more flakes seen on vangogh +- radv/ci: move vkcts-navi10 testing to KWS +- radv/ci: add more tests to the navi10 vkcts flake list +- radv/ci: increase the parallelism of the vkcts-navi21 job +- radv/ci: add more tests to the navi21 vkcts flake list +- radv/ci/vkcts-navi21: catch all the line_stipple_(enable|params) flakes +- radv/ci/vkcts-navi21: document more flakes +- radv/ci/vkcts-navi10: catch all the line-related flakes +- radv/ci: update the vkcts gfx1100 flake/fail lists +- radv/ci: add a manual job to run vkcts on navi31 +- radv/ci: add a manual job for vkd3d-proton on navi31 +- ci/vkcts-vangogh: mark dEQP-VK.dynamic_rendering.primary_cmd_buff.basic.* as flake +- ci/vkcts-navi21: mark more of the RT handles checks as flakes +- ci: make B2C_JOB_VOLUME_EXCLUSIONS to all .b2c-test jobs +- zink/ci: remove 19 tests from the zink-radv-polaris10-fails list +- ci/b2c: switch containers to a back-up ahead of valve-infra renaming +- zink/ci: remove 42 tests from the zink-radv-polaris10-fails list +- radv/ci: tighten the vkcts-navi21 timeouts +- zink/ci: tighten the zink-radv-vangogh timeouts + +Martin Stransky (1): + +- llvmpipe: fix UAF in lp_scene_is_resource_referenced. + +Mary (6): + +- nouveau/mme: Add initial Fermi definition +- nouveau/mme: Add Fermi builder +- nouveau/mme: Add Fermi simulator +- nouveau/mme: Add Fermi hardware tests +- agx: Move nir_lower_fragcolor out of agx_preprocess_nir +- agx: Ensure to lower 1D image load/store to 2D + +Mary Guillemard (4): + +- nir: Add NVIDIA-specific geometry shader opcodes +- venus: skip bind sparse info when checking for feedback query +- zink: Check for VK_EXT_extended_dynamic_state3 before setting A2C +- venus: Do not submit batch manually when no feedback is required + +Matt Coster (21): + +- pvr: Pad rogue_regarray_cache_key union members to avoid UB +- pvr: Clean up extension tables +- pvr: Refactor pvr_GetPhysicalDeviceProperties2() +- docs: Fixup imagination/pvr extension support +- pvr: Add VK_KHR_get_display_properties2 +- pvr: Add VK_KHR_get_memory_requirements2 +- pvr: Add VK_KHR_get_surface_capabilities2 +- pvr: Print VkStructureType name on pvr_debug_ignored_stype() +- pvr: Add VK_KHR_copy_commands2 +- pvr: Don't override commands copied to new buffer when extending cs +- pvr: Do not require TA_STATE_HEADER.pres_ispctl_dbsc for {db,sc}enable +- pvr: Zero tail of cs buffers after linking when dumping cs +- pvr: Cleanup comments in pvr_physical_device_get_supported_*() +- pvr: Don't rely on GNU void pointer arithmetic +- pvr: Force compile error on GNU void pointer arithmetic +- pvr: Switch to common pipeline cache implementation +- pvr: Use vk_sampler base +- pvr: Clean up & fix sampler border color support +- pvr: Don't pass pvr_physical_device when only device info is needed +- pvr: Minor refactor of pvr_device.c +- pvr: Use common physical device properties + +Matt Turner (10): + +- Revert "intel/fs: only avoid SIMD32 if strictly inferior in throughput" +- intel: Rearrange for next commit +- intel: Consider with_intel_clc in with_any_intel +- intel: Only build blorp if drivers are enabled +- intel: Only build ds if drivers are enabled +- intel: Only build perf if drivers or tools are enabled +- intel: Allow using intel_clc from the system +- intel: Limit Intel Vulkan RT to x86_64 +- r600: Add missing dep on git_sha1.h +- util: Include stdint.h in libdrm.h + +Mauro Rossi (7): + +- nouveau/ws: fix building error in nouveau_ws_push_dump() +- vulkan/meta: fix gnu-empty-initializer build error +- nouveau/mme: fix print inst for case MME_FERMI_OP_MERGE +- anv/android: remove numFds check +- hasvk/android: remove numFds check +- Android.mk: filter out cflags to build with Android 14 bundled clang +- Android.mk: disable android-libbacktrace to build with Android 14 + +Mike Blumenkrantz (293): + +- ci: bump VVL to 1.3.257 +- zink: set pipeline dynamic state count after all dynamic states are set +- zink: set feedback attachments on batch init +- zink: be even dumber about buffer refs when replacing storage +- zink: emit SpvCapabilitySampleMaskPostDepthCoverage with SpvExecutionModePostDepthCoverage +- zink: fix the fix for separate shader program refcounting +- kopper: handle pixmap creation failure more gracefully +- glxsw: check geometry of drawables on creation +- kopper: move pixmap param for drawable creation to info struct +- glx/dri3: split out modifier check +- glx/sw: check for modifier support in the kopper path +- kopper: pass modifier availability to drawable creation +- kopper: determine modifier support per-drawable +- zink: don't clobber descriptor mode on multiple screen creation +- nir: fix slot calculations for compact variables with location_frac +- lavapipe: use the component offset directly for xfb +- nir: add a helper for calculating variable slots +- radv: bump max xfb output to 128 +- ir3: bump max xfb output to 128 +- gallium: bump PIPE_MAX_SO_OUTPUTS to 128 +- zink: add feedback loop exts to optimal profile +- glsl: only explicitly check GS components in PSIZ injection with output variables +- lavapipe: statically allocate fb attachment array +- lavapipe: zero fb attachment array at rp start +- lavapipe: don't check geometry for fb attachments +- lavapipe: be slightly more permissive for bad apps (and cts) with dynrender +- lavapipe: VK_EXT_host_image_copy +- zink: better handle separate shader dsl creation when no bindings exist +- zink: force image barriers after dmabuf import +- ci: bump VVL to 1.3.261 +- zink: use VK_WHOLE_SIZE when binding null db buffer descriptors +- zink: unset line stipple ds3 state flags when stipple not available +- nir/lower_io_to_scalar: fix 64bit io splitting +- nir/linking_helpers: force type matching in does_varying_match +- nir/print: print location names for (some) tess slots +- nir/print: always group variables by type when printing +- zink: add batch refs for transient images +- zink: fix zs resolve attachment indexing +- zink: don't add VK_IMAGE_USAGE_ATTACHMENT_FEEDBACK_LOOP_BIT_EXT for transient images +- zink: don't append msrtss to dynamic render if not supported +- zink: set msrtss depth resolve mode when enabled +- zink: hook up VK_KHR_workgroup_memory_explicit_layout +- zink: propagate have_workgroup_memory_explicit_layout to ntv +- zink: use SPV_KHR_workgroup_memory_explicit_layout when available +- zink: add more locking for pipeline cache +- zink: add VK_PIPELINE_CACHE_CREATE_EXTERNALLY_SYNCHRONIZED_BIT_EXT +- aux/trace: fix winsys handle dumping +- zink: generated tcs is on the tes, not the vs +- zink: apply ZINK_DEBUG=noopt to linked separate shaders +- gallivm: handle A8_UNORM image stores +- llvmpipe: enable A8_UNORM for shader images +- llvmpipe: export PIPE_CAP_IMAGE_LOAD_FORMATTED +- lavapipe: GetRenderingAreaGranularityKHR +- llvmpipe: block weird uses of subsampled formats in buffers +- llvmpipe: fix early depth + alpha2coverage + occlusion query interaction +- lavapipe: fix BindVertexBuffers2 buffer size handling +- lavapipe: fix resolves where src image has a layer offset +- lavapipe: block yuv formats from getting blit feature flags +- lavapipe: BindIndexBuffer2 +- lavapipe: GetDeviceImageSubresourceLayoutKHR +- lavapipe: VK_REMAINING_ARRAY_LAYERS for copy ops +- lavapipe: maintenance5 +- zink: fix xfb buffer array sizing to use buffer limit, not output +- zink: move ZINK_DEBUG=nir printing to just before compile +- draw: fix so debug offset printing +- zink: reindex ssa defs before dumping debug shaders +- lavapipe: zero-init pipe_sampler_state +- zink: explicitly set non-optimal last_vertex_stage shader key on ctx create +- zink: fix big tcs output io +- zink: don't try to replace separate shader prog in noopt mode +- zink: pre-convert mode in fixup_io_locations +- zink: add a special separate shader i/o mode for legacy variables +- nir: minor fixes for io_to_scalar +- nir/lower_io: add a new doubles-only 64bit lowering option +- nir: add a filter cb to lower_io_to_scalar +- d3d10umd: use cso_context to set vertex buffers and elements +- virgl: move virgl_vertex_elements_state to header +- virgl: fix some indentation +- nouveau: calloc vertex csos +- gallium: move vertex stride to CSO +- zink: fix null config screen creation +- zink: fix crash in lower_pv_mode_gs_store +- u/draw: skip zero-sized indirect draws +- lavapipe: handle VkPipelineCreateFlagBits2KHR +- lavapipe: handle VkBufferUsageFlags2KHR +- zink: ci updates +- zink: track start/stop of a couple query types +- zink: require EDS1 for CWE usage +- zink: unset primgen suspended flag when ending a primgen query +- zink: rework rast-discard for primgen queries +- zink: rip out some awkward parts of the old non-cwe path +- zink: drop CWE requirement for renderpass tracking with primgen queries +- nir/zink: fix gs emulation xfb_info sizing +- zink: move fragcolor lowering further along the compile process +- zink: add a mode param to find_var_with_location_frac +- zink: use lowered io (kinda) for i/o vars +- zink: stop lowering indirect derefs +- ntt: handle interp intrinsics as derefs +- zink: delete split_blocks pass +- zink: delete lower_64bit_vertex_attribs pass +- zink: fix clip/cull dist xfb inlining +- zink: delete all the extra gross xfb handling +- zink: stop using pipe_stream_output +- zink: remove pipe_stream_output from function params +- zink: ci updates +- aux/trace: print bindless handles as pointers +- zink: remove unused param from create_ici +- zink: split create_ici to init and eval +- zink: add maintenance extensions to profile +- zink: use maintenance5 +- zink: use real A8_UNORM when possible +- vk/graphics: fix CWE handling with DS3 +- Revert "vk/wsi/x11: handle geometry updating more asynchronously" +- r600: store the mask of buffers used by a vertex state +- r600: better tracking for vertex buffer emission +- zink: wait on async fence during ctx program removal +- zink: handle patch variable locations for separate shaders better +- zink: don't start multiple cache jobs for the same program +- zink: use the "set" optimal key for prog last_variant_hash for consistency +- zink: sanitize optimal keys +- zink: copy some cs shader properties to the program struct +- zink: handle global atomic intrinsics +- zink: use Aligned with global load/store ops +- zink: fix rewrite_read_as_0 filtering +- rusticl: fixes for zink shader images +- zink: pass KERNEL shaders through successfully +- zink: add a618 flake +- zink: break out ds3 state resetting +- zink: be consistent with ds3 state resetting for blits +- zink: fix optimal_keys warning message +- zink: force-reset unordered flags for buffer barriers on non-matching batch access +- zink: reset unordered flags for image barriers on non-matching batch access +- zink: make image barrier init functions void return +- zink: simplify some image barrier conditionals +- zink: remove sync TODO +- zink: add lavapipe flake +- ci: disable nouveau shaderdb +- egl/dri3: only set driver_name if not already set +- egl: call dri3_x11_connect() for zink +- egl: bind dri2_set_WL_bind_wayland_display for zink when necessary +- zink: be more precise about flagging rp changes around unordered u_blitter +- zink: don't block reordering during ref updates in unordered blits +- lavapipe: update vbo indices before propagating stride +- lavapipe: fix pipeline stride propagation +- zink: fix linear modifier dmabuf imports +- zink: polaris ci updates +- aux/tc: handle stride mismatch during rp-optimized subdata +- zink: always add a per-prog ref for gpl libs +- zink: use a pointer to simplify submit struct mechanics +- zink: make zink_resource_image_barrier2_init public +- zink: add a third submitinfo (unused for now) +- zink: make submitinfo handling easier to manage with enum +- zink: add another submitinfo for fd semaphore waits +- zink: add a screen cache for fd semaphores +- zink: add a util for getting cached fd semaphores +- zink: hook up cached fd semaphore usage for batch signal/waits +- zink: handle implicit sync for dmabufs +- zink: handle multi-plane implicit sync +- zink: ci updates +- zink: set is_xfb=false for all i/o variables +- zink: reorder bindless io lowering +- zink: fix typing on bindless io lowering +- zink: delete some bindless io lowering code +- zink: use nir_io_semantics::num_slots for indirect var creation +- zink: simplify an arrayed io check during variable creation +- zink: use explicit stride from types instead of copying old_var stride +- zink: use MAX_PATCH_VERTICES directly for arrayed io var sizing +- zink: use explicit sizing for builtins when creating variables +- zink: create new vars without copying existing ones +- zink: add a new linker pass to handle mismatched i/o components +- zink: use right function to get src_type in eliminate_io_wrmasks +- zink: re-rework i/o variable handling to make having variables entirely optional +- ci: bump VVL to 1.3.263 +- zink: simplify redundant is_buffer check +- zink: use VkFormatProperties3 +- lavapipe: handle VkHostImageCopyDevicePerformanceQueryEXT +- lavapipe: don't advertise UNDEFINED layout for HIC +- zink: hook up VK_EXT_host_image_copy +- zink: move mem type detection up in file +- zink: disable HIC without resizable BAR +- zink: add a fixup method for extra driver props +- zink: fix some off-by-one indentation +- zink: use some return codes for check_ici errors +- zink: check/use suboptimal HIC during ici init +- zink: use HIC for image subdata when possible +- zink: slightly refactor psiz deletion during linking +- zink: delete all psiz=1.0 stores if maintenance5 is present +- nir/inline_uniforms: fix oob access with nir_find_inlinable_uniforms +- zink: add ZINK_DEBUG=quiet +- zink: imply ZINK_DEBUG=quiet if ZINK_DEBUG=optimal_keys is set on turnip +- zink: set optimal_keys for turnip jobs +- aux/tc: fix staging buffer sizing for texture_subdata +- aux/tc: fix address calc for segmented texture subdata +- zink: ci updates +- lavapipe: KHR_map_memory2 +- zink: slightly refactor pipeline compile selection +- zink: add a flag for combined pipeline compile for doing FAIL_ON_PIPELINE_COMPILE_REQUIRED +- zink: remove an intermediate variable in pipeline compile selection +- zink: use FAIL_ON_PIPELINE_COMPILE_REQUIRED for GPL path +- zink: pass a stage mask to pipeline create functions +- glsl: check for xfb setting xfb info +- zink: don't warn about missing scalarBlockLayout on v3dv +- aux/tc: fix renderpass tracking fb state clobber scenario +- vk/enum2str: add more max enum vendors +- aux/tc: fix rp info handling around tc_sync calls +- aux/tc: don't use pipe_buffer_create_with_data() for rp-optimized subdata +- zink: flag db maps as unsynchronized +- lavapipe: clamp cache uuid size +- lavapipe: EXT_load_store_op_none +- tu: handle unused color attachments without crashing +- zink: use much bigger dummy surfaces +- zink: propagate rp_tc_info_updated across unordered blits +- zink: use null attachments for null attachments with dynamic render +- egl/swrast: expose EXT_swap_buffers_with_damage and EXT_present_opaque +- egl/wayland: split out wl drm extension init +- egl/wayland: use more registry listeners to better handle device init +- egl/wayland: enable WL_bind_wayland_display for zink +- zink: delete injected pointsize during shader creation +- zink: require maintenance5 for shobj +- zink: delete a non-maintenance5 workaround for shobj use +- lavapipe: set separate_shaders for shader objects +- zink: set workgroup_memory_explicit_layout for shader validation +- zink: add a ZINK_DEBUG=validation alias +- zink: fix semaphore signal ordering +- zink: move swapchain fence to swapchain object +- zink: avoid UAF on wayland async present with to-be-retired swapchain +- zink: always trace_screen_unwrap in acquire +- lavapipe: fix variable descriptor count support handling +- lavapipe: always set independent blend +- lavapipe: more vertex stride fixups +- lavapipe: set default viewport and scissor count for cmdbufs +- lavapipe: set default min sample shading to 1 +- glx: XFree visual info +- radv: fix external handle type queries for dmabuf/fd +- zink: fix crashing in image rebinds +- zink: move push descriptor disable to driver workarounds +- zink: move v3dv scalarBlockLayout workaround +- zink: fix end-of-batch barrier pipeline stages +- zink: guarantee egl syncobj lifetime +- aux/trace: dump enum names for map usage +- gallium: add PIPE_MAP_NONE +- Revert "egl/wayland: Add image loader extension for swrast" +- egl/wayland: don't block in swrast when updating buffers for zink +- egl/wayland: return sooner from swrast_update_buffers() if zink +- zink: don't check submit count for unflushed usage +- egl: don't set ForceSoftware for all zink loading +- zink: error at handle export on missing EXT_image_drm_format_modifier +- gbm: delete some zink handling +- zink: apply ZINK_DEBUG=quiet to all missing feature warnings +- zink: set ZINK_DEBUG=quiet for polaris jobs +- lavapipe: don't block begin/end cmdbuf pipeline barriers +- ci: add a630 trace flakes +- zink: shrink vectors during optimization +- zink: always clamp shader stage in descriptor handling +- zink: add set_global_binding +- zink: eliminate samplers from no-sampler CL texops +- zink: add some checks to determine whether queue is init on screen destroy +- zink: don't destroy any simple_mtx_t objects during screen destroy +- zink: don't destroy uninitialized disk cache thread +- zink: reorder glsl_type_singleton_init_or_ref call +- zink: use screen destructor for creation fails +- zink: fix readback_present locking +- zink: add automatic swapchain readback using heuristics +- lavapipe: VK_EXT_nested_command_buffer +- zink: ignore unacquired swapchain images during end-of-frame flush +- nir/lower_fragcolor: preserve location_frac +- zink: update pointer for GPL pipeline cache entry formats +- zink: fix legacy depth texture rewriting for single component reads +- egl: unify dri2_egl_display creation +- egl: init dri3 version info during screen creation +- egl/glx: don't load non-sw zink without dri3 support +- egl: add automatic zink fallback loading between hw and sw drivers +- glx: add automatic zink fallback loading between hw and sw drivers +- ci: don't set GALLIUM_DRIVER for zink +- egl/wayland: only add more registry listeners for hardware devices +- zink: only increment image_rebind_counter on image export if binds exist +- zink: check for sampler view existence during zink_rebind_all_images() +- zink: use weston for anv ci +- zink: blow up broken xservers more reliably +- zink: delete some dead modifier handling +- ci: skip implicit modifier piglits for zink +- zink: don't block large vram allocations +- zink: add copy box locking +- zink: emit SpvCapabilitySampleRateShading with SampleId +- zink: always set VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT for usermem +- zink: clamp resolve extents to src/dst geometry +- zink: only emit xfb execution mode for last vertex stage +- aux/u_transfer_helper: set rendertarget bind for msaa staging resource +- zink: unset explicit_xfb_buffer for non-xfb shaders +- mesa/st/texture: match width+height for texture downloads of cube textures +- zink: add more locking for compute pipelines +- radv: correctly return oom from the device when failing to create a cs +- zink: check for cbuf0 writes before setting A2C + +Mohamed Ahmed (19): + +- vulkan/util: Support 10-bit and 12-bit color formats in ycbcr_info in vk_format.c +- vulkan/util: Support VK_EXT_ycbcr_2plane_444_formats color formats in vk_format.c +- vulkan/util: Use ycbcr_info for multiplane helpers in vk_format.c +- nvk: implement vkGetDeviceImageMemoryRequirementsKHR() +- nvk: add stub for vkGetDeviceImageSparseMemoryRequirementsKHR() +- nvk: implement vkGetDeviceBufferMemoryRequirementsKHR() +- nvk: advertise VK_KHR_maintenance4 +- nvk: advertise DemoteToHelperInvocation +- nvk: Enable multiplane images and image views +- nouveau/nvk: Add YCbCr sampler NIR lowering pass +- nouveau/nvk: Support multi-plane descriptors in nvk_nir_lower_descriptors.c +- nouveau/nvk: Create helper function for sampler creation +- nouveau/nvk: Add multiple sampler planes for CONVERSION_SEPARATE_RECONSTRUCTION_FILTER_BIT +- nouveau/nvk: Enable VK_KHR_sampler_ycbcr +- util/format: Add G8B8_G8R8_422_UNORM and B8G8_R8G8_422_UNORM formats +- vulkan/format: Translate G8B8G8R8_422_UNORM and B8G8R8G8_422_UNORM properly +- nvk: Enable SEPARATE_RECONSTRUCTION_FILTER_BIT for multi-planar formats only +- nvk: Enable MIDPOINT_CHROMA_SAMPLES_BIT for multi-planar formats only +- nil: Add support for G8B8_G8R8_UNORM and B8G8_R8G8_UNORM + +Nanley Chery (33): + +- iris: Remap DRM_FORMAT_MOD_INVALID more often during import +- anv: Don't support ASTC images with modifiers +- intel: Add and use isl_drm_modifier_get_plane_count +- anv: Handle explicit surface layout of DG2_RC_CCS +- anv: Reduce accesses of isl_mod_info->aux_usage +- iris: Reduce accesses of mod_info->aux_usage +- crocus: Delete modifier with aux code +- hasvk: Delete modifier with aux code +- iris: Swap stencil and modifier aux assignment order +- intel: Describe modifier compression with booleans +- intel/isl: Move the Tile4 modifier score case down +- intel/isl: Add a score for DG2_RC_CCS +- intel/blorp: Ambiguate after CCS resolves on gfx7-8 +- iris: Reorder render_aux_usage parameters +- iris: Pass the render format to prepare_render +- iris: Create BLORP surfaces after resource preparation +- iris: Handle clear color compatibility in prepare_render +- iris: Sample more texture view fast-clears on gfx11+ +- iris: Fix aux usage tracking in prepare_render +- iris: Fix iris_copy_region calls involving FCV_CCS_E +- iris: Drop get_copy_region_aux_settings +- iris: Inline iris_can_sample_mcs_with_clear +- anv: Initialize the clear color more often for FCV +- intel: Return a bool from intel_aux_map_add_mapping +- anv: Move scope of CCS binding determination +- anv: Allocate space for aux-map CCS in image bindings +- anv: Wrap aux surface image binding queries +- anv: Refactor CCS disabling at image bind time +- anv: Place images into the aux-map when safe to do so +- anv: Loosen anv_bo_allows_aux_map +- anv: Meet CCS alignment reqs with dedicated allocs +- anv: Delete implicit CCS code +- intel/isl: Add scores for GEN12_RC_CCS and MTL_RC_CCS + +Neal Gompa (1): + +- asahi: Fix 32-bit x86 build with correct data type for overflow error message + +Neha Bhende (1): + +- ntt: lower indirect tesslevels in ntt + +Paul Gofman (2): + +- driconf: add a workaround for Captain Lycop: Invasion of the Heters +- driconf: add a workaround for Rainbow Six Extraction + +Paulo Zanoni (15): + +- anv: rename the vm_bind vfuncs +- anv: add a new vm_bind vfunc +- anv/xe: make vm_binds async +- anv/xe: return failure in case waiting for the vm_bind syncobj fails +- anv: remove misleading comment about batch_len +- iris: assert bufmgr->bo_deps_lock is held +- iris: avoid stack overflow in iris_bo_wait_syncobj() +- iris: assert(bo->deps) after realloc() +- intel/isl: add ISL_SURF_USAGE_SPARSE_BIT +- intel/isl: simplify the check for maximum surface size +- anv/sparse: add the initial code for Sparse Resources +- anv/sparse: get ready to issue a single vm_bind ioctl per non-opaque bind +- anv/sparse: add INTEL_DEBUG=sparse +- anv: enable sparse resources by default +- vulkan: fix potential memory leak in create_rect_list_pipeline() + +Pavel Ondračka (44): + +- r300: update RV370 failures +- r300: check for index overflow when translating from TGSI +- r300: source register index is always unsigned +- r300: bump the RC_MAX_INDEX_BITS +- r300: normal instruction can't have presubtract op +- r300: add a helper for checking number of temporary sources +- r300: cycles estimate for shader-db +- r300: fix cycles calculation +- r300: don't abort on flow control when using draw for vs +- r300: add dEQP baseline for RV370 with forced swtcl +- r300: copy ntt to r300 compiler +- r300: add lower_sqrt to nir option +- r300: remove unused intrinsics in ntr +- r300: remove irrelevant opcodes in ntr +- r300: remove unused integer support in ntr +- r300: remove ntr_tgsi_usage_mask +- r300: remove more unused 64-bit pieces from ntr +- r300: simplify vectorization rules +- r300: remove more ntr unused helpers +- r300: remove the unneeded ntr_lower_vec_to_reg callback +- r300: remove unneeded 64bit and atomic lowering passes +- r300: remove unused ntr default settings +- r300: remove ntr default options +- r300: simplify ntr_emit_load_ubo +- r300: simplify ntr_emit_load_input +- r300: remove some virglrenderer specifics from ntr +- r300: simplify ntr_setup_uniforms +- r300: simplify ntr_output_decl +- r300: simplify ntr_try_store_in_tgsi_output +- r300: remove some unsupported texture opcodes +- r300: remove unused barrier code from ntr +- r300: simplify ntr_get_gl_varying_semantic +- r300: remove the nrt main optimization loop +- r300: reorder for easier presubtract 1-x pattern recognition +- r300: exit early in presubtract is not supported +- r300: implement bias presubtract +- r300: convert x * 2 into x + x for presubtract +- r300: move power of two multipliers down +- r300: there is no limitation on presubtract source file +- r300: use w channel for scalar opcodes if possible +- r300: reduce number of iterations for vertex shader loops +- r300: enable nir_move_vec_src_uses_to_dest +- nir/move_vec_src_uses_to_dest: skip reuse if vec is used only once in store_output +- nir/move_vec_src_uses_to_dest: allow to skip reuse of constant sources + +Philipp Zabel (1): + +- etnaviv: fix segfault after compile failure + +Pierre-Eric Pelloux-Prayer (18): + +- radeonsi/sdma: use multiple commands if required +- radv/sdma: use multiple commands if required +- radv/sdma: use correct limits for gfx10.3 +- glx: drop the 'libGL' log prefix +- loader: refactor DRI_PRIME handling code +- loader: extend DRI_PRIME to support =N +- loader: add DRI_PRIME_DEBUG env var +- device_select_layer: support DRI_PRIME=n +- docs: update DRI_PRIME documentation +- device_select: add shortcut for MESA_VK_DEVICE_SELECT_FORCE_DEFAULT_DEVICE +- st/mesa: check renderbuffer before using it +- radeonsi: emit framebuffer state after allocating cmask +- amd/common: update addrlib for gfx11.5 +- amd/common: add registers for gfx11.5 +- ac/nir: extract must_wait_attr_ring helper +- amd, radeonsi: Add code to enable gfx11.5 +- mesa: restore call to _mesa_set_varying_vp_inputs from set_vertex_processing_mode +- radeonsi: check sctx->tess_rings is valid before using it + +Piotr Kocia (2): + +- nir: Remove dead nir_const_value variables +- glsl: ir_function_param_visitor::visit_enter always true condition + +Qiang Yu (77): + +- aco,radv: replace tess_input_vertices shader info param +- radeonsi: aco does not pass LS outputs to HS by arg +- radeonsi: extract si_get_prev_stage_nir_shader to be shared with aco +- radeonsi: init aco shader info for merged LS/HS +- radeonsi: simplify si_build_wrapper_function +- radeonsi: move vertex shader vb desc input sgpr args to last +- radeonsi: remove param type check in wrapper function +- radeonsi: refine si_llvm_ls_build_end +- radeonsi: refine si_llvm_es_build_end +- radeonsi: aco compile support merged mono shader +- radeonsi: calculate lds size for merged shaders +- radeonsi: enable aco compile for mono merged LS/HS +- radeonsi: enable aco compile for mono merged ES/GS +- aco: extract aco_compile_shader_part from aco_compile_ps_epilog +- aco: add p_end_with_regs pseudo instruction +- aco: move jump to epilog out of ic_merged_wave_info +- aco: add tcs end regs for epilog usage +- aco: allow tcs with epilog to keep nir store output instruction +- aco: add pending_lds_access option for insert waitcnt +- aco: add tcs epilog generation for radeonsi +- aco: don't emit s_endpgm for tcs with epilog +- aco: skip scratch init when no scratch arg provide +- aco,radeonsi: save const addr to symbol +- ac/nir/tess: move tess factor output out of control flow +- aco: use semantic location as io temp index +- radeonsi: add exec_size to shader binary +- radeonsi: support upload multi part shader binary +- radeonsi: share si_get_tcs_out_patch_stride with aco +- radeonsi: fill part mode tcs aco shader info +- radeonsi: extract si_llvm_build_shader_part +- radeonsi: remove separate_prolog arg from prolog/epilog build +- radeonsi: add si_get_tcs_epilog_args +- radeonsi: change si_fill_aco_options args +- radeonsi: add si_aco_build_shader_part +- radeonsi: part mode standalone tcs support aco compile +- radeonsi: remove unused arg of get_tcs_tes_buffer_address +- aco: simplify setup_tcs_info +- aco: pass sw_stage when setup_isel_context +- aco: prepare fix_ls_vgpr_init_bug to be used by gl vs prolog +- aco: add vs prolog instruction selection for radeonsi +- aco: add aco compile interface for radeonsi vs prolog +- aco: do not fix_exports when program is prolog +- radeonsi: fill aco_shader_info->is_monolithic +- radeonsi: remove is_monolithic from vs prolog key +- radeonsi: extract si_get_vs_prolog_args to be shared with aco +- radeonsi: fix aco options has_ls_vgpr_init_bug setup +- radeonsi: add vs prolog aco build +- radeonsi: set vs has prolog aco shader info +- radeonsi: enable aco compile for part mode standalone vs +- aco,radv,radeonsi: rename is_monolithic to merged_shader_compiled_separately +- ac,radeonsi: move ps arg pos_fixed_pt to ac_shader_args +- aco: do not eliminate final exec write when p_end_with_regs block +- aco: remove p_end_with_regs from needs_exact() +- aco: add ps prolog generation for radeonsi +- aco: handle ps outputs from radeonsi +- aco: add create_fs_end_for_epilog for radeonsi +- aco,radv: remove unused ps epilog info fields +- aco,radv: rename ps epilog info inputs to colors +- aco: simplify export_fs_mrt_color +- aco,radv: add radeonsi spec ps epilog code +- aco: compact ps expilog color export for radeonsi +- aco,radv,radeonsi: pass spi ps input ena and addr +- aco: do not fix_exports when program has epilog +- aco: fix assertion fail when program contains empty block +- aco: create exit block for p_end_with_regs to branch to +- aco: wait memory ops done before go to next shader part +- radeonsi: reduce sgpr count for scratch_offset when aco +- radeonsi: init spi_ps_input_addr for part mode ps +- radeonsi: extract si_prolog_get_internal_binding_slot +- radeonsi: extract si_get_ps_prolog_args to be shared with aco +- ac,radeonsi: remove unused ps prolog key fields +- radeonsi: add ps prolog shader part build +- radeonsi: extract si_get_ps_epilog_args to be shared with aco +- radeonsi: fill aco shader info for ps part +- radeonsi: add ps epilog shader part build +- radeonsi: enable aco compile for part mode ps +- radeonsi: disable disk cache when use aco + +Rebecca Mckeever (32): + +- vulkan/runtime: Add helper functions for VK_EXT_host_image_copy +- nouveau/codegen: Support nir_intrinsic_load_workgroup_id_zero_base +- nouveau/codegen: Set lower_device_index_to_zero +- nvk: Convert system values for gl_PointCoord and PointCoord into inputs +- nvk: Add base_group to root descriptor table +- nvk: Lower base_workgroup_id +- nvk: Implement nvk_CmdDispatchBase and delete nvk_CmdDispatch +- nvk: Advertise KHR_device_group +- nvk: Add VK_FORMAT_B4G4R4A4_UNORM_PACK16 format to nil_format_info table +- nvk: Add A4B4G4R4 formats to nil_format_info table +- nvk: Advertise EXT_4444_formats +- nvk: Enable shadow sampling +- nvk: Implement VK_EXT_non_seamless_cube_map +- nouveau/nil: Add macros for ufixed +- nvk: Implement VK_EXT_image_view_min_lod +- nvk: Update mutable descriptor struct type +- nvk: Replace asserts with conditional that sets type_list = NULL +- nvk: Implement nvk_GetDescriptorSetLayoutSupport +- nvk: Enable VK_KHR_maintenance3 +- nvk: Advertise VK_EXT_mutable_descriptor_type +- nvk: Set image index to zero for NULL nvk_buffer_view +- nvk: Advertise VK_EXT_image_robustness +- nvk: Advertise VK_EXT_robustness2 +- nvk: Add view_index to root descriptor table +- nvk: Lower nir_intrinsic_load_view_index +- nvk: Add draw support for multiview +- nvk: Add query support for multiview +- nvk: Add input attachments support for multiview +- nvk: Advertise VK_KHR_multiview +- nvk: Load view_mask to shadow scratch in nvk_CmdBeginRendering +- nvk: Combine CLEAR_VIEWS and CLEAR_LAYERS MME macros +- nvk: Move code inside view mask loops to a helper function + +Rhys Perry (89): + +- ac/llvm: fix AC_TM_CHECK_IR +- radv: fix radv_get_ballot_bit_size with CS +- ac/llvm: fix wave32 ac_build_mbcnt_add with 64-bit mask +- ac/llvm: skip ballot zext for 32-bit dest with wave32-as-wave64 +- radv: add conformant_trunc_coord to cache UUID +- radv: don't unset TRUNC_COORD if conformant_trunc_coord=true +- ac/nir: always round cube array layers +- nir/unsigned_upper_bound: fix phi(bcsel) +- nir/tests: add test for unsigned_upper_bound with loop header phis +- nir/opt_dead_cf: remove nodes after a jump earlier +- nir/tests: add nir_opt_dead_cf_test.jump_before_constant_if +- aco: insert s_nop before VGPR deallocation +- nir/lower_shader_calls: vectorize stack access for all shaders +- radv: workaround WWZ exporting index=1 through location=1 +- radv: correctly skip MRT output NaN fixup for meta shaders +- radv: don't set vertex_attribute_strides on GFX8+ +- radv/ci: skip some mesh shader tests on GFX1100 +- aco: summarize register demand after handling branches +- aco: don't create sendmsg(dealloc_vgprs) if scratch is used +- radv: disable 64-bit color attachments +- radv: fix 128bpp comp-to-single clears +- radv: support 128bpp comp-to-single with all colors +- radv/gfx11: re-enable 0001/1110 clear values +- nir/lower_shader_calls: fix align_offset +- nir/opt_load_store_vectorize: support scratch access +- radv: vectorize RT stack access +- radv: vectorize scratch access +- aco: fix p_bpermute_gfx6 with input at non-zero byte +- aco: fix p_bpermute_gfx6's exec save/restore with wave32 +- aco: clarify bpermute pseudo opcode names +- aco: add adjust_bpermute_dst helper +- aco/spill: skip p_branch in process_block +- aco/spill: add all live-in to merge block spill candidates +- nir/lower_system_values change num_workgroups to uint32_t +- radv: optimize mesh workgroup ID using ts_mesh_dispatch_dimensions +- radv: use shortcut_1d_workgroup_id +- aco: remove fast path in insert_exec_mask's process_instructions +- aco/optimizer_postRA: check overwritten_subdword in is_overwritten_since() +- aco: check logical_phi_info at p_logical_end when eliminating exec writes +- aco: remove unused p_logical_end check when optimizing branching sequence +- radv: disable mesh dispatch XYZ_DIM when possible +- nir/deref: remove rematerialize_deref_in_block cache +- aco: reset prefetch in the correct block after removing the exit +- aco/waitcnt: replace wait_cnt::\*_cnt with booleans +- aco/waitcnt: add print helpers +- nir/lower_int64: fix find_lsb(0) +- nir/algebraic: optimize u2u32(a >> 32) +- aco/optimizer_postRA: don't combine DPP across exec on GFX8/9 +- aco: don't combine DPP into v_cmpx +- aco: disable zero offset optimization for strict WQM coords +- nir/constant_folding: remove zero texel offset +- aco: remove zero offset optimization +- aco: shrink DPP8_instruction +- aco: add fetch_inactive field to DPP instructions +- nir: add fetch inactive index to quad_swizzle_amd/masked_swizzle_amd +- aco: disable FI for quad/masked swizzle +- aco: fix LdsDirectVMEMHazard WaW with the wrong waitcnt +- aco: only mitigate VcmpxExecWARHazard when necessary +- aco: fix s_setreg hazards +- aco: consider exec_hi in reads_exec() +- aco: resolve all possible hazards at the end of shader parts +- aco/tests: test that hazards are resolved at the end of shader parts +- radv: skip zero-sized memcpy +- ac/nir: fix out-of-bounds access in ac_nir_export_position +- radv: fix signed integer overflow +- Revert "radv: pre-init surface info" +- nir: improve ms_cross_invocation_output_access with local_invocation_id +- aco,nir: add export_row_amd intrinsic +- ac/nir: add row parameter to helpers +- ac/nir: remove dead code +- ac/nir: refactor mesh vertex/primitive export +- ac/nir: implement mesh shader gs_fast_launch=2 +- ac/nir: optimize mesh shader local_invocation_index +- radv: implement mesh shader gs_fast_launch=2 +- ac/nir: add emit_ms_outputs helper +- ac/nir,radv: pass workgroup size to ac_nir_lower_ngg_ms +- ac/nir: implement mesh shader multi-row export +- radv: implement mesh shader multi-row export +- radv: enable mesh shader gs_fast_launch=2 and multi-row export +- nir/serialize: fix signed integer overflow +- nir/lower_shader_calls: skip zero-sized qsort +- util: skip zero-sized SHA1Update +- radv: call lower_array_deref_of_vec before lower_io_arrays_to_elements +- radv: skip radv_remove_varyings for mesh shaders +- radv: disable gs_fast_launch=2 by default +- docs: fix RADV_THREAD_TRACE_CACHE_COUNTERS default +- radv: add radv_disable_trunc_coord option +- radv: enable radv_disable_trunc_coord for vkd3d-proton/DXVK +- ac/nir: fix partial mesh shader output writes on GFX11 + +Rob Clark (60): + +- freedreno: move virtgpu msm_proto.h to common +- freedreno/drm/virtio: Remove unused header +- tu/msm: staticify a couple things +- tu/knl: Remove some random const'ness +- drm-uapi: Update virtgpu header +- freedreno: Update virtgpu proto +- freedreno/drm/virtio: Use global_faults +- tu: close submitqueues before device_finish() +- tu/drm: Factor out shared helpers +- tu/drm: Add missing error path cleanup +- tu/drm: Split out helper for iova alloc +- tu: Add virtgpu support +- util: Decouple disk cache from EGL_ANDROID_blob_cache +- docs: Followup to !24636 +- tu: Workaround bionic _SC_LEVEL1_DCACHE_LINESIZE +- ir3+tu: Simplify ir3_find_sysval_regid callers +- freedreno/a6xx: Drop unused screen args +- freedreno/a6xx: Re-work fd6_emit_shader +- freedreno/a6xx: Re-write the function-of-doom +- freedreno: Implement ATI_meminfo +- freedreno/a6xx: ARB_post_depth_coverage +- freedreno/a6xx: ARB_sample_locations +- freedreno/a6xx: ARB_texture_filter_minmax +- freedreno/a6xx: EXT_demote_to_helper_invocation +- freedreno/a6xx: EXT_shader_image_load_formatted +- freedreno/a6xx: EXT_depth_bounds_test +- freedreno/a6xx: Use pipe_blit_info::sample0_only +- freedreno/a6xx: Handle PIPE_BIND_BLENDABLE +- freedreno/a6xx: ARB_shader_viewport_layer_array +- tu: Fix heap size +- freedreno: Fix crash with debug msgs enabled +- freedreno/layout: Handle 565/etc MSAA special case +- freedreno/decode: Fix printing chip-id +- freedreno/a6xx: Add L8_SRGB +- freedreno: Add reformatting commits to .git-blame-ignore-revs +- freedreno/fence: Hold a strong ref to batch +- freedreno/decode: Lookup device info +- freedreno/decode: Use info->chip to decode +- freedreno/decode: Remove gpu_id +- freedreno: Indentation fix +- freedreno: Use explicit QCOM_TILED3 modifier +- freedreno/a6xx: Remove dummy packet for globals +- freedreno: Fix streamout offset_buf dirtiness +- freedreno: Fix user const buffer dirtiness +- freedreno/batch: Move query_buf allocation +- freedreno: Add private-BO tracking +- freedreno: Add missing indirect_draw_count tracking +- freedreno: Move/add some attach_bo() +- freedreno: Add attach-bo debugging +- freedreno: Rework supported-modifiers handling +- mesa: Introduce MESA_texture_const_bandwidth +- mesa: Implement MESA_texture_const_bandwidth +- freedreno: Add PIPE_CAP_HAS_CONST_BW support +- panfrost: Add PIPE_CAP_HAS_CONST_BW support +- iris: Add PIPE_CAP_HAS_CONST_BW support +- radeonsi: Add PIPE_CAP_HAS_CONST_BW support +- tu/msm: Fix timeline semaphore support +- tu/virtio: Fix timeline semaphore support +- freedreno/drm: Fix race in zombie import +- freedreno: Always attach bo to submit + +Robert Foss (9): + +- egl: Expose access to DeviceList +- egl: Rename _eglRefreshDeviceList() to _eglDeviceRefreshList() +- egl: Refresh DeviceList during eglInitialize() +- egl/surfaceless: Use EGL DeviceList instead of drmGetDevices2() +- egl/android: Use EGL DeviceList instead drmGetDevices2() +- egl: Rename _eglAddDevice() to _eglFindDevice() +- egl: Rename _eglAddDevice() to _eglFindDevice() +- egl: Fix attrib_list[0] == EGL_NONE check +- egl: Always set _EGLDisplay->Device during eglGetPlatformDisplay() + +Robert Mader (6): + +- egl/wayland: wait for compositor to release shm buffers +- iris: Support parameter queries for main planes +- util: Add new helpers for pipe resources +- panfrost: Support parameter queries for main planes +- vc4/resource: Support offset query for multi-planar planes +- v3d/resource: Support offset query for multi-planar planes + +Rohan Garg (33): + +- iris: migrate WA 14013910100 to use the WA framework +- iris: migrate WA 14016118574 to use the WA framework +- iris: fix iris for WA 16013000631 +- intel/perf: add perf query support for Intel Raptorlake +- intel/genxml: set a default value for "Pixel Position Offset Enable" in genxml +- anv: use the WA infrastructure where possible when generating state +- anv: use the correct GFX_VERx10 macro for WA +- anv,iris: program the maximum number of threads on compute queue init +- anv: drop CFE state validation checks +- iris: track reset signalling instead of replacing the context +- iris: allow for a unsynchronized device reset query +- anv: partially revert 2e8b1f6d +- anv: emitting 3DSTATE_PRIMITIVE_REPLICATION is required on Gen12+ +- anv: use the pre defined _3DPRIMITIVE_DIRECT macro +- anv: drop dead ifdef +- iris: use the correct WA macros and lineage numbers +- anv: use the lineage number for WA +- crocus: add a __gen_get_batch_address declaration +- crocus: fix GFX_VERx10 macro +- blorp: drop undefined macro +- iris: migrate preemption streamwout wa to WA infra +- intel/genxml: update PIPE_CONTROL instruction for dg2 +- anv: define clear color localy within can_fast_clear_color_att +- intel/compiler: Adjust CS payload registers for new register width on Xe2+ +- intel/compiler: Adjust fence message lengths for new register width on Xe2+ +- intel/compiler: Adjust barrier emission for Xe2+ +- intel/genxml: fix 3DSTATE_3D_MODE length to align with BSpec +- anv: ensure that FCV_CCS_E fast clears are properly tracked +- anv: enable FCV for Gen12.5 +- anv: fix debug string for PC flush +- anv: cleanup includes +- anv: turn off non zero fast clears for CCS_E +- anv: selectively enable FCV optimization for DG2 + +Roland Scheidegger (1): + +- lavapipe: further limit accurate_a0 hack + +Roman Stratiienko (22): + +- egl: android: Remove legacy name-based shared buffers support +- util: Add NONNULL macro +- android: Introduce the Android buffer info abstraction +- android: Fix num_planes assignment in u_gralloc_fallback +- v3dv/android: Use u_gralloc code +- v3dv/android: Enable shared presentable image support +- v3dv: Migrate to vk_device_memory +- v3dv/android: Skip swapchain binding +- v3dv: Rely on the internal tiled flag instead of the common vk structure +- v3dv/android: Add a helper function to support explicit layouts +- v3dv/android: Rework Android native buffer importing logic +- v3dv: Use format stored in vk_image and vk_image_view after init +- v3dv: Split v3dv_image_init to use layout setting logic separately +- v3dv/android: Add AHardwareBuffer support +- v3dv: Enable VK API v1.2 for Android +- panvk: Add Android ICD loader entry point +- u_gralloc: Remove inline modifiers from the functions +- u_gralloc: Remove usage of NONNULL macro +- Revert "util: Add NONNULL macro" +- u_gralloc: Add a function that returns gralloc type +- dri: Remove __driDriverExtensions leftovers +- v3d: Don't implicitly clear the content of the imported buffer + +Ruijing Dong (2): + +- frontends/va: checking va version for av1enc support +- radeonsi/vcn: change max_poc to fixed value for hevc encoder. + +Ryan Neph (1): + +- vulkan/android: add missed STACK_ARRAY_FINISH() + +Sagar Ghuge (34): + +- intel/compiler: Look at 2 register worth of data instead of 4 +- isl: Disable MCS compression just on ACM platform +- intel: Add env variable to add break point on/before draw +- anv: Add GPU breakpoint before/after specific draw call +- iris: Add GPU breakpoint before/after draw call +- blorp: Implement blorp hooks to emit breakpoint +- docs: Add INTEL_DEBUG_BKP_BEFORE/AFTER_DRAW_COUNT +- intel/isl: Enable INTEL_DEBUG=noccs/nohiz in ISL helpers +- anv,hasvk: drop unnecessary DEBUG_NO_CCS/NO_HIZ checks +- iris,crocus: drop unnecessary DEBUG_NO_CCS/NO_HIZ checks +- blorp: Drop unnecessary assertions in blorp_can_hiz_clear_depth +- anv: Add helper to create companion RCS command buffer +- anv: Split out End/Destroy/Reset cmd buffer code into helper +- anv: Handle companion RCS in end/destory/reset code path +- intel: Add helper to create/destroy i915 VM +- intel: Pass virtual memory address space ID while creating context +- anv: Create companion RCS engine +- anv: Move compute specfic bits under compute queue init +- anv: Execute RCS init batch on companion RCS context/engine +- anv: Setup companion RCS command buffer submission +- anv: Execute an empty batch to sync main and companion RCS batch +- anv: Add secondary companion RCS cmd buffer to primary +- anv: Skip layout transition on the compute queue +- anv: Extract batch print code to anv_print_batch helper +- iris: Enable always flush cache with DEBUG_STALL option +- intel/genxml: Add STATE_COMPUTE_MODE instruction +- anv: Program and emit STATE_COMPUTE_MODE +- anv: Enable barrier handling on video engines +- isl: Use 16-bit instead of 8-bits for surface format info fields +- anv: Handle end of pipe with MI_FLUSH_DW on transfer queue +- anv: Enable transfer queue only on ACM+ platforms +- blorp: Use the correct miptail start LOD for surfaces +- anv: Write timestamp using MI_FLUSH_DW on blitter +- anv: Flush data cache while clearing depth using HIZ_CCS_WT + +Saleemkhan Jamadar (1): + +- radeonsi/vcn: set jpeg reg version for gfx 1150 + +Samuel Holland (3): + +- Android.mk: Allow building only Vulkan drivers +- Android.mk: Explicitly enable/disable LLVM support +- Android.mk: Only link LLVM for radeonsi, not amd_vk + +Samuel Pitoiset (299): + +- radv: remove support for VK_INDIRECT_COMMANDS_TOKEN_TYPE_STATE_FLAGS_NV +- radv: make radv_get_pa_su_sc_mode_cntl() static +- zink/ci: update list of expected failures for NAVI10 +- radv: stop using a pipeline for emitting VGT_VERTEX_REUSE_BLOCK_CNTL +- radv: remove unused param in radv_pipeline_emit_vgt_gs_out() +- radv: pass a shaders array for computing ia_multi_vgt_param +- radv: bind the pre-compiled PS epilog to the cmdbuf state +- radv: stop using an array of binaries when compiling a compute shader +- radv: add radv_compile_cs() to compile a compute shader +- radv: remove the pipeline dependency for creating a GS copy shader +- radv: add a helper to compute the ESGS itemsize +- radv: use the number of GS linked inputs to compute the ESGS itemsize +- radv: determine ES info for VS/TES with GS earlier +- radv: determine as_ls earlier by using the next stage +- radv: simplify getting next VS stage for VS prologs +- radv: use next_stage for determining the stage to lower NGG +- radv/amdgpu: fix dumping CS with the chained IBs path +- radv/amdgpu: rename old_ib to ib in radv_amdgpu_winsys_cs_dump() +- radv: pass submit info to radv_check_gpu_hangs() +- radv: initialize stage/next_stage earlier +- radv: set next_stage to MESA_SHADER_NONE if there is no FS +- radv: rework considering force VRS without relying on graphics pipeline +- radv: stop passing radv_graphics_pipeline to radv_fill_shader_info() +- radv: move removing all varyings when the FS is a noop +- radv: rename graphics pipeline linking helpers +- radv: simplify lowering NGG GS intrinsics +- radv: rework determining the NGG stage without a graphics pipeline +- radv: cleanup pipeline compute emit helpers +- radv: rename radv_pipeline_stage to radv_shader_stage +- radv: rename NGG query state to be more generic +- radv: declare the shader query user SGPR for emulating GS counters +- radv: enable pipelinestat query emulation for legacy GS +- radv: simplify the NGG vs legacy pipelinestat query path +- radv: rename RADV_SHADER_QUERY_PIPELINE_STAT_OFFSET +- radv: implement nir_intrinsic_atomic_add_gs_invocation_count_amd +- radv: emulate GEOMETRY_SHADER_INVOCATIONS query on RDNA1-2 +- radv: track whether inputs/outputs are linked per shader stage +- radv: add support for VS/TES as ES without shaders IO linking +- radv: use next_stage to determine if the layer should be exported +- radv: use next stage to determine if primID/clip dist should be exported +- radv: compute the legacy GS info earlier +- radv: stop copying some NIR info fields from TES to TCS +- radv: stop lowering patch vertices for TES +- radv: do not always copy the number of tess patches to TES +- radv: initialize tcs.tes_{patch}_inputs_read to a default value +- radv: prevent linking TCS<->TES when TES is NULL +- radv: use a packed user SGPR for the TES state +- radv: stop checking if patch control points is dynamic everywhere +- radv: copy the number of TCS vertices out to TES shader info +- radv: add support for dynamic TCS vertices out for TES +- radv: remove radv_shader_info::tes::num_linked_patch_inputs +- amd,radeonsi: move si_shader_io_get_unique_index_patch() to common code +- radv: allow to use fixed IO locations for VS<->TCS<->TES without linking +- aco: add aco_shader_info::tcs::has_epilog +- aco: add infra for compiling TCS epilogs +- radv,aco: move has_epilog to radv_shader_info +- radv: assume a TCS needs an epilog unless it's linked with a TES +- radv: do not write tess factors in main TCS when it has an epilog +- radv: track if TES reads tess factors differently +- radv: declare new argument for the TCS epilog PC +- radv: add radv_tcs_epilog_key +- radv: add infra for creating TCS epilogs +- radv: add support for a TCS epilogs cache in the device +- radv: add support for emitting TCS epilogs in cmdbuf +- radv: remove unnecessary check in radv_pipeline_nir_to_asm() +- radv: stop passing a graphics pipeline to radv_pipeline_nir_to_asm() +- radv: inline radv_pipeline_get_nir() in radv_graphics_pipeline_compile() +- radv: add a struct for the retained shaders and GPL +- radv: add radv_graphics_shaders_compile() to compile graphics shaders +- radv: remove redundant check in radv_cmd_buffer_after_draw() +- radv: track if patch control points is dynamic from the cmdbuf state +- radv: re-emit binning state if the framebuffer is dirty +- radv: track if vertex binding stride is dynamic from the cmdbuf state +- vulkan: bump header register to 1.3.261 +- vulkan/runtime: add common implementation for GetImageSubresourceLayout() +- vulkan/format: add VK_FORMAT_{A8_UNORM,A1B5G5R5_UNORM_PACK16}_KHR +- radv: use the RT prolog scratch size directly for tracing rays +- radv: add a helper to get the maximum number of scratch waves per shader +- radv: update the number of scratch waves for RT prolog at bind time +- radv: update cmdbuf scratch size info when shaders are bound +- vulkan: add init/finish helpers for vk_buffer_view +- radv: use vk_buffer_view +- radv: use vk_sampler +- radv: use common vkCmdBegin/EndQuery wrappers +- radv: use vk_query +- zink: fix setting VkShaderCreateInfoEXT::nextStage +- radv/rt: fix capture/replay support +- vulkan/render_pass: add common vkGetRenderingAreaGranularityKHR() +- radv: implement vkCmdBindIndexBuffer2KHR() +- radv: allow VK_WHOLE_SIZE for pSizes in vkCmdBindVertexBuffers2() +- radv/rmv: remove unused pipeline create flags when logging pipelines +- radv: store pipeline create flags to radv_pipeline::create_flags +- radv: add support for VkPipelineCreateFlags2CreateInfoKHR +- radv: add support for VkBufferUsageFlags2CreateInfoKHR +- radv: allow VK_REMAINING_ARRAY_LAYERS with VkImageSubresourceLayers +- radv: implement radv_Get{Device}ImageSubresourceLayout2KHR() +- radv: advertise VK_KHR_maintenance5 +- radv: remove useless NULL for pipeline layout during shader info pass +- radv: introduce radv_shader_layout for per-stage descriptor layout +- radv: stop passing redundant stage to radv_shader_stage_init() +- radv: re-introduce radv_pipeline_stage_init() +- radv: add support for loading the LSHS vertex stride from a SGPR +- radv: use the number of VS outputs for computing the tessellation info +- vulkan: ignore VkPipelineColorWriteCreateInfoEXT if the state is dynamic +- radv: reduce TCS_OFFCHIP_LAYOUT_NUM_PATCHES to 6-bits +- radv: add missing comment about TCS_OFFCHIP_LAYOUT_LSHS_VERTEX_STRIDE +- radv: fix emitting TCS epilogs for GFX6-9 +- radv: remove radv_cmd_buffer::cached_vertex_formats +- radv: remove unused param from radv_pipeline_init_multisample_state() +- radv: simplify declaring VS specific input SGPRs +- radv: stop copying if VS or TES uses the InvocationID built-in +- Revert "radv/amdgpu: workaround a kernel bug when replacing sparse mappings" +- Revert "radv/amdgpu: skip adding per VM BOs for sparse during CS BO list build" +- radv/amdgpu: allow to execute external IBs on the compute queue +- radv/amdgpu: add support for submitting external IBs with the chained path +- zink/ci: update list of expected failures for NAVI10 +- radv: use the maximum possible workgroup size for TCS epilogs +- radv: stop declaring the scratch offset argument for TCS epilogs +- radv: declare shader arguments for TCS epilogs +- radv: add tcs_out_patch_fits_subgroup to radv_tcs_epilog_key +- aco: fix jumping from main TCS to epilog on GFX9+ +- aco: adjust TCS epilogs for RADV +- aco: allow SGPRs operands with p_jump_to_epilog +- aco: implement create_tcs_jump_to_epilog() +- radv: track the pipeline bind point for indirect commands layout +- radv: prepare radv_get_sequence_size() for DGC compute +- radv: prepare radv_prepare_dgc() for DGC compute +- radv: implement NV_device_generated_commands_compute +- radv: allow DGC on the compute queue +- radv: advertise NV_device_generated_commands_compute +- aco: rework printing shader stages +- radv: fix the per-patch data offset when TES isn't linked with TCS +- radv: stop declaring unused SGPR arguments for PS epilogs +- radv: add radv_shader_info::is_monolithic +- radv: use info->uses_view_index directly when declaring shader arguments +- radv: do not inline push constants for non-monolithic shaders +- radv: force indirect descriptor sets for non-monolithic shaders +- radv: always declare some arguments for non-monolithic VS/TCS shaders +- radv: add a new shader argument for non-monolithic shaders PC +- ac: allow to mark shader arguments as preserved +- radv: preserve shader arguments for non-monolithic VS/TCS on GFX9+ +- aco: disable shared VGPRs for non-monolithic shaders on GFX9+ +- aco: ensure to initialize exec manually for VS as LS on GFX9+ +- aco: add support for compiling VS+TCS separately on GFX9+ +- radv: always declare some arguments for non-monolithic {VS,TES}/GS shaders +- radv: preserve shader arguments for non-monolithic {VS,TES}/GS on GFX9+ +- aco: ensure to initialize exec manually for non-monolithic {VS,TES}/GS on GFX9+ +- aco: add support for compiling {VS,TES}+GS separately on GFX9+ +- radv,aco: remove unused clip/cull distances variables +- radv: rename tcs_shader to tcs in radv_emit_tcs_epilog_state() +- radv: small cleanups in radv_emit_patch_control_points() +- radv: fix emitting TCS epilogs if TES and GS are linked on GFX9+ +- radv: remove the pipeline dependency for emitting VGT_GS_MODE +- aco: fix emitting TCS epilogs end on GFX9+ +- radv: re-order IO slot layout for stages that aren't linked +- amd/ci: update list of failures/flakes for glcts-vangogh-valve +- ci: uprev vkd3d-proton +- ci: uprev Fossilize +- ci: add comment explaining which image tags to update for Fossilize +- radv: preserve shader argument for separate compilation of NGG shaders +- aco: flag blocks with long-jump as export_end for separate compilation +- aco: adjust fix_exports() for VS/TES as NGG and non-monolithic shaders +- aco: allow separate compilation of NGG shaders +- zink/ci: add zink-radv-polaris10-valve +- radv/ci: re-enable vkcts-polaris10-valve +- radv: fix capturing indirect dispatches with SQTT +- radv/ci: re-enable vkd3d-polaris10-valve +- ci: do not fail vkd3d-proton job when the expectations match +- radv/amdgpu: fix executing secondaries without IB2 +- radv/amdgpu: do not copy the original chain link for IBs +- radv: avoid emitting SQTT markers for DGC calls +- radv: add support for DGC with SQTT +- zink/ci: merge GLCTS testing with GLESx for RADV +- zink/ci: merge piglit testing with deqp-runner for RADV +- radv: fix interactions with primitives generated queries and pipeline stats +- radv: skip DGC calls when the indirect sequence count is zero with a predicate +- radv: avoid emitting THREAD_TRACE_MARKER for predicated draws/dispatches +- radv: adjust next stage for VS prologs and merged shaders compiled separately +- radv: adjust emitted prolog regs for merged shaders compiled separately +- radv: do not use pre-compiled prologs when VS is compiled separately +- radv: remove useless PIPELINE_CREATE_2_LIBRARY_BIT check for retained shaders +- radv: fix enabling DGCC +- radv: fix emitting SQTT userdata when CAM is needed +- radv: fix capturing RGP on RDNA3 with more than one Shader Engine +- zink/ci: update list of expected failures for POLARIS10/NAVI10 +- radv: set THREAD_TRACE_TOKEN_MASK.BOP_EVENTS_TOKEN_INCLUDE on GFX10.3+ +- radv: disable unsupported hw shader stages for RGP on GFX11+ +- radv: fix instruction timing on GFX11 +- ac/rgp: use correct API stage string for mesh/task shaders +- radv: set THREAD_TRACE_MARKER_ENABLE for mesh/task draws +- radv: emit relocation for mesh/task shaders +- issue_templates/Bug Report: fix outdated URL for GFXReconstruct +- ac,radv,radeonsi: rework SPM counters configuration and share it +- ac/perfcounter: add new SQ_WGP block for GFX11+ +- ac/spm: add SPM counters configuration for GFX11 +- radv: enable the PKT3 CAM bit for some SPM register writes +- radv,radeonsi: use AC_SPM_SEGMENT_TYPE_xxx instead of magic values +- ac/spm: remove useless SPM block setting for GFX9 and older GPUs +- ac/spm: add SPM block definition for GFX10-GFX10.3 +- ac/gpu_info: init num_cu_per_sh from the kernel +- ac/perfcounter: set the number of instances of GL1C to 4 +- ac/perfcounter: compute the number of global instances of TCP,SQ,GL1C and GL2C +- ac/spm: fix checking if the counter instance is valid +- ac/spm: rework how segment muxsel RAM are filled +- ac/spm: initialize and set instance mapping for counters +- radv: reserve more CS space in SQTT/SPM paths +- ac/spm: use block flags to initialize instance mapping +- ac/spm: select correct segment type for per-SE blocks +- radv,radeonsi: make sure to emit GRBM_GFX_INDEX before SQ select registers +- ac/spm: fix number of instances of GL2C +- ac,radv,radeonsi: prepare support for multi-instance SPM SQ counters +- ac,radv,radeonsi: prepare support for multi-instance SPM generic counters +- ac/spm: move the counter instance to ac_spm_counter_create_info +- ac/spm: enable support for multi-instance counters +- radv: fix checking if RGP is enabled with others tracing tools +- radv: fix missing ISA with RGP and GPL +- ac/perfcounter: add SG_WQP group for GFX11 +- ac/perfcounter: add GFX11 groups +- drirc: remove Path of Exile workarounds +- radv: remove drirc workarounds for Path Of Exile +- radv: remove absolute_depth_bias workaround +- ac/gpu_info: define AMD_MAX_WGP +- ac/spm: add new segment types for GFX11 +- ac/spm: add support for GFX11 +- radv: add SPM support for GFX11 +- radv: enable cache counters for RGP on GFX11 +- ci: update to vulkan-cts-1.3.6.3 +- radv/ci: skip dEQP-VK.robustness.* on Vangogh due to weird GPU hangs +- nir: rename atomic_add_gs_invocation_count_amd to make it more generic +- ac/nir: add lowering for mesh shader queries +- ac/nir: add lowering for task shader queries +- radv: add GDS counters offset for mesh/task queries +- radv: adjust lowering of intrinsic queries for mesh/task shaders +- radv: enable lowering of mesh/task shader queries when enabled +- radv: declare shader_query_state for mesh/task shaders +- radv: stop skip emitting CB states when there is no color attachment +- radv: re-enable DCC with mipmaps on GFX11 +- radv: fix COMPUTE_SHADER_INVOCATIONS query on compute queue +- radv: emit missing PA_{SC,SU}_LINE_STIPPLE_xxx regs in gfx preamble +- radv: fix alignment of DGC command buffers +- radv/ci: update list of expected failures on PITCAIRN +- radv/ci: update list of flakes for NAVI10/VEGA10 +- radv/amdgpu: fix alignment of command buffers +- radv: enable DCC for MSAA images on GFX11 +- zink/ci: update list of expectations for zink-anv-tgl +- zink/ci: bump zink-anv-tgl-full timeout to 1h45m +- radv/ci: rename GFX1100 lists to NAVI31 +- radv: fix emulated geometry shader primitives/invocations queries +- radv/ci: remove duplicate skipped tests for RAVEN/STONEY +- radv/ci: exclude dEQP-VK.texture.explicit_lod.2d.sizes.128x128_* for all jobs +- radv: fix synchronization with emulated GS primitives/invocations queries +- radv/ci: remove no longer existing test for VANGOGH +- radv/ci: cleanup list of expected failures for NAVI10/NAVI21/VEGA10 +- radv: always write the sample positions when a new descriptor BO is created +- radv: fill the scratch BO in radv_fill_shader_rings() +- radv: fix gang submissions with chaining +- radv: fix re-emitting streamout descriptors for NGG streamout +- radv: fix IB alignment +- zink: use warn_missing_feature for missing modifier support +- radv: fix destroying GDS/OA BOs +- radv: allocate only 1 GDS OA counter for gfx10 NGG streamout +- ac/nir: only consider overflow for valid feedback buffers +- radv/ci: update list of expected failures on RAVEN +- radv/ci: update list of flakes for VANGOGH +- radv/ci: update list of flakes for STONEY +- radv: disable primitive restart for non-indexed draws on GFX11 +- radv: enable radv_disable_aniso_single_level=true for Zink too +- amd/llvm,aco,radv: implement NGG streamout with GDS_STRMOUT registers on GFX11 +- radv: mark GDS as needed for XFB queries with NGG streamout on GFX11 +- radv: skip GDS allocation for NGG streamout on GFX11 +- zink/ci: remove expected failures that are skipped for RADV +- ci: update CTS to vulkan-cts-1.3.7.0 +- ci: bump the number of tests per group from 500 to 5000 for Vulkan drivers +- ci: bump DEQP_FRACTION for some jobs +- radv: set ENABLE_PING_PONG_BIN_ORDER for GFX11.5 +- radv: initialize video decoder for GFX11.5 +- ac/gpu_info: query the maximum number of IBs per submit from the kernel +- Revert "radv: fix finding shaders by PC" +- radv: fix missing predicate bit for WRITE_DATA helper +- ac/gpu_info: fix querying the maximum number of IBs per ring +- radv: remove outdated RADV_DEBUG=vmfaults support +- amd: update amdgpu_drm.h +- amd: add has_gpuvm_fault_query +- radv/amdgpu: add support quering the last GPUVM fault +- radv: query and report the last GPUVM fault with RADV_DEBUG=hang +- radv: report the last GPUVM fault when a device lost is detected +- ac/gpu_info: remove bogus assertion about number of COMPUTE/SDMA queues +- radv: fix a synchronization issue with primitives generated query on RDNA1-2 +- radv: bind the non-dynamic graphics state from the pipeline unconditionally +- radv: fix compute shader invocations query on compute queue on GFX6 +- radv: emit COMPUTE_PIPELINESTAT_ENABLE for CS invocations on ACE +- nir: fix inserting the break instruction for partial loop unrolling +- radv: fix registering queues for RGP with compute only +- radv: set radv_zero_vram=true for Unreal Engine 4/5 +- radv: fix a descriptor leak with debug names and host base descriptor set +- radv: add a missing async compute workaround for Tonga/Iceland +- radv: disable TC-compatible HTILE on Tonga and Iceland +- radv: set radv_invariant_geom=true for War Thunder +- radv: do not set OREO_MODE to fix rare corruption on GFX11 + +Saroj Kumar (4): + +- radeonsi: Add perfetto support in radeonsi +- radeonsi: Add u_trace init code in radeonsi +- radeonsi: Add tracepoints in radeonsi driver +- radeonsi: fixes compilaton error when perfetto is disabled + +Sathishkumar S (2): + +- radeonsi/vcn: support variable number of bs_bufs +- radeonsi/vcn: num bs_bufs must be proportional to num jpeg engines + +Semjon Kravtsenko (1): + +- glx: Assign unique serial number to GLXBadFBConfig error + +Seppo Yli-Olli (1): + +- zink: Fix SyntaxWarning in zink_extensions script + +Sergi Blanch Torne (7): + +- Introduce ci-kdl builder and launcher. +- Integrate ci-kdl in the building process and launch process. +- ci: disable Collabora's LAVA lab for maintance +- Revert "ci: disable Collabora's LAVA lab for maintance" +- Revert "ci: disable Collabora's LAVA lab for maintance" +- ci: disable Collabora's LAVA lab for maintance +- Revert "ci: disable Collabora's LAVA lab for maintance" + +Sid Pranjale (1): + +- nvk: Enable VK_EXT_load_store_op_none + +Sil Vilerino (20): + +- util: Blake3 - Identify arm64ec as aarch64 instead of x64 +- d3d12: Fix Map/Unmap of YUV resources +- d3d12: Fix H264 interlaced decode +- d3d12: Video Decode - Remove unnecessary copy for texture array case +- util/vl_vlc: Use UINT64_MAX instead of ~0UL with MSVC compiler +- d3d12: Extend video screen AV1 encode tile support checking +- aux/tc: Add ASSERTED to unreferenced release build variable +- d3d12: Video - Relax ID3D12VideoDevice QI version for decode, process +- frontends/va: Add profile param when querying PIPE_VIDEO_CAP_ENC_QUALITY_LEVEL +- d3d12: Upgrade to D3D12 Agility SDK 1.611 Video interface +- d3d12: Fixes AV1 tx_mode_support reporting and unsupported tx_mode overriding +- d3d12: Video Decode - Wait for GPU completion before destroying decoder in-flight objects +- d3d12: Do not destroy codec when destroying video buffer +- d3d12: AV1 encode - Add lower resolution fallback check for uniform tile support +- d3d12: AV1 encode - add fallback for app passing unsupported pic_params.InterpolationFilter +- d3d12: AV1 Encode - Fix VAConfigAttribEncMaxRefFrames reporting +- frontend/va: Add support for VAConfigAttribEncMaxTileRows/Cols +- d3d12: Add support for PIPE_VIDEO_CAP_ENC_MAX_TILE_ROWS/COLS +- d3d12: Allocate d3d12_video_buffer with higher alignment for compatibility +- d3d12: d3d12_video_buffer_create_impl - Fix resource importing + +Simon Ser (7): + +- wayland: enable use of wayland-protocols as a subproject +- vulkan/wsi/wayland: add support for IMMEDIATE +- vulkan/wsi/wayland: fix unset present_mode +- radv/winsys: check amdgpu_create_bo_from_user_mem() for EINVAL +- egl: extract EGLDevice setup in dedicated function +- egl: move dri2_setup_device() after dri2_setup_extensions() +- egl: ensure a render node is passed to _eglFindDevice() + +Simon Zeni (1): + +- nouveau/winsys: use mmap instead of mmap64 in nouveau_bo + +SoroushIMG (1): + +- pvr: fix mipmap size calculation for bc formats + +Sviatoslav Peleshko (9): + +- dri: Use RGB internal formats for RGBX formats +- intel/isl: Don't over-allocate CLEAR_COLOR size to use whole cache line +- anv: Do fast clear color initialization more delicately +- zink: Change zink_vertex_elements_hw_state::b.strides to VkDeviceSize +- intel/fs: Check if the whole ubo load range is in the push const range +- zink: Store zink_vertex_elements_hw_state::b.strides by binding id +- intel/fs: Fix "packed word exception" condition for register regioning +- intel/eu/validate: Validate "packed word exception" stricter +- nir/loop_analyze: Fix inverted condition handling in iterations calculation + +Sylvain Munaut (9): + +- egl/dri2: Add a couple of missing mutex release in error path +- mesa: Enable ARB_texture_border_clamp in GL Core +- include: Fix the PFN declarations to be pointers as they should +- glx: Add missing MesaGLInteropGLXFlushObjects +- glx: Export the MESA GL Interop functions through glXGetProcAddress +- egl: Export the MESA GL Interop functions through eglGetProcAddress +- glx: Remove MESA_depth_float_bit from enum +- glx: Advertise GLX_MESA_gl_interop extension if support present +- egl: Advertise EGL_MESA_gl_interop extension if support present + +Tapani Pälli (34): + +- intel/blorp: add a new flag to communicate PSS sync need +- anv: implement required PSS sync for Wa_18019816803 +- iris: implement required PSS sync for Wa_18019816803 +- vulkan/runtime: change assert to match specification needs +- anv: remove assert, size is asserted in the runtime +- anv: refactor batch_set_preemption to use batch_emit_pipe_control +- anv: implement a dummy depth flush for Wa_14016712196 +- iris: implement a dummy depth flush for Wa_14016712196 +- mesa: fix some TexParameter and SamplerParameter cases +- mesa: remove GL_UNSIGNED_BYTE as supported for snorm reads +- ci: add a fix for KHR-GLES3.packed_pixels.*snorm tests +- anv: implement Wa_14018912822 +- iris: implement Wa_14018912822 +- driconf: use lower_depth_range_rate for The Spirit and The Mouse +- mesa: disable snorm readpix clamping with EXT_render_snorm +- iris: modify Wa_14014414195 to use intel_needs_workaround +- mesa: some cleanups for texparam extension checks +- iris: avoid issues with undefined clip distance +- crocus: avoid issues with undefined clip distance +- anv: refactor to fix pipe control debugging +- anv: fix a leak of fp64_nir shader +- iris: use intel_needs_workaround for Wa_14014414195 part 2 +- iris: correct dst alpha blend factor in Wa_14018912822 +- iris/anv: move Wa_14018912822 as a drirc workaround +- iris: flush data cache when flushing HDC on GFX < 12 +- anv: HDC flush is available only for GFX_VER 12+ +- iris: HDC flush is available only for GFX_VER 12+ +- intel/genxml: remove HDC from gen11.xml, it is not available +- mesa/st: ignore StencilSampling if stencil not part of the format +- intel/dev: expand existing fix for all gfx12 with small EU count +- egl: fix leaking drmDevicePtr in _eglFindDevice +- iris: add data cache flush for pre hiz op +- anv/drirc: add option to disable FCV optimization +- drirc: Set limit_trig_input_range option for Valheim + +Tatsuyuki Ishi (8): + +- radv/amdgpu: Remove unused bo_list variable from cs_submit. +- radv/winsys: Remove unused struct radv_winsys_bo_list. +- radv/amdgpu: Do not pass in a BO handle when clearing PRT VA region. +- radv: Fix IB size for RADV_DEBUG=hang. +- radv: Fix dumping vertex descriptors with RADV_DEBUG=hang. +- radv/amdgpu: Use rwlock to protect access to virtual BOs. +- zink: Fix missing sparse buffer bind synchronization. +- zink: Fix waiting for texture commit semaphores. + +Thomas H.P. Andersen (65): + +- tgsi: remove unused tgsi_shader_info.num_tokens +- tgsi: remove unused tgsi_shader_info.array_max +- tgsi: remove unused tgsi_shader_info.num_memory_instructions +- tgsi: remove unused tgsi_shader_info.colors_read +- tgsi: remove unused tgsi_shader_info.colors_written +- tgsi: remove unused tgsi_shader_info.reads_position +- tgsi: remove unused tgsi_shader_info.reads_samplemask +- svga: remove unused struct field +- tgsi: remove unused tgsi_shader_info.reads_tess_factors +- tgsi: remove unused tgsi_shader_info fields +- tgsi: remove unused tgsi_shader_info fields +- tgsi: remove unused tgsi_shader_info.uses_drawid +- tgsi: remove unused tgsi_shader_info fields +- tgsi: remove unused tgsi_shader_info.uses_subgroup_info +- tgsi: remove unused tgsi_shader_info.writes_primid +- tgsi: remove unused tgsi_shader_info.uses_doubles +- tgsi: remove unused tgsi_shader_info.uses_derivatives +- tgsi: remove unused tgsi_shader_info.uses_bindless_samplers +- tgsi: remove unused tgsi_shader_info.uses_bindless_images +- tgsi: remove unused tgsi_shader_info.clipdist_writemask +- tgsi: remove unused tgsi_shader_info.culldist_writemask +- tgsi: remove unused tgsi_shader_info.images_load +- tgsi: remove unused tgsi_shader_info.images_store +- tgsi: remove unused tgsi_shader_info.images_atomic +- tgsi: remove unused tgsi_shader_info.uses_bindless_buffer_load +- tgsi: remove unused tgsi_shader_info.uses_bindless_buffer_store +- tgsi: remove unused tgsi_shader_info.uses_bindless_buffer_atomic +- tgsi: remove unused tgsi_shader_info.uses_bindless_image_load +- tgsi: remove unused tgsi_shader_info.uses_bindless_image_store +- tgsi: remove unused tgsi_shader_info.uses_bindless_image_atomic +- tgsi: remove unused tgsi_shader_info.indirect_files_read +- tgsi: remove unused tgsi_shader_info.indirect_files_written +- tgsi: remove unused tgsi_shader_info.const_buffers_indirect +- tgsi: remove unused tgsi_shader_info.max_depth +- tgsi: drop two unused functions +- nvk: use common physical device enumeration +- nvk: fix implicit-fallthrough warnings with clang +- nvk: delete commented code +- nvk: fix mem leaks +- nvk: use common descriptor set layout code +- nvk: use common pipeline layout code +- nvk: advertise KHR_shader_non_semantic_info +- nvk: advertise KHR_image_format_list +- nvk: advertise EXT_private_data +- nvk: advertise KHR_sampler_mirror_clamp_to_edge +- nvk: KHR_descriptor_update_template +- nvk: CmdPushDescriptorSetWithTemplateKHR +- nvk: drop dead assignment +- nvk: drop dead assignment +- nvk: fix initialization override +- nvk: sort extensions +- nvk: advertize KHR_relaxed_block_layout +- nvk: add check for VK_IMAGE_CREATE_2D_VIEW_COMPATIBLE_BIT_EXT +- nvk: advertise EXT_image_2d_view_of_3d +- nvk: fix maxPushDescriptors +- nvk: call correct macro to clear views +- nouveau/mme: use fermi enum in fermi builder +- nvk: add warning on non-nouveau drm driver +- nvk: Implement VK_KHR_draw_indirect_count on Turing+ +- nvk: set device info before use in nvk_get_device_extensions +- nvk: simplify code by using new helpers +- nvk: remove duplicated device features +- nvk: EXT_conditional_rendering +- nvk: advertise VK_EXT_tooling_info +- nvk: set optimization level to 3 + +Thong Thai (3): + +- radeonsi: enable vcn encoder rgb input support +- Update radeon_vcn_enc.c +- frontends/va/config: report max width and height for encoding/decoding + +Timothy Arceri (27): + +- glsl: fix validation of ES vertex attribs +- nir/opt_copy_prop_vars: don't clone copies if branch empty +- nir/opt_copy_prop_vars: speedup cloning of copy tables +- nir/opt_copy_prop_vars: remove var hash entry on kill alias +- nir/opt_copy_prop_vars: skip cloning of copies arrays until needed +- nir/opt_copy_prop_vars: drop reuse of dynamic arrays +- glsl: fix spirv sso validation +- glsl: mark structs containing images as bindless +- util: add radeonsi workaround for Nowhere Patrol +- glsl: fix out params in glsl to nir +- glsl_to_nir: add more unhandled function types +- nir: replace use of nir_src_copy() +- nir: remove unused nir_src_copy() +- nir: remove unused param from nir_alu_src_copy() +- glsl: remove field from gl_shader_program +- glsl: move get_varying_type() declaration earlier +- glsl: add nir version of validate_first_and_last_interface_explicit_locations() +- glsl: switch to nir validate_first_and_last_interface_explicit_locations() +- glsl: remove unused validate_first_and_last_interface_explicit_locations() +- nir: fix typo in comment +- nir: copy explicit_invariant flag to nir vars +- glsl: move interpolation_string() to linker_util +- glsl: move is_gl_identifier() to linker_util +- nir: add used field to nir variables +- glsl: implement cross_validate_outputs_to_inputs() in nir linker +- glsl: switch to nir linkers cross_validate_outputs_to_inputs() +- glsl: remove now unused varying linker code + +Timur Kristóf (39): + +- aco: Fix subgroup_id intrinsic on GFX10.3+. +- ac/nir: Simplify arg unpacking when shift is zero. +- ac/nir: Add new pass to lower intrinsics to shader args. +- radv: Move radv_select_hw_stage to radv_shader_info. +- radv: Use ac_nir_lower_intrinsics_to_args. +- radeonsi: Move si_select_hw_stage to si_shader_info. +- radeonsi: Use ac_nir_lower_intrinsics_to_args. +- aco: Remove subgroup_id and num_subgroups intrinsics. +- ac/llvm: Remove subgroup_id and num_subgroups intrinsics. +- aco: Refactor select_program to smaller functions. +- nir/opt_dead_cf: Remove if branches with undef condition. +- ac/nir: Add done arg to ac_nir_export_position. +- ac/nir: Slightly refactor how pos0 exports are added when missing. +- ac/nir/ngg: Wait for attribute stores before VS/TES/GS pos0 export. +- ac/nir/ngg: Refactor mesh shader primitive export. +- ac/nir/ngg: Wait for attribute ring stores in mesh shaders. +- ac/nir/ngg: Extract nogs_export_vertex_params function. +- ac/gpu_info: Add some SDMA related information. +- ac: Clarify SDMA opcode defines. +- ac: Add amd_ip_type argument to ac_parse_ib and ac_parse_ib_chunk. +- ac: Rename ac_do_parse_ib to parse_pkt3_ib. +- ac: Print IP type for IBs. +- ac: Add rudimentary implementation of printing SDMA IBs. +- radv: Rename SDMA file to radv_sdma.c +- radv: Use const device argument in radv_sdma_copy_buffer. +- radv: Use const on vi_alpha_is_on_msb arguments. +- radv: Only call si_cp_dma_wait_for_idle on GFX and ACE queues. +- radv: Move radv_cp_wait_mem to radv_cs.h and add queue family argument. +- radv: Refactor WRITE_DATA helper function. +- radv: Use new WRITE_DATA helper in more places. +- radv: Add queue family argument to some functions. +- radv: Wait for bottom of pipe in ACE gang wait postamble. +- radv: Simplify gang CS and semaphore initialization. +- radv: Allow gang submit use cases other than task shaders. +- radv: Slightly refactor gang semaphore functions. +- radv: Add gang follower semaphore functions. +- radv: Support SDMA in radv_cs_write_data_head. +- radv: Support SDMA in radv_cp_wait_mem. +- radv: Support SDMA in si_cs_emit_write_event_eop. + +Vignesh Raman (4): + +- ci: add Vignesh Raman into restricted traces access list +- Do explicit cast to suppress clang warnings +- ci: enforce -Wimplicit-const-int-float-conversion for clang +- ci: Uprev crosvm + +Vinson Lee (8): + +- nvk: Fix assert +- lavapipe: Fix struct initialization +- intel/decoder: Fix memory leak on error path +- nv50: Remove unused value +- vk/wsi/x11: Remove dead code +- freedreno/replay: Fix implicit-function-declaration error +- anv: Fix transfer type assert +- broadcom/qpu: Remove duplicate variable opcode + +Vitaliy Triang3l Kuzmin (3): + +- r600/asm: Fix AR force_add_cf setting if a clause is not open +- r600/asm: Make sure MOVA and SET_CF_IDX are in the same clause +- r600: Replace R600_BIG_ENDIAN with UTIL_ARCH_BIG_ENDIAN + +Vlad Schiller (15): + +- pvr: Implement VK_EXT_tooling_info +- pvr: Add 'info' PVR_DEBUG flag +- pvr: Implement VK_KHR_format_feature_flags2 +- pvr: Remove PVR_WINSYS_BO_FLAG_ZERO_ON_ALLOC flag +- pvr: Add VK_KHR_driver_properties +- pvr: Use correct index when writing query availability data +- pvr: Enable VK_EXT_scalar_block_layout +- pvr: Enable KHR_image_format_list +- pvr: Enable VK_KHR_uniform_buffer_standard_layout +- pvr: Implement VK_KHR_external_fence +- pvr: Implement VK_KHR_external_semaphore +- pvr: Enable VK_KHR_bind_memory2 extension +- pvr: Implement VK_EXT_texel_buffer_alignment +- pvr: Implement VK_EXT_host_query_reset +- pvr: Fix VK_EXT_texel_buffer_alignment + +WinLinux1028 (1): + +- radeonsi: prefix function with si\_ to prevent name collision + +Xaver Hugl (1): + +- vulkan wsi: add support for PresentOptionAsyncMayTear + +Yiwei Zhang (46): + +- venus: handle query feedback creation failure +- venus: ensure consistency of query overflow behavior +- venus: add a missing barrier before copying query feedback +- venus: refactor query feedback cmd record +- venus: reduce to use 4K mem suballoc align on platforms known to fit +- turnip: flush cache for dstBuffer in vkCmdCopyQueryPoolResults +- lvp: avoid reading immutable sampler from desc write info +- ci/venus: update venus-lavapipe expectations +- venus: fix a cmd builder render_pass state leak across reset +- venus: fix cmd state leak across implicit reset +- venus: log and doc the broken query feedback in suspended render pass +- venus: move transient storage from cmd to pool +- venus: remove redundant fb tracking from cmd builder +- venus: use tracked queue_family_index from the cmd pool +- venus: cleanup vn_cmd_begin_render_pass usage +- venus: add helpers to track subpass view mask +- venus: avoid redundant tracking of render pass +- venus: refactor more cmd states into cmd builder +- venus: use in_render_pass to skip present_src counting +- ci/venus: remove fixed tests that no longer run +- ci/venus: reenable pipeline cts +- venus: suppress a false logging +- venus: add no_sparse debug option to disable sparse resource support +- venus: set deviceMemoryReport feature +- venus: expose at least one cached memory type +- venus: expose KHR_external_fence/sempahore_fd extensions +- venus: fix a device memory report leak +- vulkan: remove a dup entry from vk_image_usage_to_ahb_usage +- vulkan/android: improve vkQueueSignalReleaseImageANDROID +- vulkan/android: add missing AHARDWAREBUFFER_USAGE_GPU_DATA_BUFFER usage +- vulkan/android: drop vk_buffer dependency from common AHB impl +- venus: use common vk_queue object +- venus: use common ANB implementation +- venus: use more common vk_queue related implementations +- venus: drop device, family, index, flags tracking from vn_queue +- venus: fix re-export of imported classic 3d resources +- venus: remove redundant bo roundtrip and add more docs +- venus: track VkPhysicalDeviceMemoryProperties instead +- venus: refactor vn_device_memory to prepare for async alloc +- venus: make device memory alloc async +- venus: enable Vulkan 1.3 for Android 13 and above +- zink: sync queue access for vkQueueWaitIdle +- venus: properly expose KHR_external_fence/sempahore_fd +- ci/venus: mark more flaky tests after recent cts uprev +- venus: fix query feedback batch leak and race upon submission +- zink: apply can_do_invalid_linear_modifier to Venus + +Yogesh Mohan Marimuthu (12): + +- gallium: remove start_slot parameter from pipe_context::set_vertex_buffers +- ac/surface: add astc block size to bpe_to_format() function +- util: move ASTCLutHolder from mesa/main to util +- vulkan/formats,zink: move vk_format_from_pipe_format() function +- vulkan/runtime: add compute astc decoder helper functions +- vulkan add 3D texture support for compute astc decoder +- radv: integrate meta astc compute decoder to radv +- radeonsi: add more documentation for dpbb debug env variable +- docs: remove document for unused variable dfsm from AMD_DEBUG +- radeonsi: correct old comment in si_emit_framebuffer_state() +- radeonsi: In gfx6_init_gfx_preamble_state() use gfx_level only from sctx +- radeonsi: add radeonsi to GL_RENDERER string + +Yonggang Luo (43): + +- lima: Convert to use nir_foreach_function_impl when possible +- freedreno: Switch to use nir_foreach_function_impl in tu_shader.cc +- zink: Convert to use nir_foreach_function_impl when possible +- lavapipe: Convert to use nir_foreach_function_impl +- lavapipe: fixes indent of function lvp_inline_uniforms +- microsoft/compiler: convert to use nir_foreach_function_with_impl in function emit_module +- microsoft/clc/compiler: Convert to use nir_foreach_function_impl when possible +- radeonsi: Convert to use nir_foreach_function_impl +- ac: Switch to use nir_foreach_function_impl in function analyze_shader_before_culling +- util: Move pipe_swizzle from p_defines.h to u_formats.h +- util: Move PIPE_MASK_* from p_defines.h to u_formats.h +- util: Move pipe_color_union from p_defines.h into u_formats.h +- util: Move u_pack_color.h and dbughelp.h into src/util from/src/gallium/auxiliary/util/ +- util: Remove include "pipe/\*.h" in src/util/* files +- util:Move only gallium used u_debug_refcnt.* and u_debug_describe.* into src/gallium/auxiliary/util/ +- util/meson: Getting mesa util core to be self contained +- pvr: decouple vulkan driver and compiler from gallium +- freedreno: decouple compiler and vulkan driver from gallium +- glx: decouple from gallium +- meson: Remove arm_neon_workaround +- nouveau/drm-shim: Decouple from gallium +- ac/radv: decouple radv vulkan driver and compiler from gallium +- etnaviv: decouple drm from gallium +- asahi: decouple layout from gallium +- compiler: Move WRITEMASK_* from prog_instruction.h into shader_enums.h +- intel/blorp: Use float directly to avoid #include "mesa/main/format_utils.h" +- intel/blorp: brw_sampler_prog_key_data::swizzles is only and should only accessed in crocus +- intel/brw: Define and use BRW_SWIZZLE_* instead of SWIZZLE_* +- crocus: #include "program/prog_instruction.h" for SWIZZLE_* +- intel/compiler,intel/blorp,intel/vulkan: decouple vulkan driver and compiler from gallium +- util/treewide: Use alignas(x) instead __attribute__((aligned(x))) +- v3dv: Use alignas(8) over 64 bit atomic value +- svga: use alignas over struct MKSGuestStatInfoEntry +- radv: Fixes mingw linkage error undefined reference to \`radv_GetCalibratedTimestampsEXT' +- v3d: Use DIV_ROUND_UP instead div_round_up +- freedreno: Use shared DIV_ROUND_UP instead div_round_up +- sfn: Use 4 instead of ATOMIC_COUNTER_SIZE +- intel/brw: use 4 instead of MAX_VERTEX_STREAMS to avoid #include "mesa/main/config.h" +- d3d12: replace use of MAX_VERTEX_STREAMS with PIPE_MAX_VERTEX_STREAMS +- compiler: use 4 instead ATOMIC_COUNTER_SIZE in glsl_types.h to avoid #include "mesa/main/config.h" +- compiler/glsl: Move glsl_print_type from glsl_types.* to ir_print_visitor.cpp +- util: Deduplicate macros between u_math.h and macros.h +- nvk: Should use alignment instead of align + +Yusuf Khan (4): + +- nouveau/ws: remove the drm.h header +- nvk: implement GetDeviceMemoryCommitment +- nvk: support GetImageSparseMemoryRequirements2 +- nvk: expose KHR_driver_properties + +Zhang Ning (1): + +- Revert "intel/ci: disable iris-jsl-deqp because it always fails for an AMD MR" + +antonino (14): + +- virgl: add ci flake +- freedreno: add ci flake +- zink: remove unused indices from \`nir_load_push_constant` calls +- zink/nir: add a zink specific intrinsic for push constants +- vulkan/wsi: add \`vk_wsi_force_swapchain_to_current_extent` driconf +- drirc: enable \`vk_wsi_force_swapchain_to_current_extent` for "The Talos Principle" +- drirc: enable \`vk_wsi_force_swapchain_to_current_extent` for "Serious Sam Fusion" +- vulkan: Extend vkGet/SetPrivateDataEXT handling to all platforms +- vulkan: Extend vkGet/SetPrivateDataEXT handling to VkSurface +- vulkan: Handle vkSetDebugUtilsObjectNameEXT on WSI objects +- zink: store bindless var when creating it to avoid creating it again +- nir: fix several crashes in \`nir_lower_tex` +- nir: don't take the derivative of the array index in \`nir_lower_tex` +- vulkan: use instance allocator for \`object_name` in some objects + +cheyang (1): + +- isaspec : fix isaspec build error in aosp + +georgeouzou (1): + +- nvk: Support VK_EXT_line_rasterization + +jazzfool (1): + +- zink: Hash only first 32 bits of zink_gfx_pipeline_state with full DS3 + +lorn10 (1): + +- docs: Update Clover's env variable documentation + +norablackcat (2): + +- spirv/nir_to_spirv: add expect assume op codes +- rusticl: add cl_khr_expect_assume + +timmac-qmc (1): + +- glsl: fix potential crash with DisableUniformArrayResize + +twisted89 (1): + +- util/driconf: add workarounds for the Chronicles of Riddick + +wangra (1): + +- tu/kgsl: Fix bitfield of DITHER_MODE_MRT6 + +xurui (1): + +- glx: There is no need to psc++ diff --git a/docs/relnotes/23.3.1.rst b/docs/relnotes/23.3.1.rst new file mode 100644 index 00000000000..0b6b66e7d73 --- /dev/null +++ b/docs/relnotes/23.3.1.rst @@ -0,0 +1,183 @@ +Mesa 23.3.1 Release Notes / 2023-12-13 +====================================== + +Mesa 23.3.1 is a bug fix release which fixes bugs found since the 23.3.0 release. + +Mesa 23.3.1 implements the OpenGL 4.6 API, but the version reported by +glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) / +glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used. +Some drivers don't support all the features required in OpenGL 4.6. OpenGL +4.6 is **only** available if requested at context creation. +Compatibility contexts may report a lower version depending on each driver. + +Mesa 23.3.1 implements the Vulkan 1.3 API, but the version reported by +the apiVersion property of the VkPhysicalDeviceProperties struct +depends on the particular driver being used. + +SHA256 checksum +--------------- + +:: + + 6e48126d70fdb3f20ffeb246ca0c2e41ffdc835f0663a03d4526b8bf5db41de6 mesa-23.3.1.tar.xz + + +New features +------------ + +- None + + +Bug fixes +--------- + +- [23.3.0] Parallel build failure - fatal error: vtn_generator_ids.h: No such file or directory +- crocus: Assertion failures in NIR divergence analysis +- anv: Resident Evil 2 hang +- Mesa 23.3.0 release build fails on 22.04 LTS +- Segfault in SDL2 game when using environment variables: \`SDL_VIDEODRIVER=wayland DRI_PRIME=1\` +- Mesa 22.3.0 SEGFAULT in nir shader creation for r600 cards on FreeBSD +- anv: piglit tests regressed for zink +- aco,radeonsi: GFX11 dEQP-GLES31.functional.separate_shader.random.0 fail when AMD_DEBUG=useaco + + +Changes +------- + +Alessandro Astone (1): + +- asahi: Use the compat version of qsort_r + +Boris Brezillon (2): + +- panfrost: Fix multiplanar YUV texture descriptor emission on v9+ +- panfrost: Don't leak NIR compute shaders + +Dave Airlie (1): + +- nvk: fix transform feedback with multiple saved counters. + +David Heidelberg (1): + +- docs: drop unused manual optimizations override + +Eric Engestrom (16): + +- docs: add release notes for 23.3.0 +- docs: add sha256sum for 23.3.0 +- .pick_status.json: Update to 0e1bee73eb401e3b9c39f4777f775dd3ab9a08e2 +- .pick_status.json: Mark e0c2244ea9b162788c781398743919956b0d55b7 as denominated +- bin/gen_release_notes: fix regex raw string +- .pick_status.json: Update to ebaede788e05ea3a22bfd4f054c85053247de9ff +- amd/ci: radeonsi is gl, not vk +- .pick_status.json: Update to 1700c6af6f807f801382c6cea5cb7136563e8bad +- nvk: use \`||\` instead of \`|\` between bools +- .pick_status.json: Update to 5bf68ab70133edd264f832f4a133288b8b45f66d +- ci: fix rules for formatting checks +- v3d: drop leftover from "move v3d_tiling to common" +- .pick_status.json: Update to 9ab59574ef162393f89c36980a366eeb8ecccb64 +- .pick_status.json: Update to a921a69010102c6e35267066dc8a50461cae46fd +- spirv: add missing build dependency +- ci: fix kdl commit fetch + +Erik Faye-Lund (1): + +- meson: work around meson 0.62 issue + +Felix bridault (1): + +- radv: use 32bit va range for sparse descriptor buffers + +Georg Lehmann (1): + +- aco: don't optimize DPP across more than one block + +Gert Wollny (2): + +- r600/sfn: Fix usage of std::string constructor +- r600/sfn: Don't try to re-use iterators when the set is made empty + +Ian Romanick (1): + +- nir: Handle divergence for decl_reg + +José Expósito (1): + +- zink: initialize drm_fd to -1 + +José Roberto de Souza (1): + +- anv: Fix handling of host_cached_coherent bos in gen9 lp in older kernels + +Juan A. Suarez Romero (2): + +- ci/baremetal: make BM_BOOTCONFIG optional +- ci: do not mount already mounted directories + +Juston Li (2): + +- venus: implement vkGet[Device]ImageSparseMemoryRequirements +- venus: fix query feedback copy sanitize off by 1 + +Kenneth Graunke (2): + +- anv: Drop 3/4 of PPGTT size restriction for sys heap size calculation +- anv: Don't report more memory available than the heap size + +Konstantin Seurer (1): + +- nir/lower_vars_to_scratch: Remove all unused derefs + +Lionel Landwerlin (5): + +- intel/fs: fix incorrect register flag interaction with dynamic interpolator mode +- intel/aux_map: introduce ref count of L1 entries +- anv: use main image address to determine ccs compatibility +- anv: track & unbind image aux-tt binding +- anv: remove heuristic preferring dedicated allocations + +Mario Kleiner (1): + +- v3d: add B10G10R10[X2/A2]_UNORM to format table. + +Mark Collins (1): + +- meson: Update lua wrap to 5.4.6-4 + +Pierre-Eric Pelloux-Prayer (1): + +- egl/wayland: set the correct modifier for the linear_copy image + +Rhys Perry (1): + +- nir/loop_analyze: skip if basis/limit/comparison is vector + +Rob Clark (2): + +- freedreno/drm: Fix zombie BO import harder +- freedreno/a6xx: Fix NV12+UBWC import + +Rohan Garg (1): + +- intel/compiler: infer the number of operands using lsc_op_num_data_values + +Samuel Pitoiset (2): + +- radv: fix bogus interaction between DGC and RT with descriptor bindings +- radv: set combinedImageSamplerDescriptorCount to 1 for multi-planar formats + +Sil Vilerino (3): + +- d3d12: Fix d3d12_tcs_variant_cache_destroy leak in d3d12_context +- d3d12: Fix screen->winsys leak in d3d12_screen +- d3d12: d3d12_create_fence_win32 - Fix double refcount bump + +Sviatoslav Peleshko (1): + +- anv: Fix MI_ARB_CHECK calls in generated indirect draws optimization + +Yiwei Zhang (3): + +- venus: fix async compute pipeline creation +- venus: properly initialize ring monitor initial alive status +- driconfig: add a workaround for Hades (Vulkan backend) diff --git a/docs/relnotes/23.3.2.rst b/docs/relnotes/23.3.2.rst new file mode 100644 index 00000000000..0f5a088c747 --- /dev/null +++ b/docs/relnotes/23.3.2.rst @@ -0,0 +1,177 @@ +Mesa 23.3.2 Release Notes / 2023-12-27 +====================================== + +Mesa 23.3.2 is a bug fix release which fixes bugs found since the 23.3.1 release. + +Mesa 23.3.2 implements the OpenGL 4.6 API, but the version reported by +glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) / +glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used. +Some drivers don't support all the features required in OpenGL 4.6. OpenGL +4.6 is **only** available if requested at context creation. +Compatibility contexts may report a lower version depending on each driver. + +Mesa 23.3.2 implements the Vulkan 1.3 API, but the version reported by +the apiVersion property of the VkPhysicalDeviceProperties struct +depends on the particular driver being used. + +SHA256 checksum +--------------- + +:: + + 3cfcb81fa16f89c56abe3855d2637d396ee4e03849b659000a6b8e5f57e69adc mesa-23.3.2.tar.xz + + +New features +------------ + +- None + + +Bug fixes +--------- + +- anv: glcts regression on zink +- nir: Trivial loop not unrolling +- Possible regression with AMD GPU with flatpak apps +- Compiling Mesa with X in custom prefix fails in Intel Vulkan driver +- radv/aco: Crysis 2 Remastered RT reflections are blocky around the edges with ACO, renders normally with LLVM + + +Changes +------- + +Bas Nieuwenhuizen (1): + +- radv: Use correct writemask for cooperative matrix ordering. + +Boris Brezillon (3): + +- util/hash_table: Use FREE() to be consistent with the CALLOC_STRUCT() call +- util/hash_table: Don't leak hash_u64_key objects when the entry exists +- util/hash_table: Don't leak hash_key_u64 objects when the u64 hash table is destroyed + +Christian Gmeiner (2): + +- etnaviv: Update headers from rnndb +- etnaviv: Add static_assert(..) to catch memory corruption + +Dave Airlie (1): + +- intel/compiler: move gen5 final pass to actually be final pass + +David Heidelberg (2): + +- ci/freedreno: timestamp-get no longer fails on Adreno +- ci/freedreno: fail introduced by ARB_post_depth_coverage + +Eric Engestrom (10): + +- docs: add sha256sum for 23.3.1 +- .pick_status.json: Update to d761871761e5fe7d498b0cc818ed627698ed1225 +- .pick_status.json: Update to 377c6b2d45ee73da3e5431846a3b4bfdd7ae2b83 +- ci/b2c: drop passthrough of unset CI_JOB_JWT +- .pick_status.json: Updates notes for 6a92af158dc132eee449c175bdee66d92c68d191 +- vulkan/wsi: fix build when platform headers are installed in non-standard locations +- .pick_status.json: Update to 670a799ebff9a98daafccf49324c2a01311b0c41 +- .pick_status.json: Update to e61fae6eb8ae1ae1228d6f89329324310db808ae +- .pick_status.json: Update to 1e6fcd6a611574241b1cde306afcc416a03ac76b +- .pick_status.json: Update to 55c262898ae7188311c89a60e4ec0fbb67b7a95b + +Faith Ekstrand (1): + +- nir: Scalarize bounds checked loads and stores + +Friedrich Vock (2): + +- radv,vtn,driconf: Add and use radv_rt_ssbo_non_uniform workaround for Crysis 2/3 Remastered +- radv/rt: Initialize unused children in PLOC early-exit + +George Ouzounoudis (1): + +- vulkan: Fix dynamic graphics state enum usage + +Gert Wollny (1): + +- r600/sfn: keep workgroup and invocation ID registers for whole shader + +Jesse Natalie (1): + +- d3d12: Only destroy the winsys during screen destruction, not reset + +Jonathan Gray (1): + +- intel/common: add directory prefix to intel_gem.h include + +José Expósito (1): + +- egl/glx: fallback to software when Zink is forced and fails + +Karol Herbst (4): + +- rusticl/kernel: explicitly set rounding modes +- rusticl: do not warn on empty RUSTICL_DEBUG or RUSTICL_FEATURES +- rusticl: silence clippy::arc-with-non-send-sync for now +- rusticl: check rustc version for flags requiring newer rustc/clippy + +Kenneth Graunke (3): + +- iris: Initialize bo->index to -1 when importing buffers +- iris: Don't search the exec list if BOs have never been added to one +- iris: Skip mi_builder init for indirect draws + +Lionel Landwerlin (4): + +- nir/clone: fix missing printf_info clone +- nir/divergence: handle printf intrinsic +- anv: fix incorrect queue_family access on command buffer +- anv: wait for CS write completion before executing secondary + +Michel Dänzer (2): + +- gallium/dri: Return __DRI_ATTRIB_SWAP_UNDEFINED for _SWAP_METHOD +- glx: Handle IGNORE_GLX_SWAP_METHOD_OML regardless of GLX_USE_APPLEGL + +Pierre-Eric Pelloux-Prayer (4): + +- radeonsi/sqtt: fix RGP pm4 state emit function +- radeonsi/sqtt: clear record_counts variable +- radeonsi/sqtt: rework pm4.reg_va_low_idx +- radeonsi/sqtt: use calloc instead of malloc + +Robert Foss (1): + +- egl/surfaceless: Fix EGL_DEVICE_EXT implementation + +Sil Vilerino (1): + +- d3d12: Fix AV1 video encode 32 bits build + +Sviatoslav Peleshko (2): + +- nir/loop_analyze: Don't test non-positive iterations count +- intel/fs: Don't optimize DW*1 MUL if it stores value to the accumulator + +Tapani Pälli (5): + +- anv/hasvk/drirc: change anv_assume_full_subgroups to have subgroup size +- drirc: setup anv_assume_full_subgroups=16 for UnrealEngine5.1 +- iris: use intel_needs_workaround with 14015055625 +- mesa: fix enum support for EXT_clip_cull_distance +- drirc/anv: disable FCV optimization for Baldur's Gate 3 + +Timothy Arceri (1): + +- radeonsi: fix divide by zero in si_get_small_prim_cull_info() + +Vinson Lee (1): + +- etnaviv: Remove duplicate initializers + +Yiwei Zhang (1): + +- vulkan/wsi/wayland: ensure drm modifiers stored in chain are immutable + +Yonggang Luo (1): + +- dzn: Fixes -Werror=incompatible-pointer-type diff --git a/docs/relnotes/23.3.3.rst b/docs/relnotes/23.3.3.rst new file mode 100644 index 00000000000..dd0b7486a72 --- /dev/null +++ b/docs/relnotes/23.3.3.rst @@ -0,0 +1,155 @@ +Mesa 23.3.3 Release Notes / 2024-01-10 +====================================== + +Mesa 23.3.3 is a bug fix release which fixes bugs found since the 23.3.2 release. + +Mesa 23.3.3 implements the OpenGL 4.6 API, but the version reported by +glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) / +glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used. +Some drivers don't support all the features required in OpenGL 4.6. OpenGL +4.6 is **only** available if requested at context creation. +Compatibility contexts may report a lower version depending on each driver. + +Mesa 23.3.3 implements the Vulkan 1.3 API, but the version reported by +the apiVersion property of the VkPhysicalDeviceProperties struct +depends on the particular driver being used. + +SHA256 checksum +--------------- + +:: + + TBD. + + +New features +------------ + +- None + + +Bug fixes +--------- + +- Error during SPIR-V parsing of OpCopyLogical +- radv: Atlas Fallen corrupted rendering +- intel: Require 64KB alignment when using CCS and multiple engines +- 23.3.2 regression: kms_swrast_dri.so segfaults +- Mesa is not compatible with Python 3.12 due to use of distutils +- anv: importing memory for a compressed image using modifier is hitting an assert + + +Changes +------- + +Connor Abbott (1): + +- ir3/legalize: Fix helper propagation with b.any/b.all/getone + +Daniel Schürmann (1): + +- nir/opt_move_discards_to_top: don't schedule discard/demote across subgroup operations + +Dave Airlie (5): + +- gallivm: handle llvm 16 atexit ordering problems. +- intel/compiler: fix release build unused variable. +- llvmpipe: fix caching for texture shaders. +- intel/compiler: reemit boolean resolve for inverted if on gen5 +- radv: don't emit cp dma packets on video rings. + +Eric Engestrom (13): + +- docs: add sha256sum for 23.3.2 +- .pick_status.json: Mark eb5bb5c784e97c533e30b348e82e446ac0da59c8 as denominated +- .pick_status.json: Update to ebee672ef87794f3f4201270623a92f34e62b8ff +- .pick_status.json: Mark 060439bdf0e74f0f2e255d0a81b5356f9a2f5457 as denominated +- .pick_status.json: Mark 8d0e70f628b745ad81124e0c3fe5e46ea84f6b46 as denominated +- .pick_status.json: Update to 39c8cca34fb72db055df18abf1d473e099f4b05b +- .pick_status.json: Update to 2c078bfd18cae0ed1a0a3916020e49fb74668504 +- .pick_status.json: Update to e2a7c877ad1fd6bda4032f707eea7646e5229969 +- .pick_status.json: Update to 031978933151e95690e93919e7bfd9f1753f2794 +- .pick_status.json: Mark fbe4e16db2d369c3e54067d17f81bdce8661a461 as denominated +- .pick_status.json: Mark b38c776690c9c39b04c57d74f9b036de56995aff as denominated +- .pick_status.json: Update to f6d2df5a7542025022e69b81dbe3af3e51ea5cd3 +- .pick_status.json: Update to 67ad1142cf6afe61de834cefeddb4be06382899f + +Erik Faye-Lund (2): + +- zink: update profile schema +- zink: use KHR version of maint5 features + +Friedrich Vock (1): + +- radv/rt: Free traversal NIR after compilation + +Georg Lehmann (1): + +- aco: fix applying input modifiers to DPP8 + +Jonathan Gray (1): + +- zink: put sysmacros.h include under #ifdef MAJOR_IN_SYSMACROS + +José Roberto de Souza (2): + +- anv: Assume that imported bos already have flat CCS requirements satisfied +- anv: Increase ANV_MAX_QUEUE_FAMILIES + +Karol Herbst (2): + +- zink: lock screen queue on context_destroy and CreateSwapchain +- zink: fix heap-use-after-free on batch_state with sub-allocated pipe_resources + +Konstantin Seurer (2): + +- vtn: Remove transpose(m0)*m1 fast path +- vtn: Allow for OpCopyLogical with different but compatible types + +Leo Liu (1): + +- gallium/vl: match YUYV/UYVY swizzle with change of color channels + +Lionel Landwerlin (2): + +- isl: implement Wa_22015614752 +- intel/fs: fix depth compute state for unchanged depth layout + +Marek Olšák (1): + +- glthread: don't unroll draws using user VBOs with GLES + +Mary Guillemard (2): + +- zink: Initialize pQueueFamilyIndices for image query / create +- zink: Always fill external_only in zink_query_dmabuf_modifiers + +Mike Blumenkrantz (1): + +- zink: enforce maxTexelBufferElements for texel buffer sizing + +Rhys Perry (1): + +- aco/tests: use more raw strings + +Samuel Pitoiset (2): + +- radv: fix binding partial depth/stencil views with dynamic rendering +- radv: disable stencil test without a stencil attachment + +Sil Vilerino (2): + +- Revert "d3d12: Only destroy the winsys during screen destruction, not reset" +- Revert "d3d12: Fix screen->winsys leak in d3d12_screen" + +Vinson Lee (1): + +- ac/rgp: Fix single-bit-bitfield-constant-conversion warning + +Yonggang Luo (1): + +- meson: Support for both packaging and distutils + +antonino (1): + +- egl: only check dri3 on X11 diff --git a/docs/relnotes/new_features.txt b/docs/relnotes/new_features.txt deleted file mode 100644 index ca79cf2a745..00000000000 --- a/docs/relnotes/new_features.txt +++ /dev/null @@ -1,21 +0,0 @@ -New drivers ------------ - -- NVK: A Vulkan driver for Nvidia hardware - -New features ------------- -VK_EXT_pipeline_robustness on ANV -VK_KHR_maintenance5 on RADV -OpenGL ES 3.1 on Asahi -GL_ARB_compute_shader on Asahi -GL_ARB_shader_atomic_counters on Asahi -GL_ARB_shader_image_load_store on Asahi -GL_ARB_shader_image_size on Asahi -GL_ARB_shader_storage_buffer_object on Asahi -GL_ARB_sample_shading on Asahi -GL_OES_sample_variables on Asahi -GL_OES_shader_multisample_interpolation on Asahi -GL_OES_gpu_shader5 on Asahi -EGL_ANDROID_blob_cache works when disk caching is disabled -VK_KHR_cooperative_matrix on RADV/GFX11+ diff --git a/meson.build b/meson.build index 722469fbe37..2902c1019f6 100644 --- a/meson.build +++ b/meson.build @@ -155,7 +155,16 @@ if gallium_drivers.contains('auto') error('Unknown OS @0@. Please pass -Dgallium-drivers to set driver options. Patches gladly accepted to fix this.'.format( host_machine.system())) endif +elif gallium_drivers.contains('all') + # Build-test everything except for i915, which depends on libdrm-intel which + # is not available on non-Intel distros. + gallium_drivers = [ + 'r300', 'r600', 'radeonsi', 'crocus', 'v3d', 'vc4', 'freedreno', 'etnaviv', + 'nouveau', 'svga', 'tegra', 'virgl', 'lima', 'panfrost', 'swrast', 'iris', + 'zink', 'd3d12', 'asahi' + ] endif + with_gallium_radeonsi = gallium_drivers.contains('radeonsi') with_gallium_r300 = gallium_drivers.contains('r300') with_gallium_r600 = gallium_drivers.contains('r600') @@ -213,6 +222,12 @@ if _vulkan_drivers.contains('auto') error('Unknown OS @0@. Please pass -Dvulkan-drivers to set driver options. Patches gladly accepted to fix this.'.format( host_machine.system())) endif +elif _vulkan_drivers.contains('all') + # Build every vulkan driver regardless of architecture. + _vulkan_drivers = ['amd', 'intel', 'intel_hasvk', 'swrast', + 'freedreno', 'panfrost', 'virtio', 'broadcom', + 'imagination-experimental', 'microsoft-experimental', + 'nouveau-experimental'] endif with_intel_vk = _vulkan_drivers.contains('intel') @@ -781,6 +796,7 @@ if with_gallium_rusticl endif add_languages('rust', required: true) + rustc = meson.get_compiler('rust') with_clc = true endif @@ -870,9 +886,12 @@ prog_python = import('python').find_installation('python3') has_mako = run_command( prog_python, '-c', ''' -from distutils.version import StrictVersion +try: + from packaging.version import Version +except: + from distutils.version import StrictVersion as Version import mako -assert StrictVersion(mako.__version__) >= StrictVersion("0.8.0") +assert Version(mako.__version__) >= Version("0.8.0") ''', check: false) if has_mako.returncode() != 0 error('Python (3.x) mako module >= 0.8.0 required to build mesa.') @@ -1459,7 +1478,6 @@ elif with_intel_vk or with_intel_hasvk error('Intel "Anvil" Vulkan driver requires the dl_iterate_phdr function') endif -# only used in Iris and ANV if with_any_intel and ['x86', 'x86_64'].contains(host_machine.cpu_family()) pre_args += '-DSUPPORT_INTEL_INTEGRATED_GPUS' endif @@ -1468,13 +1486,6 @@ if get_option('intel-xe-kmd').enabled() pre_args += '-DINTEL_XE_KMD_SUPPORTED' endif -if with_intel_hasvk and host_machine.cpu_family().startswith('x86') == false - error('Intel "hasvk" Vulkan driver requires x86 or x86_64 CPU family') -endif - -if with_gallium_crocus and host_machine.cpu_family().startswith('x86') == false - error('Intel "crocus" Gallium driver requires x86 or x86_64 CPU family') -endif if with_gallium_i915 and host_machine.cpu_family().startswith('x86') == false error('Intel "i915" Gallium driver requires x86 or x86_64 CPU family') diff --git a/meson_options.txt b/meson_options.txt index 8130c3e9321..e885ba61a8a 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -73,7 +73,7 @@ option( choices : [ 'auto', 'kmsro', 'radeonsi', 'r300', 'r600', 'nouveau', 'freedreno', 'swrast', 'v3d', 'vc4', 'etnaviv', 'tegra', 'i915', 'svga', 'virgl', - 'panfrost', 'iris', 'lima', 'zink', 'd3d12', 'asahi', 'crocus' + 'panfrost', 'iris', 'lima', 'zink', 'd3d12', 'asahi', 'crocus', 'all', ], description : 'List of gallium drivers to build. If this is set to auto ' + 'all drivers applicable to the target OS/architecture ' + @@ -211,7 +211,7 @@ option( value : ['auto'], choices : ['auto', 'amd', 'broadcom', 'freedreno', 'intel', 'intel_hasvk', 'panfrost', 'swrast', 'virtio', 'imagination-experimental', - 'microsoft-experimental', 'nouveau-experimental'], + 'microsoft-experimental', 'nouveau-experimental', 'all'], description : 'List of vulkan drivers to build. If this is set to auto ' + 'all drivers applicable to the target OS/architecture ' + 'will be built' diff --git a/src/amd/ci/gitlab-ci-inc.yml b/src/amd/ci/gitlab-ci-inc.yml index 954ee8b983e..8ea316210cb 100644 --- a/src/amd/ci/gitlab-ci-inc.yml +++ b/src/amd/ci/gitlab-ci-inc.yml @@ -84,7 +84,7 @@ stage: amd rules: - !reference [.valve-farm-manual-rules, rules] - - !reference [.vulkan-manual-rules, rules] + - !reference [.gl-manual-rules, rules] - changes: *radeonsi_file_list when: manual diff --git a/src/amd/ci/radv-navi10-aco-fails.txt b/src/amd/ci/radv-navi10-aco-fails.txt index 2967a976f05..acda34d6cf2 100644 --- a/src/amd/ci/radv-navi10-aco-fails.txt +++ b/src/amd/ci/radv-navi10-aco-fails.txt @@ -1,3 +1,2 @@ # New CTS failures in 1.3.7.0 dEQP-VK.api.version_check.unavailable_entry_points,Fail -dEQP-VK.dynamic_rendering.primary_cmd_buff.basic.partial_binding_depth_stencil,Fail diff --git a/src/amd/ci/radv-navi21-aco-flakes.txt b/src/amd/ci/radv-navi21-aco-flakes.txt index 663dfca4d0b..b6e62fed8ad 100644 --- a/src/amd/ci/radv-navi21-aco-flakes.txt +++ b/src/amd/ci/radv-navi21-aco-flakes.txt @@ -19,6 +19,3 @@ dEQP-VK.ray_tracing_pipeline.pipeline_library.configurations.multithreaded_compi dEQP-VK.ray_tracing_pipeline.pipeline_library.configurations.multithreaded_compilation.*_check_capture_replay_handles dEQP-VK.ray_tracing_pipeline.pipeline_library.configurations.singlethreaded_compilation.*_check_all_handles dEQP-VK.ray_tracing_pipeline.pipeline_library.configurations.singlethreaded_compilation.*_check_capture_replay_handles - -# New CTS flakes in 1.3.7.0 -dEQP-VK.transform_feedback.primitives_generated_query.get.* diff --git a/src/amd/ci/radv-polaris10-aco-fails.txt b/src/amd/ci/radv-polaris10-aco-fails.txt index 9ed35ee6c8d..c07d22fe8fc 100644 --- a/src/amd/ci/radv-polaris10-aco-fails.txt +++ b/src/amd/ci/radv-polaris10-aco-fails.txt @@ -20,4 +20,3 @@ dEQP-VK.texture.mipmap.cubemap.image_view_min_lod.base_level.nearest_nearest,Fai # New CTS failures in 1.3.7.0. dEQP-VK.api.version_check.unavailable_entry_points,Fail -dEQP-VK.dynamic_rendering.primary_cmd_buff.basic.partial_binding_depth_stencil,Fail diff --git a/src/amd/ci/radv-renoir-aco-fails.txt b/src/amd/ci/radv-renoir-aco-fails.txt index e37b1a769a6..a91278246ec 100644 --- a/src/amd/ci/radv-renoir-aco-fails.txt +++ b/src/amd/ci/radv-renoir-aco-fails.txt @@ -1,3 +1,2 @@ # New CTS failures in 1.3.7.0. dEQP-VK.api.version_check.unavailable_entry_points,Fail -dEQP-VK.dynamic_rendering.primary_cmd_buff.basic.partial_binding_depth_stencil,Fail diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 418a1989344..e289d741bc6 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -705,9 +705,6 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, return false; } - assert(util_is_power_of_two_or_zero(info->ip[AMD_IP_COMPUTE].num_queues)); - assert(util_is_power_of_two_or_zero(info->ip[AMD_IP_SDMA].num_queues)); - r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0, &info->me_fw_version, &info->me_fw_feature); if (r) { @@ -1249,6 +1246,13 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, info->family == CHIP_BONAIRE || info->family == CHIP_KABINI; + /* HW bug workaround with async compute dispatches when threadgroup > 4096. + * The workaround is to change the "threadgroup" dimension mode to "thread" + * dimension mode. + */ + info->has_async_compute_threadgroup_bug = info->family == CHIP_ICELAND || + info->family == CHIP_TONGA; + /* Support for GFX10.3 was added with F32_ME_FEATURE_VERSION_31 but the * feature version wasn't bumped. */ diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index c9d66f7aaba..9cd24a10d01 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -101,6 +101,7 @@ struct radeon_info { bool has_two_planes_iterate256_bug; bool has_vgt_flush_ngg_legacy_bug; bool has_cs_regalloc_hang_bug; + bool has_async_compute_threadgroup_bug; bool has_32bit_predication; bool has_3d_cube_border_color_mipmap; bool has_image_opcodes; diff --git a/src/amd/common/ac_nir_lower_ngg.c b/src/amd/common/ac_nir_lower_ngg.c index eaa675bf13e..19291338128 100644 --- a/src/amd/common/ac_nir_lower_ngg.c +++ b/src/amd/common/ac_nir_lower_ngg.c @@ -3903,6 +3903,7 @@ ms_store_arrayed_output_intrin(nir_builder *b, nir_def *soffset = nir_load_ring_attr_offset_amd(b); nir_store_buffer_amd(b, store_val, ring, base_addr_off, soffset, arr_index, .base = const_off + param_offset * 16, + .write_mask = write_mask, .memory_modes = nir_var_shader_out, .access = ACCESS_COHERENT | ACCESS_IS_SWIZZLED_AMD); } else if (out_mode == ms_out_mode_var) { diff --git a/src/amd/common/ac_rgp.c b/src/amd/common/ac_rgp.c index 71c61f54975..c6a748410e3 100644 --- a/src/amd/common/ac_rgp.c +++ b/src/amd/common/ac_rgp.c @@ -79,9 +79,9 @@ struct sqtt_file_chunk_header { struct sqtt_file_header_flags { union { struct { - int32_t is_semaphore_queue_timing_etw : 1; - int32_t no_queue_semaphore_timestamps : 1; - int32_t reserved : 30; + uint32_t is_semaphore_queue_timing_etw : 1; + uint32_t no_queue_semaphore_timestamps : 1; + uint32_t reserved : 30; }; uint32_t value; diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 0f7fd5b3c27..561f3cc02e0 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -8640,7 +8640,7 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) src = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)); src = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), mask_tmp, src); - bld.sop1(Builder::s_wqm, Definition(dst), src); + bld.sop1(Builder::s_wqm, Definition(dst), bld.def(s1, scc), src); } else if (instr->def.bit_size <= 32 || bool_use_valu) { unsigned excess_bytes = bool_use_valu ? 0 : 4 - instr->def.bit_size / 8; Definition def = (excess_bytes || bool_use_valu) ? bld.def(v1) : Definition(dst); diff --git a/src/amd/compiler/aco_optimizer.cpp b/src/amd/compiler/aco_optimizer.cpp index 9fdbffc7994..fa9c34a68b6 100644 --- a/src/amd/compiler/aco_optimizer.cpp +++ b/src/amd/compiler/aco_optimizer.cpp @@ -1440,7 +1440,7 @@ label_instruction(opt_ctx& ctx, aco_ptr& instr) instr->operands[i].setTemp(info.temp); } else if (info.is_neg() && can_use_mod && mod_bitsize_compat && can_eliminate_fcanonicalize(ctx, instr, info.temp, i)) { - if (!instr->isDPP() && !instr->isSDWA()) + if (!instr->isDPP16() && can_use_VOP3(ctx, instr)) instr->format = asVOP3(instr->format); instr->operands[i].setTemp(info.temp); if (!instr->valu().abs[i]) @@ -1448,7 +1448,7 @@ label_instruction(opt_ctx& ctx, aco_ptr& instr) } if (info.is_abs() && can_use_mod && mod_bitsize_compat && can_eliminate_fcanonicalize(ctx, instr, info.temp, i)) { - if (!instr->isDPP() && !instr->isSDWA()) + if (!instr->isDPP16() && can_use_VOP3(ctx, instr)) instr->format = asVOP3(instr->format); instr->operands[i] = Operand(info.temp); instr->valu().abs[i] = true; diff --git a/src/amd/compiler/aco_optimizer_postRA.cpp b/src/amd/compiler/aco_optimizer_postRA.cpp index 48ada196926..5978e7c4b46 100644 --- a/src/amd/compiler/aco_optimizer_postRA.cpp +++ b/src/amd/compiler/aco_optimizer_postRA.cpp @@ -492,6 +492,13 @@ try_combine_dpp(pr_opt_ctx& ctx, aco_ptr& instr) if (!op_instr_idx.found()) continue; + /* is_overwritten_since only considers active lanes when the register could possibly + * have been overwritten from inactive lanes. Restrict this optimization to at most + * one block so that there is no possibility for clobbered inactive lanes. + */ + if (ctx.current_block->index - op_instr_idx.block > 1) + continue; + const Instruction* mov = ctx.get(op_instr_idx); if (mov->opcode != aco_opcode::v_mov_b32 || !mov->isDPP()) continue; diff --git a/src/amd/compiler/aco_scheduler.cpp b/src/amd/compiler/aco_scheduler.cpp index 592e42c54c4..f4cebf7a493 100644 --- a/src/amd/compiler/aco_scheduler.cpp +++ b/src/amd/compiler/aco_scheduler.cpp @@ -596,13 +596,15 @@ perform_hazard_query(hazard_query* query, Instruction* instr, bool upwards) return hazard_fail_exec; /* Don't move exports so that they stay closer together. + * Since GFX11, export order matters. MRTZ must come first, + * then color exports sorted from first to last. * Also, with Primitive Ordered Pixel Shading on GFX11+, the `done` export must not be moved * above the memory accesses before the queue family scope (more precisely, fragment interlock * scope, but it's not available in ACO) release barrier that is expected to be inserted before * the export, as well as before any `s_wait_event export_ready` which enters the ordered * section, because the `done` export exits the ordered section. */ - if (instr->isEXP()) + if (instr->isEXP() || instr->opcode == aco_opcode::p_dual_src_export_gfx11) return hazard_fail_export; /* don't move non-reorderable instructions */ diff --git a/src/amd/compiler/tests/glsl_scraper.py b/src/amd/compiler/tests/glsl_scraper.py index 291b33958f4..3167d7cf614 100644 --- a/src/amd/compiler/tests/glsl_scraper.py +++ b/src/amd/compiler/tests/glsl_scraper.py @@ -28,16 +28,16 @@ def __init__(self, *args): } base_layout_qualifier_id_re = r'({0}\s*=\s*(?P<{0}>\d+))' -id_re = '(?P[^(gl_)]\w+)' -type_re = '(?P\w+)' +id_re = r'(?P[^(gl_)]\w+)' +type_re = r'(?P\w+)' location_re = base_layout_qualifier_id_re.format('location') component_re = base_layout_qualifier_id_re.format('component') binding_re = base_layout_qualifier_id_re.format('binding') set_re = base_layout_qualifier_id_re.format('set') unk_re = r'\w+(=\d+)?' layout_qualifier_re = r'layout\W*\((%s)+\)' % '|'.join([location_re, binding_re, set_re, unk_re, '[, ]+']) -ubo_decl_re = 'uniform\W+%s(\W*{)?(?P)' % (id_re%0) -ssbo_decl_re = 'buffer\W+%s(\W*{)?(?P)' % (id_re%1) +ubo_decl_re = r'uniform\W+%s(\W*{)?(?P)' % (id_re%0) +ssbo_decl_re = r'buffer\W+%s(\W*{)?(?P)' % (id_re%1) image_buffer_decl_re = r'uniform\W+imageBuffer\w+%s;(?P)' % (id_re%2) image_decl_re = r'uniform\W+image\w+\W+%s;(?P)' % (id_re%3) texture_buffer_decl_re = r'uniform\W+textureBuffer\w+%s;(?P)' % (id_re%4) diff --git a/src/amd/compiler/tests/test_optimizer_postRA.cpp b/src/amd/compiler/tests/test_optimizer_postRA.cpp index 811e762399b..c0cb4fc8a2f 100644 --- a/src/amd/compiler/tests/test_optimizer_postRA.cpp +++ b/src/amd/compiler/tests/test_optimizer_postRA.cpp @@ -571,6 +571,12 @@ BEGIN_TEST(optimizer_postRA.dpp_across_cf) //! buffer_store_dword %c:v[2], 0, %d:v[3], 0 offen bld.mubuf(aco_opcode::buffer_store_dword, c, Operand::zero(), d, Operand::zero(), 0, true); + //! v1: %res10:v[12] = v_add_f32 %a:v[0], %b:v[1] row_mirror bound_ctrl:1 fi + //! p_unit_test 10, %res10:v[12] + Temp result = + bld.vop2(aco_opcode::v_add_f32, bld.def(v1, reg_v12), Operand(dpp_tmp, reg_v12), b); + writeout(10, Operand(result, reg_v12)); + //! p_logical_end //! s2: %0:vcc = p_branch BB3 @@ -605,12 +611,6 @@ BEGIN_TEST(optimizer_postRA.dpp_across_cf) //! /* logical preds: BB1, BB4, / linear preds: BB4, BB5, / kind: uniform, top-level, merge, */ //! s2: %0:exec = p_parallelcopy %saved_exec:s[84-85] - //! v1: %res10:v[12] = v_add_f32 %a:v[0], %b:v[1] row_mirror bound_ctrl:1 fi - //! p_unit_test 10, %res10:v[12] - Temp result = - bld.vop2(aco_opcode::v_add_f32, bld.def(v1, reg_v12), Operand(dpp_tmp, reg_v12), b); - writeout(10, Operand(result, reg_v12)); - finish_optimizer_postRA_test(); END_TEST diff --git a/src/amd/vulkan/bvh/ploc_internal.comp b/src/amd/vulkan/bvh/ploc_internal.comp index 267a914d89b..c7c8b5d394e 100644 --- a/src/amd/vulkan/bvh/ploc_internal.comp +++ b/src/amd/vulkan/bvh/ploc_internal.comp @@ -249,7 +249,8 @@ main(void) total_bounds.min = vec3(INFINITY); total_bounds.max = vec3(-INFINITY); - for (uint32_t i = 0; i < DEREF(args.header).active_leaf_count; i++) { + uint32_t i = 0; + for (; i < DEREF(args.header).active_leaf_count; i++) { uint32_t child_id = DEREF(INDEX(key_id_pair, src_ids, i)).id; if (child_id != RADV_BVH_INVALID_NODE) { @@ -263,6 +264,8 @@ main(void) DEREF(dst_node).children[i] = child_id; } + for (; i < 2; i++) + DEREF(dst_node).children[i] = RADV_BVH_INVALID_NODE; DEREF(dst_node).base.aabb = total_bounds; DEREF(dst_node).bvh_offset = RADV_UNKNOWN_BVH_OFFSET; diff --git a/src/amd/vulkan/layers/radv_sqtt_layer.c b/src/amd/vulkan/layers/radv_sqtt_layer.c index 7584d624839..be64c6cd6d3 100644 --- a/src/amd/vulkan/layers/radv_sqtt_layer.c +++ b/src/amd/vulkan/layers/radv_sqtt_layer.c @@ -767,10 +767,10 @@ sqtt_CmdCopyQueryPoolResults(VkCommandBuffer commandBuffer, VkQueryPool queryPoo flags); } -#define EVENT_RT_MARKER(cmd_name, ...) \ - EVENT_MARKER_BASE(cmd_name, Dispatch, cmd_name | ApiRayTracingSeparateCompiled, __VA_ARGS__); +#define EVENT_RT_MARKER(cmd_name, flags, ...) EVENT_MARKER_BASE(cmd_name, Dispatch, cmd_name | flags, __VA_ARGS__); -#define EVENT_RT_MARKER_ALIAS(cmd_name, event_name, ...) EVENT_MARKER_BASE(cmd_name, Dispatch, event_name, __VA_ARGS__); +#define EVENT_RT_MARKER_ALIAS(cmd_name, event_name, flags, ...) \ + EVENT_MARKER_BASE(cmd_name, Dispatch, event_name | flags, __VA_ARGS__); VKAPI_ATTR void VKAPI_CALL sqtt_CmdTraceRaysKHR(VkCommandBuffer commandBuffer, const VkStridedDeviceAddressRegionKHR *pRaygenShaderBindingTable, @@ -779,8 +779,8 @@ sqtt_CmdTraceRaysKHR(VkCommandBuffer commandBuffer, const VkStridedDeviceAddress const VkStridedDeviceAddressRegionKHR *pCallableShaderBindingTable, uint32_t width, uint32_t height, uint32_t depth) { - EVENT_RT_MARKER(TraceRaysKHR, commandBuffer, pRaygenShaderBindingTable, pMissShaderBindingTable, - pHitShaderBindingTable, pCallableShaderBindingTable, width, height, depth); + EVENT_RT_MARKER(TraceRaysKHR, ApiRayTracingSeparateCompiled, commandBuffer, pRaygenShaderBindingTable, + pMissShaderBindingTable, pHitShaderBindingTable, pCallableShaderBindingTable, width, height, depth); } VKAPI_ATTR void VKAPI_CALL @@ -791,14 +791,15 @@ sqtt_CmdTraceRaysIndirectKHR(VkCommandBuffer commandBuffer, const VkStridedDeviceAddressRegionKHR *pCallableShaderBindingTable, VkDeviceAddress indirectDeviceAddress) { - EVENT_RT_MARKER(TraceRaysIndirectKHR, commandBuffer, pRaygenShaderBindingTable, pMissShaderBindingTable, - pHitShaderBindingTable, pCallableShaderBindingTable, indirectDeviceAddress); + EVENT_RT_MARKER(TraceRaysIndirectKHR, ApiRayTracingSeparateCompiled, commandBuffer, pRaygenShaderBindingTable, + pMissShaderBindingTable, pHitShaderBindingTable, pCallableShaderBindingTable, indirectDeviceAddress); } VKAPI_ATTR void VKAPI_CALL sqtt_CmdTraceRaysIndirect2KHR(VkCommandBuffer commandBuffer, VkDeviceAddress indirectDeviceAddress) { - EVENT_RT_MARKER_ALIAS(TraceRaysIndirect2KHR, TraceRaysIndirectKHR, commandBuffer, indirectDeviceAddress); + EVENT_RT_MARKER_ALIAS(TraceRaysIndirect2KHR, TraceRaysIndirectKHR, ApiRayTracingSeparateCompiled, commandBuffer, + indirectDeviceAddress); } VKAPI_ATTR void VKAPI_CALL @@ -806,27 +807,27 @@ sqtt_CmdBuildAccelerationStructuresKHR(VkCommandBuffer commandBuffer, uint32_t i const VkAccelerationStructureBuildGeometryInfoKHR *pInfos, const VkAccelerationStructureBuildRangeInfoKHR *const *ppBuildRangeInfos) { - EVENT_RT_MARKER(BuildAccelerationStructuresKHR, commandBuffer, infoCount, pInfos, ppBuildRangeInfos); + EVENT_RT_MARKER(BuildAccelerationStructuresKHR, 0, commandBuffer, infoCount, pInfos, ppBuildRangeInfos); } VKAPI_ATTR void VKAPI_CALL sqtt_CmdCopyAccelerationStructureKHR(VkCommandBuffer commandBuffer, const VkCopyAccelerationStructureInfoKHR *pInfo) { - EVENT_RT_MARKER(CopyAccelerationStructureKHR, commandBuffer, pInfo); + EVENT_RT_MARKER(CopyAccelerationStructureKHR, 0, commandBuffer, pInfo); } VKAPI_ATTR void VKAPI_CALL sqtt_CmdCopyAccelerationStructureToMemoryKHR(VkCommandBuffer commandBuffer, const VkCopyAccelerationStructureToMemoryInfoKHR *pInfo) { - EVENT_RT_MARKER(CopyAccelerationStructureToMemoryKHR, commandBuffer, pInfo); + EVENT_RT_MARKER(CopyAccelerationStructureToMemoryKHR, 0, commandBuffer, pInfo); } VKAPI_ATTR void VKAPI_CALL sqtt_CmdCopyMemoryToAccelerationStructureKHR(VkCommandBuffer commandBuffer, const VkCopyMemoryToAccelerationStructureInfoKHR *pInfo) { - EVENT_RT_MARKER(CopyMemoryToAccelerationStructureKHR, commandBuffer, pInfo); + EVENT_RT_MARKER(CopyMemoryToAccelerationStructureKHR, 0, commandBuffer, pInfo); } VKAPI_ATTR void VKAPI_CALL diff --git a/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c b/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c index a5d91119b8d..210a1357f00 100644 --- a/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c +++ b/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c @@ -34,7 +34,7 @@ typedef struct { uint32_t address32_hi; bool disable_aniso_single_level; bool has_image_load_dcc_bug; - bool conformant_trunc_coord; + bool disable_tg4_trunc_coord; const struct radv_shader_args *args; const struct radv_shader_info *info; @@ -246,7 +246,7 @@ get_sampler_desc(nir_builder *b, apply_layout_state *state, nir_deref_instr *der } uint32_t dword0_mask = - tex->op == nir_texop_tg4 && !state->conformant_trunc_coord ? C_008F30_TRUNC_COORD : 0xffffffffu; + tex->op == nir_texop_tg4 && state->disable_tg4_trunc_coord ? C_008F30_TRUNC_COORD : 0xffffffffu; const uint32_t *samplers = radv_immutable_samplers(layout, binding); return nir_imm_ivec4(b, samplers[constant_index * 4 + 0] & dword0_mask, samplers[constant_index * 4 + 1], samplers[constant_index * 4 + 2], samplers[constant_index * 4 + 3]); @@ -330,7 +330,7 @@ get_sampler_desc(nir_builder *b, apply_layout_state *state, nir_deref_instr *der comp[6] = nir_iand_imm(b, comp[6], C_00A018_WRITE_COMPRESS_ENABLE); return nir_vec(b, comp, 8); - } else if (desc_type == AC_DESC_SAMPLER && tex->op == nir_texop_tg4 && !state->conformant_trunc_coord) { + } else if (desc_type == AC_DESC_SAMPLER && tex->op == nir_texop_tg4 && state->disable_tg4_trunc_coord) { nir_def *comp[4]; for (unsigned i = 0; i < 4; i++) comp[i] = nir_channel(b, desc, i); @@ -507,7 +507,8 @@ radv_nir_apply_pipeline_layout(nir_shader *shader, struct radv_device *device, c .address32_hi = device->physical_device->rad_info.address32_hi, .disable_aniso_single_level = device->instance->disable_aniso_single_level, .has_image_load_dcc_bug = device->physical_device->rad_info.has_image_load_dcc_bug, - .conformant_trunc_coord = device->physical_device->rad_info.conformant_trunc_coord, + .disable_tg4_trunc_coord = + !device->physical_device->rad_info.conformant_trunc_coord && !device->disable_trunc_coord, .args = args, .info = info, .layout = layout, diff --git a/src/amd/vulkan/nir/radv_nir_lower_cooperative_matrix.c b/src/amd/vulkan/nir/radv_nir_lower_cooperative_matrix.c index d81231b0137..e882100e141 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_cooperative_matrix.c +++ b/src/amd/vulkan/nir/radv_nir_lower_cooperative_matrix.c @@ -181,7 +181,7 @@ radv_nir_lower_cooperative_matrix(nir_shader *shader, unsigned wave_size) nir_def *elem = intr->src[1].ssa; nir_def *r = nir_vector_insert(&b, src1, elem, index); - nir_store_deref(&b, dst_deref, r, 0xffff); + nir_store_deref(&b, dst_deref, r, nir_component_mask(r->num_components)); nir_instr_remove(instr); progress = true; break; @@ -193,7 +193,7 @@ radv_nir_lower_cooperative_matrix(nir_shader *shader, unsigned wave_size) nir_def *r = nir_replicate(&b, elem, radv_nir_cmat_length(desc, wave_size)); - nir_store_deref(&b, dst_deref, r, 0xffff); + nir_store_deref(&b, dst_deref, r, nir_component_mask(r->num_components)); nir_instr_remove(instr); progress = true; break; @@ -253,7 +253,7 @@ radv_nir_lower_cooperative_matrix(nir_shader *shader, unsigned wave_size) } nir_def *mat = nir_vec(&b, vars, length); - nir_store_deref(&b, dst_deref, mat, 0xffff); + nir_store_deref(&b, dst_deref, mat, nir_component_mask(mat->num_components)); nir_instr_remove(instr); progress = true; break; @@ -332,7 +332,8 @@ radv_nir_lower_cooperative_matrix(nir_shader *shader, unsigned wave_size) ret = nir_cmat_muladd_amd(&b, A, B, C, .saturate = nir_intrinsic_saturate(intr), .cmat_signed_mask = nir_intrinsic_cmat_signed_mask(intr)); - nir_store_deref(&b, nir_instr_as_deref(intr->src[0].ssa->parent_instr), ret, 0xffff); + nir_store_deref(&b, nir_instr_as_deref(intr->src[0].ssa->parent_instr), ret, + nir_component_mask(ret->num_components)); nir_instr_remove(instr); progress = true; break; @@ -366,7 +367,7 @@ radv_nir_lower_cooperative_matrix(nir_shader *shader, unsigned wave_size) ret = nir_vec(&b, components, ret->num_components * 2); } - nir_store_deref(&b, dst_deref, ret, 0xffff); + nir_store_deref(&b, dst_deref, ret, nir_component_mask(ret->num_components)); nir_instr_remove(instr); progress = true; break; @@ -375,7 +376,8 @@ radv_nir_lower_cooperative_matrix(nir_shader *shader, unsigned wave_size) nir_def *src1 = radv_nir_load_cmat(&b, wave_size, intr->src[1].ssa); nir_op op = nir_intrinsic_alu_op(intr); nir_def *ret = nir_build_alu2(&b, op, src1, intr->src[2].ssa); - nir_store_deref(&b, nir_instr_as_deref(intr->src[0].ssa->parent_instr), ret, 0xffff); + nir_store_deref(&b, nir_instr_as_deref(intr->src[0].ssa->parent_instr), ret, + nir_component_mask(ret->num_components)); nir_instr_remove(instr); progress = true; break; @@ -385,14 +387,16 @@ radv_nir_lower_cooperative_matrix(nir_shader *shader, unsigned wave_size) nir_def *src2 = radv_nir_load_cmat(&b, wave_size, intr->src[2].ssa); nir_op op = nir_intrinsic_alu_op(intr); nir_def *ret = nir_build_alu2(&b, op, src1, src2); - nir_store_deref(&b, nir_instr_as_deref(intr->src[0].ssa->parent_instr), ret, 0xffff); + nir_store_deref(&b, nir_instr_as_deref(intr->src[0].ssa->parent_instr), ret, + nir_component_mask(ret->num_components)); nir_instr_remove(instr); progress = true; break; } case nir_intrinsic_cmat_bitcast: { nir_def *src1 = radv_nir_load_cmat(&b, wave_size, intr->src[1].ssa); - nir_store_deref(&b, nir_instr_as_deref(intr->src[0].ssa->parent_instr), src1, 0xffff); + nir_store_deref(&b, nir_instr_as_deref(intr->src[0].ssa->parent_instr), src1, + nir_component_mask(src1->num_components)); nir_instr_remove(instr); progress = true; break; diff --git a/src/amd/vulkan/nir/radv_nir_lower_io.c b/src/amd/vulkan/nir/radv_nir_lower_io.c index bc5ecfe41e9..e78523a7a49 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_io.c +++ b/src/amd/vulkan/nir/radv_nir_lower_io.c @@ -41,9 +41,6 @@ radv_nir_lower_io_to_scalar_early(nir_shader *nir, nir_variable_mode mask) { bool progress = false; - NIR_PASS(progress, nir, nir_lower_array_deref_of_vec, mask, - nir_lower_direct_array_deref_of_vec_load | nir_lower_indirect_array_deref_of_vec_load | - nir_lower_direct_array_deref_of_vec_store | nir_lower_indirect_array_deref_of_vec_store); NIR_PASS(progress, nir, nir_lower_io_to_scalar_early, mask); if (progress) { /* Optimize the new vector code and then remove dead vars */ diff --git a/src/amd/vulkan/radv_android.c b/src/amd/vulkan/radv_android.c index d440a0d9f1a..d4e3b89fe47 100644 --- a/src/amd/vulkan/radv_android.c +++ b/src/amd/vulkan/radv_android.c @@ -117,13 +117,6 @@ radv_image_from_gralloc(VkDevice device_h, const VkImageCreateInfo *base_info, struct radv_image *image = NULL; VkResult result; - if (gralloc_info->handle->numFds != 1) { - return vk_errorf(device, VK_ERROR_INVALID_EXTERNAL_HANDLE, - "VkNativeBufferANDROID::handle::numFds is %d, " - "expected 1", - gralloc_info->handle->numFds); - } - /* Do not close the gralloc handle's dma_buf. The lifetime of the dma_buf * must exceed that of the gralloc handle, and we do not own the gralloc * handle. diff --git a/src/amd/vulkan/radv_buffer.c b/src/amd/vulkan/radv_buffer.c index a42a61cac06..a9b38fdbfb9 100644 --- a/src/amd/vulkan/radv_buffer.c +++ b/src/amd/vulkan/radv_buffer.c @@ -90,6 +90,8 @@ radv_create_buffer(struct radv_device *device, const VkBufferCreateInfo *pCreate enum radeon_bo_flag flags = RADEON_FLAG_VIRTUAL; if (pCreateInfo->flags & VK_BUFFER_CREATE_DEVICE_ADDRESS_CAPTURE_REPLAY_BIT) flags |= RADEON_FLAG_REPLAYABLE; + if (pCreateInfo->usage & VK_BUFFER_USAGE_2_RESOURCE_DESCRIPTOR_BUFFER_BIT_EXT) + flags |= RADEON_FLAG_32BIT; uint64_t replay_address = 0; const VkBufferOpaqueCaptureAddressCreateInfo *replay_info = diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 7315cf12eb9..c4336345fb4 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -355,7 +355,7 @@ radv_create_cmd_buffer(struct vk_command_pool *pool, struct vk_command_buffer ** cmd_buffer->cs = device->ws->cs_create(device->ws, ring, cmd_buffer->vk.level == VK_COMMAND_BUFFER_LEVEL_SECONDARY); if (!cmd_buffer->cs) { radv_destroy_cmd_buffer(&cmd_buffer->vk); - return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY); + return vk_error(device, VK_ERROR_OUT_OF_DEVICE_MEMORY); } vk_object_base_init(&device->vk, &cmd_buffer->meta_push_descriptors.base, VK_OBJECT_TYPE_DESCRIPTOR_SET); @@ -698,7 +698,7 @@ radv_gang_init(struct radv_cmd_buffer *cmd_buffer) device->ws->cs_create(device->ws, AMD_IP_COMPUTE, cmd_buffer->vk.level == VK_COMMAND_BUFFER_LEVEL_SECONDARY); if (!ace_cs) { - vk_command_buffer_set_error(&cmd_buffer->vk, VK_ERROR_OUT_OF_HOST_MEMORY); + vk_command_buffer_set_error(&cmd_buffer->vk, VK_ERROR_OUT_OF_DEVICE_MEMORY); return false; } @@ -2271,17 +2271,19 @@ radv_emit_primitive_topology(struct radv_cmd_buffer *cmd_buffer) static void radv_emit_depth_control(struct radv_cmd_buffer *cmd_buffer) { + const struct radv_rendering_state *render = &cmd_buffer->state.render; struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; + const bool stencil_test_enable = + d->vk.ds.stencil.test_enable && (render->ds_att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT); - radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, - S_028800_Z_ENABLE(d->vk.ds.depth.test_enable ? 1 : 0) | - S_028800_Z_WRITE_ENABLE(d->vk.ds.depth.write_enable ? 1 : 0) | - S_028800_ZFUNC(d->vk.ds.depth.compare_op) | - S_028800_DEPTH_BOUNDS_ENABLE(d->vk.ds.depth.bounds_test.enable ? 1 : 0) | - S_028800_STENCIL_ENABLE(d->vk.ds.stencil.test_enable ? 1 : 0) | - S_028800_BACKFACE_ENABLE(d->vk.ds.stencil.test_enable ? 1 : 0) | - S_028800_STENCILFUNC(d->vk.ds.stencil.front.op.compare) | - S_028800_STENCILFUNC_BF(d->vk.ds.stencil.back.op.compare)); + radeon_set_context_reg( + cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, + S_028800_Z_ENABLE(d->vk.ds.depth.test_enable ? 1 : 0) | + S_028800_Z_WRITE_ENABLE(d->vk.ds.depth.write_enable ? 1 : 0) | S_028800_ZFUNC(d->vk.ds.depth.compare_op) | + S_028800_DEPTH_BOUNDS_ENABLE(d->vk.ds.depth.bounds_test.enable ? 1 : 0) | + S_028800_STENCIL_ENABLE(stencil_test_enable) | S_028800_BACKFACE_ENABLE(stencil_test_enable) | + S_028800_STENCILFUNC(d->vk.ds.stencil.front.op.compare) | + S_028800_STENCILFUNC_BF(d->vk.ds.stencil.back.op.compare)); } static void @@ -5861,6 +5863,11 @@ radv_BeginCommandBuffer(VkCommandBuffer commandBuffer, const VkCommandBufferBegi render->ds_att.format = inheritance_info->depthAttachmentFormat; if (inheritance_info->stencilAttachmentFormat != VK_FORMAT_UNDEFINED) render->ds_att.format = inheritance_info->stencilAttachmentFormat; + + if (vk_format_has_depth(render->ds_att.format)) + render->ds_att_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT; + if (vk_format_has_stencil(render->ds_att.format)) + render->ds_att_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT; } cmd_buffer->state.inherited_pipeline_statistics = pBeginInfo->pInheritanceInfo->pipelineStatistics; @@ -6618,6 +6625,11 @@ radv_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipeline case VK_PIPELINE_BIND_POINT_GRAPHICS: { struct radv_graphics_pipeline *graphics_pipeline = radv_pipeline_to_graphics(pipeline); + /* Bind the non-dynamic graphics state from the pipeline unconditionally because some PSO + * might have been overwritten between two binds of the same pipeline. + */ + radv_bind_dynamic_state(cmd_buffer, &graphics_pipeline->dynamic_state); + if (cmd_buffer->state.graphics_pipeline == graphics_pipeline) return; radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint); @@ -6686,8 +6698,6 @@ radv_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipeline cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RBPLUS; } - radv_bind_dynamic_state(cmd_buffer, &graphics_pipeline->dynamic_state); - radv_bind_vs_input_state(cmd_buffer, graphics_pipeline); radv_bind_multisample_state(cmd_buffer, &graphics_pipeline->ms); @@ -7713,6 +7723,7 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe } struct radv_attachment ds_att = {.iview = NULL}; + VkImageAspectFlags ds_att_aspects = 0; const VkRenderingAttachmentInfo *d_att_info = pRenderingInfo->pDepthAttachment; const VkRenderingAttachmentInfo *s_att_info = pRenderingInfo->pStencilAttachment; if ((d_att_info != NULL && d_att_info->imageView != VK_NULL_HANDLE) || @@ -7748,7 +7759,16 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe assert(d_iview == NULL || s_iview == NULL || d_iview == s_iview); ds_att.iview = d_iview ? d_iview : s_iview, ds_att.format = ds_att.iview->vk.format; - radv_initialise_ds_surface(cmd_buffer->device, &ds_att.ds, ds_att.iview); + + if (d_iview && s_iview) { + ds_att_aspects = VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT; + } else if (d_iview) { + ds_att_aspects = VK_IMAGE_ASPECT_DEPTH_BIT; + } else { + ds_att_aspects = VK_IMAGE_ASPECT_STENCIL_BIT; + } + + radv_initialise_ds_surface(cmd_buffer->device, &ds_att.ds, ds_att.iview, ds_att_aspects); assert(d_res_iview == NULL || s_res_iview == NULL || d_res_iview == s_res_iview); ds_att.resolve_iview = d_res_iview ? d_res_iview : s_res_iview; @@ -7797,6 +7817,7 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe render->color_att_count = pRenderingInfo->colorAttachmentCount; typed_memcpy(render->color_att, color_att, render->color_att_count); render->ds_att = ds_att; + render->ds_att_aspects = ds_att_aspects; render->vrs_att = vrs_att; render->vrs_texel_size = vrs_texel_size; cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER; @@ -7804,7 +7825,7 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe if (cmd_buffer->device->physical_device->rad_info.rbplus_allowed) cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RBPLUS; - cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS; + cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE; if (render->vrs_att.iview && cmd_buffer->device->physical_device->rad_info.gfx_level == GFX10_3) { if (render->ds_att.iview) { @@ -9707,11 +9728,11 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer, const struct radv radeon_emit(cs, dispatch_initiator); } } else { + const unsigned *cs_block_size = compute_shader->info.cs.block_size; unsigned blocks[3] = {info->blocks[0], info->blocks[1], info->blocks[2]}; unsigned offsets[3] = {info->offsets[0], info->offsets[1], info->offsets[2]}; if (info->unaligned) { - const unsigned *cs_block_size = compute_shader->info.cs.block_size; unsigned remainder[3]; /* If aligned, these should be an entire block size, @@ -9776,6 +9797,21 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer, const struct radv predicating = false; } + if (cmd_buffer->device->physical_device->rad_info.has_async_compute_threadgroup_bug && + cmd_buffer->qf == RADV_QUEUE_COMPUTE) { + for (unsigned i = 0; i < 3; i++) { + if (info->unaligned) { + /* info->blocks is already in thread dimensions for unaligned dispatches. */ + blocks[i] = info->blocks[i]; + } else { + /* Force the async compute dispatch to be in "thread" dim mode to workaround a hw bug. */ + blocks[i] *= cs_block_size[i]; + } + + dispatch_initiator |= S_00B800_USE_THREAD_DIMENSIONS(1); + } + } + radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) | PKT3_SHADER_TYPE_S(1)); radeon_emit(cs, blocks[0]); radeon_emit(cs, blocks[1]); @@ -9873,6 +9909,7 @@ radv_dgc_before_dispatch(struct radv_cmd_buffer *cmd_buffer) { struct radv_compute_pipeline *pipeline = cmd_buffer->state.compute_pipeline; struct radv_shader *compute_shader = cmd_buffer->state.shaders[MESA_SHADER_COMPUTE]; + bool pipeline_is_dirty = pipeline != cmd_buffer->state.emitted_compute_pipeline; /* We will have run the DGC patch shaders before, so we can assume that there is something to * flush. Otherwise, we just split radv_dispatch in two. One pre-dispatch and another one @@ -9885,6 +9922,17 @@ radv_dgc_before_dispatch(struct radv_cmd_buffer *cmd_buffer) si_emit_cache_flush(cmd_buffer); radv_upload_compute_shader_descriptors(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE); + + if (pipeline_is_dirty) { + /* Raytracing uses compute shaders but has separate bind points and pipelines. + * So if we set compute userdata & shader registers we should dirty the raytracing + * ones and the other way around. + * + * We only need to do this when the pipeline is dirty because when we switch between + * the two we always need to switch pipelines. + */ + radv_mark_descriptor_sets_dirty(cmd_buffer, VK_PIPELINE_BIND_POINT_RAY_TRACING_KHR); + } } static void @@ -9899,17 +9947,6 @@ radv_dgc_after_dispatch(struct radv_cmd_buffer *cmd_buffer) radv_emit_shader_prefetch(cmd_buffer, compute_shader); } - if (pipeline_is_dirty) { - /* Raytracing uses compute shaders but has separate bind points and pipelines. - * So if we set compute userdata & shader registers we should dirty the raytracing - * ones and the other way around. - * - * We only need to do this when the pipeline is dirty because when we switch between - * the two we always need to switch pipelines. - */ - radv_mark_descriptor_sets_dirty(cmd_buffer, VK_PIPELINE_BIND_POINT_RAY_TRACING_KHR); - } - if (compute_shader->info.cs.regalloc_hang_bug) cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH; @@ -10573,7 +10610,10 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer, const VkDependencyInfo *dep_inf } radv_gang_barrier(cmd_buffer, 0, dst_stage_mask); - radv_cp_dma_wait_for_stages(cmd_buffer, src_stage_mask); + + const bool is_gfx_or_ace = cmd_buffer->qf == RADV_QUEUE_GENERAL || cmd_buffer->qf == RADV_QUEUE_COMPUTE; + if (is_gfx_or_ace) + radv_cp_dma_wait_for_stages(cmd_buffer, src_stage_mask); cmd_buffer->state.flush_bits |= dst_flush_bits; diff --git a/src/amd/vulkan/radv_cp_reg_shadowing.c b/src/amd/vulkan/radv_cp_reg_shadowing.c index 9f19c68fec9..f846bf51b33 100644 --- a/src/amd/vulkan/radv_cp_reg_shadowing.c +++ b/src/amd/vulkan/radv_cp_reg_shadowing.c @@ -44,7 +44,7 @@ radv_create_shadow_regs_preamble(const struct radv_device *device, struct radv_q struct radeon_cmdbuf *cs = ws->cs_create(ws, AMD_IP_GFX, false); if (!cs) - return VK_ERROR_OUT_OF_HOST_MEMORY; + return VK_ERROR_OUT_OF_DEVICE_MEMORY; radeon_check_space(ws, cs, 256); @@ -131,7 +131,7 @@ radv_init_shadowed_regs_buffer_state(const struct radv_device *device, struct ra cs = ws->cs_create(ws, AMD_IP_GFX, false); if (!cs) - return VK_ERROR_OUT_OF_HOST_MEMORY; + return VK_ERROR_OUT_OF_DEVICE_MEMORY; radeon_check_space(ws, cs, 768); diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h index fb18bf0c8cb..91174c0323e 100644 --- a/src/amd/vulkan/radv_debug.h +++ b/src/amd/vulkan/radv_debug.h @@ -88,6 +88,7 @@ enum { RADV_PERFTEST_NGG_STREAMOUT = 1u << 11, RADV_PERFTEST_VIDEO_DECODE = 1u << 12, RADV_PERFTEST_DMA_SHADERS = 1u << 13, + RADV_PERFTEST_GS_FAST_LAUNCH_2 = 1u << 14, }; bool radv_init_trace(struct radv_device *device); diff --git a/src/amd/vulkan/radv_descriptor_set.c b/src/amd/vulkan/radv_descriptor_set.c index 979ea00ab69..602a9952d4b 100644 --- a/src/amd/vulkan/radv_descriptor_set.c +++ b/src/amd/vulkan/radv_descriptor_set.c @@ -691,7 +691,7 @@ radv_descriptor_set_create(struct radv_device *device, struct radv_descriptor_po pool->entries[pool->entry_count].size = layout_size; pool->entries[pool->entry_count].set = set; } else { - pool->layouts[pool->entry_count] = layout; + pool->sets[pool->entry_count] = set; } pool->current_offset += layout_size; @@ -775,7 +775,8 @@ radv_destroy_descriptor_pool(struct radv_device *device, const VkAllocationCallb } } else { for (uint32_t i = 0; i < pool->entry_count; ++i) { - vk_descriptor_set_layout_unref(&device->vk, &pool->layouts[i]->vk); + vk_descriptor_set_layout_unref(&device->vk, &pool->sets[i]->header.layout->vk); + vk_object_base_finish(&pool->sets[i]->header.base); } } @@ -881,15 +882,15 @@ radv_create_descriptor_pool(struct radv_device *device, const VkDescriptorPoolCr bo_size += 16 * MIN2(num_16byte_descriptors, pCreateInfo->maxSets); } - uint64_t layouts_size = 0; + uint64_t sets_size = 0; if (!(pCreateInfo->flags & VK_DESCRIPTOR_POOL_CREATE_FREE_DESCRIPTOR_SET_BIT)) { size += pCreateInfo->maxSets * sizeof(struct radv_descriptor_set); size += sizeof(struct radeon_winsys_bo *) * bo_count; size += sizeof(struct radv_descriptor_range) * range_count; - layouts_size = sizeof(struct radv_descriptor_set_layout *) * pCreateInfo->maxSets; - size += layouts_size; + sets_size = sizeof(struct radv_descriptor_set *) * pCreateInfo->maxSets; + size += sets_size; } else { size += sizeof(struct radv_descriptor_pool_entry) * pCreateInfo->maxSets; } @@ -903,7 +904,7 @@ radv_create_descriptor_pool(struct radv_device *device, const VkDescriptorPoolCr vk_object_base_init(&device->vk, &pool->base, VK_OBJECT_TYPE_DESCRIPTOR_POOL); if (!(pCreateInfo->flags & VK_DESCRIPTOR_POOL_CREATE_FREE_DESCRIPTOR_SET_BIT)) { - pool->host_memory_base = (uint8_t *)pool + sizeof(struct radv_descriptor_pool) + layouts_size; + pool->host_memory_base = (uint8_t *)pool + sizeof(struct radv_descriptor_pool) + sets_size; pool->host_memory_ptr = pool->host_memory_base; pool->host_memory_end = (uint8_t *)pool + size; } @@ -975,7 +976,8 @@ radv_ResetDescriptorPool(VkDevice _device, VkDescriptorPool descriptorPool, VkDe } } else { for (uint32_t i = 0; i < pool->entry_count; ++i) { - vk_descriptor_set_layout_unref(&device->vk, &pool->layouts[i]->vk); + vk_descriptor_set_layout_unref(&device->vk, &pool->sets[i]->header.layout->vk); + vk_object_base_finish(&pool->sets[i]->header.base); } } @@ -1095,7 +1097,11 @@ write_buffer_descriptor(struct radv_device *device, unsigned *dst, uint64_t va, dst[0] = va; dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32); - dst[2] = range; + /* robustBufferAccess is relaxed enough to allow this (in combination with the alignment/size + * we return from vkGetBufferMemoryRequirements) and this allows the shader compiler to create + * more efficient 8/16-bit buffer accesses. + */ + dst[2] = align(range, 4); dst[3] = rsrc_word3; } @@ -1111,12 +1117,6 @@ write_buffer_descriptor_impl(struct radv_device *device, struct radv_cmd_buffer range = vk_buffer_range(&buffer->vk, buffer_info->offset, buffer_info->range); assert(buffer->vk.size > 0 && range > 0); - - /* robustBufferAccess is relaxed enough to allow this (in combination with the alignment/size - * we return from vkGetBufferMemoryRequirements) and this allows the shader compiler to create - * more efficient 8/16-bit buffer accesses. - */ - range = align(range, 4); } write_buffer_descriptor(device, dst, va, range); diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 4aa4b930c82..247192d8a38 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -707,11 +707,13 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr bool use_dgc = false; bool smooth_lines = false; bool mesh_shader_queries = false; + bool dual_src_blend = false; /* Check enabled features */ if (pCreateInfo->pEnabledFeatures) { if (pCreateInfo->pEnabledFeatures->robustBufferAccess) buffer_robustness = MAX2(buffer_robustness, RADV_BUFFER_ROBUSTNESS_1); + dual_src_blend = pCreateInfo->pEnabledFeatures->dualSrcBlend; } vk_foreach_struct_const (ext, pCreateInfo->pNext) { @@ -720,6 +722,7 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr const VkPhysicalDeviceFeatures2 *features = (const void *)ext; if (features->features.robustBufferAccess) buffer_robustness = MAX2(buffer_robustness, RADV_BUFFER_ROBUSTNESS_1); + dual_src_blend |= features->features.dualSrcBlend; break; } case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: { @@ -940,7 +943,8 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr device->pbb_allowed = device->physical_device->rad_info.gfx_level >= GFX9 && !(device->instance->debug_flags & RADV_DEBUG_NOBINNING); - device->mesh_fast_launch_2 = device->physical_device->rad_info.gfx_level >= GFX11; + device->mesh_fast_launch_2 = (device->instance->perftest_flags & RADV_PERFTEST_GS_FAST_LAUNCH_2) && + device->physical_device->rad_info.gfx_level >= GFX11; /* The maximum number of scratch waves. Scratch space isn't divided * evenly between CUs. The number is only a function of the number of CUs. @@ -1124,6 +1128,17 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n", 1 << util_logbase2(device->force_aniso)); } + device->disable_trunc_coord = device->instance->disable_trunc_coord; + + if (device->instance->vk.app_info.engine_name && !strcmp(device->instance->vk.app_info.engine_name, "DXVK")) { + /* For DXVK 2.3.0 and older, use dualSrcBlend to determine if this is D3D9. */ + bool is_d3d9 = !dual_src_blend; + if (device->instance->vk.app_info.engine_version > VK_MAKE_VERSION(2, 3, 0)) + is_d3d9 = device->instance->vk.app_info.app_version & 0x1; + + device->disable_trunc_coord &= !is_d3d9; + } + if (use_perf_counters) { size_t bo_size = PERF_CTR_BO_PASS_OFFSET + sizeof(uint64_t) * PERF_CTR_MAX_PASSES; result = device->ws->buffer_create(device->ws, bo_size, 4096, RADEON_DOMAIN_GTT, @@ -1827,7 +1842,7 @@ radv_initialise_vrs_surface(struct radv_image *image, struct radv_buffer *htile_ void radv_initialise_ds_surface(const struct radv_device *device, struct radv_ds_buffer_info *ds, - struct radv_image_view *iview) + struct radv_image_view *iview, VkImageAspectFlags ds_aspects) { unsigned level = iview->vk.base_mip_level; unsigned format, stencil_format; @@ -1844,7 +1859,9 @@ radv_initialise_ds_surface(const struct radv_device *device, struct radv_ds_buff stencil_format = surf->has_stencil ? V_028044_STENCIL_8 : V_028044_STENCIL_INVALID; uint32_t max_slice = radv_surface_max_layer_count(iview) - 1; - ds->db_depth_view = S_028008_SLICE_START(iview->vk.base_array_layer) | S_028008_SLICE_MAX(max_slice); + ds->db_depth_view = S_028008_SLICE_START(iview->vk.base_array_layer) | S_028008_SLICE_MAX(max_slice) | + S_028008_Z_READ_ONLY(!(ds_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) | + S_028008_STENCIL_READ_ONLY(!(ds_aspects & VK_IMAGE_ASPECT_STENCIL_BIT)); if (device->physical_device->rad_info.gfx_level >= GFX10) { ds->db_depth_view |= S_028008_SLICE_START_HI(iview->vk.base_array_layer >> 11) | S_028008_SLICE_MAX_HI(max_slice >> 11); @@ -2018,8 +2035,7 @@ radv_gfx11_set_db_render_control(const struct radv_device *device, unsigned num_ max_allowed_tiles_in_wave = 15; } - *db_render_control |= - S_028000_OREO_MODE(V_028000_OMODE_O_THEN_B) | S_028000_MAX_ALLOWED_TILES_IN_WAVE(max_allowed_tiles_in_wave); + *db_render_control |= S_028000_MAX_ALLOWED_TILES_IN_WAVE(max_allowed_tiles_in_wave); } VKAPI_ATTR VkResult VKAPI_CALL diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c index 3230862878a..9195dc90880 100644 --- a/src/amd/vulkan/radv_formats.c +++ b/src/amd/vulkan/radv_formats.c @@ -1695,7 +1695,7 @@ radv_GetPhysicalDeviceImageFormatProperties2(VkPhysicalDevice physicalDevice, } if (ycbcr_props) { - ycbcr_props->combinedImageSamplerDescriptorCount = vk_format_get_plane_count(format); + ycbcr_props->combinedImageSamplerDescriptorCount = 1; } if (texture_lod_props) { diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 2ea37d3f4f8..10edc11129c 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -75,6 +75,13 @@ radv_use_tc_compat_htile_for_image(struct radv_device *device, const VkImageCrea if (device->physical_device->rad_info.gfx_level < GFX8) return false; + /* TC-compat HTILE looks broken on Tonga (and Iceland is the same design) and the documented bug + * workarounds don't help. + */ + if (device->physical_device->rad_info.family == CHIP_TONGA || + device->physical_device->rad_info.family == CHIP_ICELAND) + return false; + if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) return false; @@ -2225,7 +2232,8 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device, * block compatible format and the compressed format, so even if we take * the plain converted dimensions the physical layout is correct. */ - if (device->physical_device->rad_info.gfx_level >= GFX9 && vk_format_is_block_compressed(image->vk.format) && + if (device->physical_device->rad_info.gfx_level >= GFX9 && + vk_format_is_block_compressed(image->planes[iview->plane_id].format) && !vk_format_is_block_compressed(iview->vk.format)) { /* If we have multiple levels in the view we should ideally take the last level, * but the mip calculation has a max(..., 1) so walking back to the base mip in an diff --git a/src/amd/vulkan/radv_instance.c b/src/amd/vulkan/radv_instance.c index 03d647ad5a5..14032b93a19 100644 --- a/src/amd/vulkan/radv_instance.c +++ b/src/amd/vulkan/radv_instance.c @@ -99,6 +99,7 @@ static const struct debug_control radv_perftest_options[] = {{"localbos", RADV_P {"ngg_streamout", RADV_PERFTEST_NGG_STREAMOUT}, {"video_decode", RADV_PERFTEST_VIDEO_DECODE}, {"dmashaders", RADV_PERFTEST_DMA_SHADERS}, + {"gsfastlaunch2", RADV_PERFTEST_GS_FAST_LAUNCH_2}, {NULL, 0}}; const char * @@ -143,6 +144,7 @@ static const driOptionDescription radv_dri_options[] = { DRI_CONF_RADV_DISABLE_TC_COMPAT_HTILE_GENERAL(false) DRI_CONF_RADV_DISABLE_DCC(false) DRI_CONF_RADV_DISABLE_ANISO_SINGLE_LEVEL(false) + DRI_CONF_RADV_DISABLE_TRUNC_COORD(false) DRI_CONF_RADV_DISABLE_SINKING_LOAD_INPUT_FS(false) DRI_CONF_RADV_DGC(false) DRI_CONF_RADV_FLUSH_BEFORE_QUERY_COPY(false) @@ -151,6 +153,7 @@ static const driOptionDescription radv_dri_options[] = { DRI_CONF_RADV_FLUSH_BEFORE_TIMESTAMP_WRITE(false) DRI_CONF_RADV_RT_WAVE64(false) DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION(false) + DRI_CONF_RADV_SSBO_NON_UNIFORM(false) DRI_CONF_RADV_APP_LAYER() DRI_CONF_SECTION_END }; @@ -190,6 +193,8 @@ radv_init_dri_options(struct radv_instance *instance) instance->disable_aniso_single_level = driQueryOptionb(&instance->dri_options, "radv_disable_aniso_single_level"); + instance->disable_trunc_coord = driQueryOptionb(&instance->dri_options, "radv_disable_trunc_coord"); + instance->disable_sinking_load_input_fs = driQueryOptionb(&instance->dri_options, "radv_disable_sinking_load_input_fs"); @@ -199,6 +204,8 @@ radv_init_dri_options(struct radv_instance *instance) instance->tex_non_uniform = driQueryOptionb(&instance->dri_options, "radv_tex_non_uniform"); + instance->ssbo_non_uniform = driQueryOptionb(&instance->dri_options, "radv_ssbo_non_uniform"); + instance->app_layer = driQueryOptionstr(&instance->dri_options, "radv_app_layer"); instance->flush_before_timestamp_write = diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index d18f5b04875..26303796128 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -157,9 +157,12 @@ radv_generate_pipeline_key(const struct radv_device *device, const VkPipelineSha key.disable_aniso_single_level = device->instance->disable_aniso_single_level && device->physical_device->rad_info.gfx_level < GFX8; + key.disable_trunc_coord = device->disable_trunc_coord; + key.image_2d_view_of_3d = device->image_2d_view_of_3d && device->physical_device->rad_info.gfx_level == GFX9; key.tex_non_uniform = device->instance->tex_non_uniform; + key.ssbo_non_uniform = device->instance->ssbo_non_uniform; for (unsigned i = 0; i < num_stages; ++i) { const VkPipelineShaderStageCreateInfo *const stage = &stages[i]; @@ -214,6 +217,11 @@ radv_generate_pipeline_key(const struct radv_device *device, const VkPipelineSha key.vertex_robustness1 = 1u; } + for (uint32_t i = 0; i < num_stages; i++) { + if (stages[i].stage == VK_SHADER_STAGE_MESH_BIT_EXT && device->mesh_fast_launch_2) + key.mesh_fast_launch_2 = 1u; + } + return key; } @@ -617,7 +625,8 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_key NIR_PASS(_, stage->nir, ac_nir_lower_tex, &(ac_nir_lower_tex_options){ .gfx_level = gfx_level, - .lower_array_layer_round_even = !device->physical_device->rad_info.conformant_trunc_coord, + .lower_array_layer_round_even = + !device->physical_device->rad_info.conformant_trunc_coord || device->disable_trunc_coord, .fix_derivs_in_divergent_cf = fix_derivs_in_divergent_cf, .max_wqm_vgprs = 64, // TODO: improve spiller and RA support for linear VGPRs }); diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index d02c53f778c..72ed9697f13 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -1338,6 +1338,13 @@ radv_link_shaders(const struct radv_device *device, nir_shader *producer, nir_sh nir_link_xfb_varyings(producer, consumer); } + unsigned array_deref_of_vec_options = + nir_lower_direct_array_deref_of_vec_load | nir_lower_indirect_array_deref_of_vec_load | + nir_lower_direct_array_deref_of_vec_store | nir_lower_indirect_array_deref_of_vec_store; + + NIR_PASS(progress, producer, nir_lower_array_deref_of_vec, nir_var_shader_out, array_deref_of_vec_options); + NIR_PASS(progress, consumer, nir_lower_array_deref_of_vec, nir_var_shader_in, array_deref_of_vec_options); + nir_lower_io_arrays_to_elements(producer, consumer); nir_validate_shader(producer, "after nir_lower_io_arrays_to_elements"); nir_validate_shader(consumer, "after nir_lower_io_arrays_to_elements"); @@ -1620,6 +1627,12 @@ radv_pipeline_needs_noop_fs(struct radv_graphics_pipeline *pipeline, const struc static void radv_remove_varyings(nir_shader *nir) { + /* We can't demote mesh outputs to nir_var_shader_temp yet, because + * they don't support array derefs of vectors. + */ + if (nir->info.stage == MESA_SHADER_MESH) + return; + bool fixup_derefs = false; nir_foreach_shader_out_variable (var, nir) { diff --git a/src/amd/vulkan/radv_pipeline_rt.c b/src/amd/vulkan/radv_pipeline_rt.c index 810f6041b1d..c61d2becf47 100644 --- a/src/amd/vulkan/radv_pipeline_rt.c +++ b/src/amd/vulkan/radv_pipeline_rt.c @@ -609,6 +609,7 @@ radv_rt_compile_shaders(struct radv_device *device, struct vk_pipeline_cache *ca radv_shader_layout_init(pipeline_layout, MESA_SHADER_INTERSECTION, &traversal_stage.layout); result = radv_rt_nir_to_asm(device, cache, pCreateInfo, key, pipeline, false, &traversal_stage, NULL, NULL, &pipeline->base.base.shaders[MESA_SHADER_INTERSECTION]); + ralloc_free(traversal_module.nir); cleanup: for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 5eb9102f8c0..43a2bb7e6c1 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -410,11 +410,13 @@ struct radv_instance { bool disable_tc_compat_htile_in_general; bool disable_shrink_image_store; bool disable_aniso_single_level; + bool disable_trunc_coord; bool zero_vram; bool disable_sinking_load_input_fs; bool flush_before_query_copy; bool enable_unified_heap_on_apu; bool tex_non_uniform; + bool ssbo_non_uniform; bool flush_before_timestamp_write; bool force_rt_wave64; bool dual_color_blend_by_location; @@ -1042,6 +1044,9 @@ struct radv_device { /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */ int force_aniso; + /* Always disable TRUNC_COORD. */ + bool disable_trunc_coord; + struct radv_device_border_color_data border_color_data; /* Thread trace. */ @@ -1201,7 +1206,7 @@ struct radv_descriptor_pool { uint32_t max_entry_count; union { - struct radv_descriptor_set_layout *layouts[0]; + struct radv_descriptor_set *sets[0]; struct radv_descriptor_pool_entry entries[0]; }; }; @@ -1522,7 +1527,7 @@ struct radv_ds_buffer_info { void radv_initialise_color_surface(struct radv_device *device, struct radv_color_buffer_info *cb, struct radv_image_view *iview); void radv_initialise_ds_surface(const struct radv_device *device, struct radv_ds_buffer_info *ds, - struct radv_image_view *iview); + struct radv_image_view *iview, VkImageAspectFlags ds_aspects); void radv_initialise_vrs_surface(struct radv_image *image, struct radv_buffer *htile_buffer, struct radv_ds_buffer_info *ds); @@ -1564,6 +1569,7 @@ struct radv_rendering_state { uint32_t color_att_count; struct radv_attachment color_att[MAX_RTS]; struct radv_attachment ds_att; + VkImageAspectFlags ds_att_aspects; struct radv_attachment vrs_att; VkExtent2D vrs_texel_size; }; diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index 6596e93199b..02339b508be 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -584,7 +584,7 @@ build_timestamp_query_shader(struct radv_device *device) } #define RADV_PGQ_STRIDE 32 -#define RADV_PGQ_STRIDE_GDS (RADV_PGQ_STRIDE + 4 * 2) +#define RADV_PGQ_STRIDE_GDS (RADV_PGQ_STRIDE + 8 * 2) static nir_shader * build_pg_query_shader(struct radv_device *device) @@ -663,11 +663,21 @@ build_pg_query_shader(struct radv_device *device) nir_def *avails[2]; avails[0] = nir_channel(&b, load1, 1); avails[1] = nir_channel(&b, load2, 1); - nir_def *result_is_available = - nir_i2b(&b, nir_iand(&b, nir_iand(&b, avails[0], avails[1]), nir_imm_int(&b, 0x80000000))); + nir_store_var(&b, available, nir_i2b(&b, nir_iand_imm(&b, nir_iand(&b, avails[0], avails[1]), 0x80000000)), 0x1); + + nir_push_if(&b, uses_gds); + { + nir_def *gds_avail_start = nir_load_ssbo(&b, 1, 32, src_buf, nir_iadd_imm(&b, input_base, 36), .align_mul = 4); + nir_def *gds_avail_end = nir_load_ssbo(&b, 1, 32, src_buf, nir_iadd_imm(&b, input_base, 44), .align_mul = 4); + nir_def *gds_result_available = + nir_i2b(&b, nir_iand_imm(&b, nir_iand(&b, gds_avail_start, gds_avail_end), 0x80000000)); + + nir_store_var(&b, available, nir_iand(&b, nir_load_var(&b, available), gds_result_available), 0x1); + } + nir_pop_if(&b, NULL); /* Only compute result if available. */ - nir_push_if(&b, result_is_available); + nir_push_if(&b, nir_load_var(&b, available)); /* Pack values. */ nir_def *packed64[2]; @@ -684,7 +694,7 @@ build_pg_query_shader(struct radv_device *device) nir_def *gds_start = nir_load_ssbo(&b, 1, 32, src_buf, nir_iadd(&b, input_base, nir_imm_int(&b, 32)), .align_mul = 4); nir_def *gds_end = - nir_load_ssbo(&b, 1, 32, src_buf, nir_iadd(&b, input_base, nir_imm_int(&b, 36)), .align_mul = 4); + nir_load_ssbo(&b, 1, 32, src_buf, nir_iadd(&b, input_base, nir_imm_int(&b, 40)), .align_mul = 4); nir_def *ngg_gds_result = nir_isub(&b, gds_end, gds_start); @@ -692,8 +702,6 @@ build_pg_query_shader(struct radv_device *device) } nir_pop_if(&b, NULL); - nir_store_var(&b, available, nir_imm_true(&b), 0x1); - nir_pop_if(&b, NULL); /* Determine if result is 64 or 32 bit. */ @@ -1087,7 +1095,7 @@ radv_create_query_pool(struct radv_device *device, const VkQueryPoolCreateInfo * case VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT: if (pool->uses_gds && device->physical_device->rad_info.gfx_level < GFX11) { /* When the hardware can use both the legacy and the NGG paths in the same begin/end pair, - * allocate 2x32-bit values for the GDS counters. + * allocate 2x64-bit values for the GDS counters. */ pool->stride = RADV_PGQ_STRIDE_GDS; } else { @@ -1318,6 +1326,7 @@ radv_GetQueryPoolResults(VkDevice _device, VkQueryPool queryPool, uint32_t first break; } case VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT: { + const bool uses_gds_query = pool->uses_gds && device->physical_device->rad_info.gfx_level < GFX11; p_atomic_uint64_t const *src64 = (p_atomic_uint64_t const *)src; uint64_t primitive_storage_needed; @@ -1333,6 +1342,10 @@ radv_GetQueryPoolResults(VkDevice _device, VkQueryPool queryPool, uint32_t first !(p_atomic_read(src64 + 2) & 0x8000000000000000UL)) { available = 0; } + if (uses_gds_query && (!(p_atomic_read(src64 + 4) & 0x8000000000000000UL) || + !(p_atomic_read(src64 + 5) & 0x8000000000000000UL))) { + available = 0; + } } while (!available && (flags & VK_QUERY_RESULT_WAIT_BIT)); if (!available && !(flags & VK_QUERY_RESULT_PARTIAL_BIT)) @@ -1340,11 +1353,9 @@ radv_GetQueryPoolResults(VkDevice _device, VkQueryPool queryPool, uint32_t first primitive_storage_needed = src64[2] - src64[0]; - if (pool->uses_gds && device->physical_device->rad_info.gfx_level < GFX11) { - uint32_t const *src32 = (uint32_t const *)src; - + if (uses_gds_query) { /* Accumulate the result that was copied from GDS in case NGG shader has been used. */ - primitive_storage_needed += src32[9] - src32[8]; + primitive_storage_needed += src64[5] - src64[4]; } if (flags & VK_QUERY_RESULT_64_BIT) { @@ -1539,15 +1550,22 @@ radv_CmdCopyQueryPoolResults(VkCommandBuffer commandBuffer, VkQueryPool queryPoo break; case VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT: if (flags & VK_QUERY_RESULT_WAIT_BIT) { + const bool uses_gds_query = pool->uses_gds && cmd_buffer->device->physical_device->rad_info.gfx_level < GFX11; + for (unsigned i = 0; i < queryCount; i++) { unsigned query = firstQuery + i; uint64_t src_va = va + query * pool->stride; - radeon_check_space(cmd_buffer->device->ws, cs, 7 * 2); + radeon_check_space(cmd_buffer->device->ws, cs, 7 * 4); /* Wait on the upper word of the PrimitiveStorageNeeded result. */ radv_cp_wait_mem(cs, cmd_buffer->qf, WAIT_REG_MEM_GREATER_OR_EQUAL, src_va + 4, 0x80000000, 0xffffffff); radv_cp_wait_mem(cs, cmd_buffer->qf, WAIT_REG_MEM_GREATER_OR_EQUAL, src_va + 20, 0x80000000, 0xffffffff); + + if (uses_gds_query) { + radv_cp_wait_mem(cs, cmd_buffer->qf, WAIT_REG_MEM_GREATER_OR_EQUAL, src_va + 36, 0x80000000, 0xffffffff); + radv_cp_wait_mem(cs, cmd_buffer->qf, WAIT_REG_MEM_GREATER_OR_EQUAL, src_va + 44, 0x80000000, 0xffffffff); + } } } @@ -1737,7 +1755,7 @@ emit_begin_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *poo radv_update_hw_pipelinestat(cmd_buffer); - if (cmd_buffer->qf == RADV_QUEUE_COMPUTE) { + if (radv_cmd_buffer_uses_mec(cmd_buffer)) { uint32_t cs_invoc_offset = radv_get_pipelinestat_query_offset(VK_QUERY_PIPELINE_STATISTIC_COMPUTE_SHADER_INVOCATIONS_BIT); va += cs_invoc_offset; @@ -1829,6 +1847,7 @@ emit_begin_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *poo if (pool->uses_gds) { /* generated prim counter */ gfx10_copy_gds_query(cmd_buffer, RADV_SHADER_QUERY_PRIM_GEN_OFFSET(index), va + 32); + radv_cs_write_data_imm(cs, V_370_ME, va + 36, 0x80000000); /* Record that the command buffer needs GDS. */ cmd_buffer->gds_needed = true; @@ -1897,7 +1916,7 @@ emit_end_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *pool, va += pipelinestat_block_size; - if (cmd_buffer->qf == RADV_QUEUE_COMPUTE) { + if (radv_cmd_buffer_uses_mec(cmd_buffer)) { uint32_t cs_invoc_offset = radv_get_pipelinestat_query_offset(VK_QUERY_PIPELINE_STATISTIC_COMPUTE_SHADER_INVOCATIONS_BIT); va += cs_invoc_offset; @@ -1983,7 +2002,8 @@ emit_end_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *pool, if (pool->uses_gds) { /* generated prim counter */ - gfx10_copy_gds_query(cmd_buffer, RADV_SHADER_QUERY_PRIM_GEN_OFFSET(index), va + 36); + gfx10_copy_gds_query(cmd_buffer, RADV_SHADER_QUERY_PRIM_GEN_OFFSET(index), va + 40); + radv_cs_write_data_imm(cs, V_370_ME, va + 44, 0x80000000); cmd_buffer->state.active_prims_gen_gds_queries--; diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c index 3160824d461..abdfae500fe 100644 --- a/src/amd/vulkan/radv_queue.c +++ b/src/amd/vulkan/radv_queue.c @@ -996,7 +996,7 @@ radv_update_preamble_cs(struct radv_queue_state *queue, struct radv_device *devi struct radeon_cmdbuf *cs = NULL; cs = ws->cs_create(ws, radv_queue_family_to_ring(device->physical_device, queue->qf), false); if (!cs) { - result = VK_ERROR_OUT_OF_HOST_MEMORY; + result = VK_ERROR_OUT_OF_DEVICE_MEMORY; goto fail; } @@ -1263,8 +1263,10 @@ radv_create_gang_wait_preambles_postambles(struct radv_queue *queue) struct radeon_cmdbuf *ace_pre_cs = ws->cs_create(ws, AMD_IP_COMPUTE, false); struct radeon_cmdbuf *ace_post_cs = ws->cs_create(ws, AMD_IP_COMPUTE, false); - if (!leader_pre_cs || !leader_post_cs || !ace_pre_cs || !ace_post_cs) + if (!leader_pre_cs || !leader_post_cs || !ace_pre_cs || !ace_post_cs) { + r = VK_ERROR_OUT_OF_DEVICE_MEMORY; goto fail; + } radeon_check_space(ws, leader_pre_cs, 256); radeon_check_space(ws, leader_post_cs, 256); diff --git a/src/amd/vulkan/radv_sampler.c b/src/amd/vulkan/radv_sampler.c index 19fb0ef44e6..baf171dd5f7 100644 --- a/src/amd/vulkan/radv_sampler.c +++ b/src/amd/vulkan/radv_sampler.c @@ -200,8 +200,9 @@ radv_init_sampler(struct radv_device *device, struct radv_sampler *sampler, cons device->physical_device->rad_info.gfx_level == GFX8 || device->physical_device->rad_info.gfx_level == GFX9; unsigned filter_mode = radv_tex_filter_mode(sampler->vk.reduction_mode); unsigned depth_compare_func = V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER; - bool trunc_coord = (pCreateInfo->minFilter == VK_FILTER_NEAREST && pCreateInfo->magFilter == VK_FILTER_NEAREST) || - device->physical_device->rad_info.conformant_trunc_coord; + bool trunc_coord = ((pCreateInfo->minFilter == VK_FILTER_NEAREST && pCreateInfo->magFilter == VK_FILTER_NEAREST) || + device->physical_device->rad_info.conformant_trunc_coord) && + !device->disable_trunc_coord; bool uses_border_color = pCreateInfo->addressModeU == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER || pCreateInfo->addressModeV == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER || pCreateInfo->addressModeW == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER; diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 62625274578..54d1800a9ef 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -461,6 +461,7 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_shader_st .private_data = &spirv_debug_data, }, .force_tex_non_uniform = key->tex_non_uniform, + .force_ssbo_non_uniform = key->ssbo_non_uniform, }; nir = spirv_to_nir(spirv, stage->spirv.size / 4, spec_entries, num_spec_entries, stage->stage, stage->entrypoint, &spirv_options, &device->physical_device->nir_options[stage->stage]); @@ -1404,7 +1405,7 @@ radv_init_shader_upload_queue(struct radv_device *device) struct radv_shader_dma_submission *submission = calloc(1, sizeof(struct radv_shader_dma_submission)); submission->cs = ws->cs_create(ws, AMD_IP_SDMA, false); if (!submission->cs) - return VK_ERROR_OUT_OF_HOST_MEMORY; + return VK_ERROR_OUT_OF_DEVICE_MEMORY; list_addtail(&submission->list, &device->shader_dma_submissions); } diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index f902d3e1e94..c728412832b 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -85,6 +85,7 @@ struct radv_pipeline_key { uint32_t use_ngg : 1; uint32_t adjust_frag_coord_z : 1; uint32_t disable_aniso_single_level : 1; + uint32_t disable_trunc_coord : 1; uint32_t disable_sinking_load_input_fs : 1; uint32_t image_2d_view_of_3d : 1; uint32_t primitives_generated_query : 1; @@ -94,11 +95,13 @@ struct radv_pipeline_key { uint32_t dynamic_provoking_vtx_mode : 1; uint32_t dynamic_line_rast_mode : 1; uint32_t tex_non_uniform : 1; + uint32_t ssbo_non_uniform : 1; uint32_t enable_remove_point_size : 1; uint32_t unknown_rast_prim : 1; uint32_t mesh_shader_queries : 1; uint32_t vertex_robustness1 : 1; + uint32_t mesh_fast_launch_2 : 1; struct radv_shader_stage_key stage_info[MESA_VULKAN_SHADER_STAGES]; diff --git a/src/amd/vulkan/radv_sqtt.c b/src/amd/vulkan/radv_sqtt.c index 6c3fa93861a..979b9f9d845 100644 --- a/src/amd/vulkan/radv_sqtt.c +++ b/src/amd/vulkan/radv_sqtt.c @@ -579,7 +579,9 @@ radv_unregister_queue(struct radv_device *device, struct radv_queue *queue) static void radv_register_queues(struct radv_device *device, struct ac_sqtt *sqtt) { - radv_register_queue(device, &device->queues[RADV_QUEUE_GENERAL][0]); + if (device->queue_count[RADV_QUEUE_GENERAL] == 1) + radv_register_queue(device, &device->queues[RADV_QUEUE_GENERAL][0]); + for (uint32_t i = 0; i < device->queue_count[RADV_QUEUE_COMPUTE]; i++) radv_register_queue(device, &device->queues[RADV_QUEUE_COMPUTE][i]); } @@ -587,7 +589,9 @@ radv_register_queues(struct radv_device *device, struct ac_sqtt *sqtt) static void radv_unregister_queues(struct radv_device *device, struct ac_sqtt *sqtt) { - radv_unregister_queue(device, &device->queues[RADV_QUEUE_GENERAL][0]); + if (device->queue_count[RADV_QUEUE_GENERAL] == 1) + radv_unregister_queue(device, &device->queues[RADV_QUEUE_GENERAL][0]); + for (uint32_t i = 0; i < device->queue_count[RADV_QUEUE_COMPUTE]; i++) radv_unregister_queue(device, &device->queues[RADV_QUEUE_COMPUTE][i]); } diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 8fe25db82ae..ecb00d98575 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -1277,11 +1277,19 @@ gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level } if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); - radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) | EVENT_INDEX(0)); + if (qf == RADV_QUEUE_GENERAL) { + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); + radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) | EVENT_INDEX(0)); + } else if (qf == RADV_QUEUE_COMPUTE) { + radeon_set_sh_reg(cs, R_00B828_COMPUTE_PIPELINESTAT_ENABLE, S_00B828_PIPELINESTAT_ENABLE(1)); + } } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); - radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) | EVENT_INDEX(0)); + if (qf == RADV_QUEUE_GENERAL) { + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); + radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) | EVENT_INDEX(0)); + } else if (qf == RADV_QUEUE_COMPUTE) { + radeon_set_sh_reg(cs, R_00B828_COMPUTE_PIPELINESTAT_ENABLE, S_00B828_PIPELINESTAT_ENABLE(0)); + } } } @@ -1469,11 +1477,19 @@ si_cs_emit_cache_flush(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, enum si_emit_acquire_mem(cs, is_mec, gfx_level == GFX9, cp_coher_cntl); if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); - radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) | EVENT_INDEX(0)); + if (qf == RADV_QUEUE_GENERAL) { + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); + radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) | EVENT_INDEX(0)); + } else if (qf == RADV_QUEUE_COMPUTE) { + radeon_set_sh_reg(cs, R_00B828_COMPUTE_PIPELINESTAT_ENABLE, S_00B828_PIPELINESTAT_ENABLE(1)); + } } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); - radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) | EVENT_INDEX(0)); + if (qf == RADV_QUEUE_GENERAL) { + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); + radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) | EVENT_INDEX(0)); + } else if (qf == RADV_QUEUE_COMPUTE) { + radeon_set_sh_reg(cs, R_00B828_COMPUTE_PIPELINESTAT_ENABLE, S_00B828_PIPELINESTAT_ENABLE(0)); + } } } diff --git a/src/asahi/compiler/agx_pressure_schedule.c b/src/asahi/compiler/agx_pressure_schedule.c index a58509a191a..9dd940f8e8d 100644 --- a/src/asahi/compiler/agx_pressure_schedule.c +++ b/src/asahi/compiler/agx_pressure_schedule.c @@ -81,6 +81,8 @@ create_dag(agx_context *ctx, agx_block *block, void *memctx) assert(dep != AGX_SCHEDULE_CLASS_INVALID && "invalid instruction seen"); bool barrier = dep == AGX_SCHEDULE_CLASS_BARRIER; + bool discards = + I->op == AGX_OPCODE_SAMPLE_MASK || I->op == AGX_OPCODE_ZS_EMIT; if (dep == AGX_SCHEDULE_CLASS_STORE) add_dep(node, memory_load); @@ -94,6 +96,10 @@ create_dag(agx_context *ctx, agx_block *block, void *memctx) if (dep == AGX_SCHEDULE_CLASS_COVERAGE || barrier) serialize(node, &coverage); + /* Make sure side effects happen before a discard */ + if (discards) + add_dep(node, memory_store); + if (dep == AGX_SCHEDULE_CLASS_PRELOAD) serialize(node, &preload); else diff --git a/src/asahi/compiler/agx_register_allocate.c b/src/asahi/compiler/agx_register_allocate.c index 18f3f577bdd..a3a06ff789d 100644 --- a/src/asahi/compiler/agx_register_allocate.c +++ b/src/asahi/compiler/agx_register_allocate.c @@ -4,10 +4,12 @@ */ #include "util/u_dynarray.h" +#include "util/u_qsort.h" #include "agx_builder.h" #include "agx_compiler.h" #include "agx_debug.h" #include "agx_opcodes.h" +#include "util/u_qsort.h" /* SSA-based register allocator */ @@ -564,7 +566,7 @@ insert_copies_for_clobbered_killed(struct ra_ctx *rctx, unsigned reg, return; /* Sort by descending alignment so they are packed with natural alignment */ - qsort_r(vars, nr_vars, sizeof(vars[0]), sort_by_size, rctx->sizes); + util_qsort_r(vars, nr_vars, sizeof(vars[0]), sort_by_size, rctx->sizes); /* Reassign in the destination region */ unsigned base = reg; diff --git a/src/broadcom/ci/traces-broadcom.yml b/src/broadcom/ci/traces-broadcom.yml index 73ffb7ab917..0b1fa9a9628 100644 --- a/src/broadcom/ci/traces-broadcom.yml +++ b/src/broadcom/ci/traces-broadcom.yml @@ -27,11 +27,6 @@ traces: label: [unsupported] text: needs GL 4.1 - freedoom/freedoom-phase2-gl-high.trace: - broadcom-rpi4: - label: [unsupported] - text: needs GL 4.6 - glxgears/glxgears-2-v2.trace: broadcom-rpi4: label: [skip, flakes] @@ -116,14 +111,6 @@ traces: broadcom-rpi4: checksum: 831138a408cc9557528ef68381b080f2 - minetest/minetest-high-v2.trace: - broadcom-rpi4: - checksum: ade651f34a154d4508a00c47e532c482 - - minetest/minetest-v2.trace: - broadcom-rpi4: - checksum: 88a5c82db5ce868c81fa1d6e0f6d8dc9 - neverball/neverball-v2.trace: broadcom-rpi4: checksum: c8e8ee352bdb303e4ed144b69272575e diff --git a/src/broadcom/vulkan/v3dv_device.c b/src/broadcom/vulkan/v3dv_device.c index 48aa967e56f..027c35ffe80 100644 --- a/src/broadcom/vulkan/v3dv_device.c +++ b/src/broadcom/vulkan/v3dv_device.c @@ -553,8 +553,6 @@ physical_device_finish(struct v3dv_physical_device *device) close(device->render_fd); if (device->display_fd >= 0) close(device->display_fd); - if (device->master_fd >= 0) - close(device->master_fd); free(device->name); @@ -636,273 +634,6 @@ compute_memory_budget(struct v3dv_physical_device *device) return MIN2(heap_size, heap_used + heap_available); } -#if !using_v3d_simulator -#ifdef VK_USE_PLATFORM_XCB_KHR -static int -create_display_fd_xcb(VkIcdSurfaceBase *surface) -{ - int fd = -1; - - xcb_connection_t *conn; - xcb_dri3_open_reply_t *reply = NULL; - if (surface) { - if (surface->platform == VK_ICD_WSI_PLATFORM_XLIB) - conn = XGetXCBConnection(((VkIcdSurfaceXlib *)surface)->dpy); - else - conn = ((VkIcdSurfaceXcb *)surface)->connection; - } else { - conn = xcb_connect(NULL, NULL); - } - - if (xcb_connection_has_error(conn)) - goto finish; - - const xcb_setup_t *setup = xcb_get_setup(conn); - xcb_screen_iterator_t iter = xcb_setup_roots_iterator(setup); - xcb_screen_t *screen = iter.data; - - xcb_dri3_open_cookie_t cookie; - cookie = xcb_dri3_open(conn, screen->root, None); - reply = xcb_dri3_open_reply(conn, cookie, NULL); - if (!reply) - goto finish; - - if (reply->nfd != 1) - goto finish; - - fd = xcb_dri3_open_reply_fds(conn, reply)[0]; - fcntl(fd, F_SETFD, fcntl(fd, F_GETFD) | FD_CLOEXEC); - -finish: - if (!surface) - xcb_disconnect(conn); - if (reply) - free(reply); - - return fd; -} -#endif - -#ifdef VK_USE_PLATFORM_WAYLAND_KHR -struct v3dv_wayland_info { - struct wl_drm *wl_drm; - int fd; - bool is_set; - bool authenticated; -}; - -static void -v3dv_drm_handle_device(void *data, struct wl_drm *drm, const char *device) -{ - struct v3dv_wayland_info *info = data; - info->fd = open(device, O_RDWR | O_CLOEXEC); - info->is_set = info->fd != -1; - if (!info->is_set) { - fprintf(stderr, "v3dv_drm_handle_device: could not open %s (%s)\n", - device, strerror(errno)); - return; - } - - drm_magic_t magic; - if (drmGetMagic(info->fd, &magic)) { - fprintf(stderr, "v3dv_drm_handle_device: drmGetMagic failed\n"); - close(info->fd); - info->fd = -1; - info->is_set = false; - return; - } - wl_drm_authenticate(info->wl_drm, magic); -} - -static void -v3dv_drm_handle_format(void *data, struct wl_drm *drm, uint32_t format) -{ -} - -static void -v3dv_drm_handle_authenticated(void *data, struct wl_drm *drm) -{ - struct v3dv_wayland_info *info = data; - info->authenticated = true; -} - -static void -v3dv_drm_handle_capabilities(void *data, struct wl_drm *drm, uint32_t value) -{ -} - -struct wl_drm_listener v3dv_drm_listener = { - .device = v3dv_drm_handle_device, - .format = v3dv_drm_handle_format, - .authenticated = v3dv_drm_handle_authenticated, - .capabilities = v3dv_drm_handle_capabilities -}; - -static void -v3dv_registry_global(void *data, - struct wl_registry *registry, - uint32_t name, - const char *interface, - uint32_t version) -{ - struct v3dv_wayland_info *info = data; - if (strcmp(interface, wl_drm_interface.name) == 0) { - info->wl_drm = wl_registry_bind(registry, name, &wl_drm_interface, - MIN2(version, 2)); - wl_drm_add_listener(info->wl_drm, &v3dv_drm_listener, data); - }; -} - -static void -v3dv_registry_global_remove_cb(void *data, - struct wl_registry *registry, - uint32_t name) -{ -} - -static int -create_display_fd_wayland(VkIcdSurfaceBase *surface) -{ - struct wl_display *display; - struct wl_registry *registry = NULL; - - struct v3dv_wayland_info info = { - .wl_drm = NULL, - .fd = -1, - .is_set = false, - .authenticated = false - }; - - if (surface) - display = ((VkIcdSurfaceWayland *) surface)->display; - else - display = wl_display_connect(NULL); - - if (!display) - return -1; - - registry = wl_display_get_registry(display); - if (!registry) { - if (!surface) - wl_display_disconnect(display); - return -1; - } - - static const struct wl_registry_listener registry_listener = { - v3dv_registry_global, - v3dv_registry_global_remove_cb - }; - wl_registry_add_listener(registry, ®istry_listener, &info); - - wl_display_roundtrip(display); /* For the registry advertisement */ - wl_display_roundtrip(display); /* For the DRM device event */ - wl_display_roundtrip(display); /* For the authentication event */ - - wl_drm_destroy(info.wl_drm); - wl_registry_destroy(registry); - - if (!surface) - wl_display_disconnect(display); - - if (!info.is_set) - return -1; - - if (!info.authenticated) - return -1; - - return info.fd; -} -#endif - -/* Acquire an authenticated display fd without a surface reference. This is the - * case where the application is making WSI allocations outside the Vulkan - * swapchain context (only Zink, for now). Since we lack information about the - * underlying surface we just try our best to figure out the correct display - * and platform to use. It should work in most cases. - */ -static void -acquire_display_device_no_surface(struct v3dv_physical_device *pdevice) -{ -#ifdef VK_USE_PLATFORM_WAYLAND_KHR - pdevice->display_fd = create_display_fd_wayland(NULL); -#endif - -#ifdef VK_USE_PLATFORM_XCB_KHR - if (pdevice->display_fd == -1) - pdevice->display_fd = create_display_fd_xcb(NULL); -#endif - -#ifdef VK_USE_PLATFORM_DISPLAY_KHR - if (pdevice->display_fd == - 1 && pdevice->master_fd >= 0) - pdevice->display_fd = dup(pdevice->master_fd); -#endif -} - -/* Acquire an authenticated display fd from the surface. This is the regular - * case where the application is using swapchains to create WSI allocations. - * In this case we use the surface information to figure out the correct - * display and platform combination. - */ -static void -acquire_display_device_surface(struct v3dv_physical_device *pdevice, - VkIcdSurfaceBase *surface) -{ - /* Mesa will set both of VK_USE_PLATFORM_{XCB,XLIB} when building with - * platform X11, so only check for XCB and rely on XCB to get an - * authenticated device also for Xlib. - */ -#ifdef VK_USE_PLATFORM_XCB_KHR - if (surface->platform == VK_ICD_WSI_PLATFORM_XCB || - surface->platform == VK_ICD_WSI_PLATFORM_XLIB) { - pdevice->display_fd = create_display_fd_xcb(surface); - } -#endif - -#ifdef VK_USE_PLATFORM_WAYLAND_KHR - if (surface->platform == VK_ICD_WSI_PLATFORM_WAYLAND) - pdevice->display_fd = create_display_fd_wayland(surface); -#endif - -#ifdef VK_USE_PLATFORM_DISPLAY_KHR - if (surface->platform == VK_ICD_WSI_PLATFORM_DISPLAY && - pdevice->master_fd >= 0) { - pdevice->display_fd = dup(pdevice->master_fd); - } -#endif -} -#endif /* !using_v3d_simulator */ - -/* Attempts to get an authenticated display fd from the display server that - * we can use to allocate BOs for presentable images. - */ -VkResult -v3dv_physical_device_acquire_display(struct v3dv_physical_device *pdevice, - VkIcdSurfaceBase *surface) -{ - VkResult result = VK_SUCCESS; - mtx_lock(&pdevice->mutex); - - if (pdevice->display_fd != -1) - goto done; - - /* When running on the simulator we do everything on a single render node so - * we don't need to get an authenticated display fd from the display server. - */ -#if !using_v3d_simulator - if (surface) - acquire_display_device_surface(pdevice, surface); - else - acquire_display_device_no_surface(pdevice); - - if (pdevice->display_fd == -1) - result = VK_ERROR_INITIALIZATION_FAILED; -#endif - -done: - mtx_unlock(&pdevice->mutex); - return result; -} - static bool v3d_has_feature(struct v3dv_physical_device *device, enum drm_v3d_param feature) { @@ -999,7 +730,7 @@ create_physical_device(struct v3dv_instance *instance, drmDevicePtr display_device) { VkResult result = VK_SUCCESS; - int32_t master_fd = -1; + int32_t display_fd = -1; int32_t render_fd = -1; struct v3dv_physical_device *device = @@ -1073,16 +804,19 @@ create_physical_device(struct v3dv_instance *instance, #endif if (instance->vk.enabled_extensions.KHR_display || + instance->vk.enabled_extensions.KHR_xcb_surface || + instance->vk.enabled_extensions.KHR_xlib_surface || + instance->vk.enabled_extensions.KHR_wayland_surface || instance->vk.enabled_extensions.EXT_acquire_drm_display) { #if !using_v3d_simulator /* Open the primary node on the vc4 display device */ assert(display_device); - master_fd = open(primary_path, O_RDWR | O_CLOEXEC); + display_fd = open(primary_path, O_RDWR | O_CLOEXEC); #else /* There is only one device with primary and render nodes. * Open its primary node. */ - master_fd = open(primary_path, O_RDWR | O_CLOEXEC); + display_fd = open(primary_path, O_RDWR | O_CLOEXEC); #endif } @@ -1091,8 +825,7 @@ create_physical_device(struct v3dv_instance *instance, #endif device->render_fd = render_fd; /* The v3d render node */ - device->display_fd = -1; /* Authenticated vc4 primary node */ - device->master_fd = master_fd; /* Master vc4 primary node */ + device->display_fd = display_fd; /* Master vc4 primary node */ if (!v3d_get_device_info(device->render_fd, &device->devinfo, &v3dv_ioctl)) { result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED, @@ -1196,8 +929,8 @@ create_physical_device(struct v3dv_instance *instance, if (render_fd >= 0) close(render_fd); - if (master_fd >= 0) - close(master_fd); + if (display_fd >= 0) + close(display_fd); return result; } @@ -2253,18 +1986,8 @@ device_alloc_for_wsi(struct v3dv_device *device, #if using_v3d_simulator return device_alloc(device, mem, size); #else - /* If we are allocating for WSI we should have a swapchain and thus, - * we should've initialized the display device. However, Zink doesn't - * use swapchains, so in that case we can get here without acquiring the - * display device and we need to do it now. - */ VkResult result; struct v3dv_physical_device *pdevice = device->pdevice; - if (unlikely(pdevice->display_fd < 0)) { - result = v3dv_physical_device_acquire_display(pdevice, NULL); - if (result != VK_SUCCESS) - return result; - } assert(pdevice->display_fd != -1); mem->is_for_wsi = true; @@ -2766,6 +2489,18 @@ get_buffer_memory_requirements(struct v3dv_buffer *buffer, .size = align64(buffer->size, buffer->alignment), }; + /* UBO and SSBO may be read using ldunifa, which prefetches the next + * 4 bytes after a read. If the buffer's size is exactly a multiple + * of a page size and the shader reads the last 4 bytes with ldunifa + * the prefetching would read out of bounds and cause an MMU error, + * so we allocate extra space to avoid kernel error spamming. + */ + bool can_ldunifa = buffer->usage & + (VK_BUFFER_USAGE_STORAGE_BUFFER_BIT | + VK_BUFFER_USAGE_UNIFORM_BUFFER_BIT); + if (can_ldunifa && (buffer->size % 4096 == 0)) + pMemoryRequirements->memoryRequirements.size += buffer->alignment; + vk_foreach_struct(ext, pMemoryRequirements->pNext) { switch (ext->sType) { case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: { diff --git a/src/broadcom/vulkan/v3dv_private.h b/src/broadcom/vulkan/v3dv_private.h index 9c104b3d6d4..21934d802f8 100644 --- a/src/broadcom/vulkan/v3dv_private.h +++ b/src/broadcom/vulkan/v3dv_private.h @@ -138,7 +138,6 @@ struct v3dv_physical_device { char *name; int32_t render_fd; int32_t display_fd; - int32_t master_fd; /* We need these because it is not clear how to detect * valid devids in a portable way @@ -206,9 +205,6 @@ struct v3dv_physical_device { } caps; }; -VkResult v3dv_physical_device_acquire_display(struct v3dv_physical_device *pdevice, - VkIcdSurfaceBase *surface); - static inline struct v3dv_bo * v3dv_device_lookup_bo(struct v3dv_physical_device *device, uint32_t handle) { diff --git a/src/broadcom/vulkan/v3dv_wsi.c b/src/broadcom/vulkan/v3dv_wsi.c index 5efb1ea9530..404a64d0e17 100644 --- a/src/broadcom/vulkan/v3dv_wsi.c +++ b/src/broadcom/vulkan/v3dv_wsi.c @@ -24,8 +24,6 @@ */ #include "v3dv_private.h" -#include "drm-uapi/drm_fourcc.h" -#include "wsi_common_entrypoints.h" #include "vk_util.h" #include "wsi_common.h" #include "wsi_common_drm.h" @@ -41,19 +39,7 @@ static bool v3dv_wsi_can_present_on_device(VkPhysicalDevice _pdevice, int fd) { V3DV_FROM_HANDLE(v3dv_physical_device, pdevice, _pdevice); - - /* There are some instances with direct display extensions where this may be - * called before we have ever tried to create a swapchain, and therefore, - * before we have ever tried to acquire the display device, in which case we - * have to do it now. - */ - if (unlikely(pdevice->display_fd < 0 && pdevice->master_fd >= 0)) { - VkResult result = - v3dv_physical_device_acquire_display(pdevice, NULL); - if (result != VK_SUCCESS) - return false; - } - + assert(pdevice->display_fd != -1); return wsi_common_drm_devices_equal(fd, pdevice->display_fd); } @@ -66,7 +52,7 @@ v3dv_wsi_init(struct v3dv_physical_device *physical_device) v3dv_physical_device_to_handle(physical_device), v3dv_wsi_proc_addr, &physical_device->vk.instance->alloc, - physical_device->master_fd, NULL, + physical_device->display_fd, NULL, &(struct wsi_device_options){.sw_device = false}); if (result != VK_SUCCESS) @@ -89,67 +75,6 @@ v3dv_wsi_finish(struct v3dv_physical_device *physical_device) &physical_device->vk.instance->alloc); } -static void -constraint_surface_capabilities(VkSurfaceCapabilitiesKHR *caps) -{ - /* Our display pipeline requires that images are linear, so we cannot - * ensure that our swapchain images can be sampled. If we are running under - * a compositor in windowed mode, the DRM modifier negotiation should - * probably end up selecting an UIF layout for the swapchain images but it - * may still choose linear and send images directly for scanout if the - * surface is in fullscreen mode for example. If we are not running under - * a compositor, then we would always need them to be linear anyway. - */ - caps->supportedUsageFlags &= ~VK_IMAGE_USAGE_SAMPLED_BIT; -} - -VKAPI_ATTR VkResult VKAPI_CALL -v3dv_GetPhysicalDeviceSurfaceCapabilitiesKHR( - VkPhysicalDevice physicalDevice, - VkSurfaceKHR surface, - VkSurfaceCapabilitiesKHR* pSurfaceCapabilities) -{ - VkResult result; - result = wsi_GetPhysicalDeviceSurfaceCapabilitiesKHR(physicalDevice, - surface, - pSurfaceCapabilities); - constraint_surface_capabilities(pSurfaceCapabilities); - return result; -} - -VKAPI_ATTR VkResult VKAPI_CALL -v3dv_GetPhysicalDeviceSurfaceCapabilities2KHR( - VkPhysicalDevice physicalDevice, - const VkPhysicalDeviceSurfaceInfo2KHR* pSurfaceInfo, - VkSurfaceCapabilities2KHR* pSurfaceCapabilities) -{ - VkResult result; - result = wsi_GetPhysicalDeviceSurfaceCapabilities2KHR(physicalDevice, - pSurfaceInfo, - pSurfaceCapabilities); - constraint_surface_capabilities(&pSurfaceCapabilities->surfaceCapabilities); - return result; -} - -VKAPI_ATTR VkResult VKAPI_CALL -v3dv_CreateSwapchainKHR( - VkDevice _device, - const VkSwapchainCreateInfoKHR* pCreateInfo, - const VkAllocationCallbacks* pAllocator, - VkSwapchainKHR* pSwapchain) -{ - V3DV_FROM_HANDLE(v3dv_device, device, _device); - struct v3dv_physical_device *pdevice = device->pdevice; - - ICD_FROM_HANDLE(VkIcdSurfaceBase, surface, pCreateInfo->surface); - VkResult result = - v3dv_physical_device_acquire_display(pdevice, surface); - if (result != VK_SUCCESS) - return result; - - return wsi_CreateSwapchainKHR(_device, pCreateInfo, pAllocator, pSwapchain); -} - struct v3dv_image * v3dv_wsi_get_image_from_swapchain(VkSwapchainKHR swapchain, uint32_t index) { diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h index c9f3465406c..d2b5702d3c9 100644 --- a/src/compiler/nir/nir_builder.h +++ b/src/compiler/nir/nir_builder.h @@ -1483,9 +1483,12 @@ nir_build_deref_struct(nir_builder *build, nir_deref_instr *parent, } static inline nir_deref_instr * -nir_build_deref_cast(nir_builder *build, nir_def *parent, - nir_variable_mode modes, const struct glsl_type *type, - unsigned ptr_stride) +nir_build_deref_cast_with_alignment(nir_builder *build, nir_def *parent, + nir_variable_mode modes, + const struct glsl_type *type, + unsigned ptr_stride, + unsigned align_mul, + unsigned align_offset) { nir_deref_instr *deref = nir_deref_instr_create(build->shader, nir_deref_type_cast); @@ -1493,6 +1496,8 @@ nir_build_deref_cast(nir_builder *build, nir_def *parent, deref->modes = modes; deref->type = type; deref->parent = nir_src_for_ssa(parent); + deref->cast.align_mul = align_mul; + deref->cast.align_offset = align_offset; deref->cast.ptr_stride = ptr_stride; nir_def_init(&deref->instr, &deref->def, parent->num_components, @@ -1503,6 +1508,15 @@ nir_build_deref_cast(nir_builder *build, nir_def *parent, return deref; } +static inline nir_deref_instr * +nir_build_deref_cast(nir_builder *build, nir_def *parent, + nir_variable_mode modes, const struct glsl_type *type, + unsigned ptr_stride) +{ + return nir_build_deref_cast_with_alignment(build, parent, modes, type, + ptr_stride, 0, 0); +} + static inline nir_deref_instr * nir_alignment_deref_cast(nir_builder *build, nir_deref_instr *parent, uint32_t align_mul, uint32_t align_offset) @@ -1570,6 +1584,13 @@ nir_build_deref_follower(nir_builder *b, nir_deref_instr *parent, return nir_build_deref_struct(b, parent, leader->strct.index); + case nir_deref_type_cast: + return nir_build_deref_cast_with_alignment(b, &parent->def, + leader->modes, + leader->type, + leader->cast.ptr_stride, + leader->cast.align_mul, + leader->cast.align_offset); default: unreachable("Invalid deref instruction type"); } diff --git a/src/compiler/nir/nir_clone.c b/src/compiler/nir/nir_clone.c index 02571203c54..c8373bc7991 100644 --- a/src/compiler/nir/nir_clone.c +++ b/src/compiler/nir/nir_clone.c @@ -687,6 +687,32 @@ clone_function(clone_state *state, const nir_function *fxn, nir_shader *ns) return nfxn; } +static u_printf_info * +clone_printf_info(void *mem_ctx, const nir_shader *s) +{ + u_printf_info *infos = ralloc_array(mem_ctx, u_printf_info, s->printf_info_count); + + for (unsigned i = 0; i < s->printf_info_count; i++) { + const u_printf_info *src_info = &s->printf_info[i]; + + infos[i].num_args = src_info->num_args; + infos[i].arg_sizes = ralloc_size(mem_ctx, + sizeof(infos[i].arg_sizes[0]) * + src_info->num_args); + memcpy(infos[i].arg_sizes, src_info->arg_sizes, + sizeof(infos[i].arg_sizes[0]) * src_info->num_args); + + + infos[i].string_size = src_info->string_size; + infos[i].strings = ralloc_size(mem_ctx, + src_info->string_size); + memcpy(infos[i].strings, src_info->strings, + src_info->string_size); + } + + return infos; +} + nir_shader * nir_shader_clone(void *mem_ctx, const nir_shader *s) { @@ -734,6 +760,11 @@ nir_shader_clone(void *mem_ctx, const nir_shader *s) memcpy(ns->xfb_info, s->xfb_info, size); } + if (s->printf_info_count > 0) { + ns->printf_info = clone_printf_info(ns, s); + ns->printf_info_count = s->printf_info_count; + } + free_clone_state(&state); return ns; diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c index ad34c4db19d..47ad7a022fb 100644 --- a/src/compiler/nir/nir_divergence_analysis.c +++ b/src/compiler/nir/nir_divergence_analysis.c @@ -219,14 +219,9 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr) is_divergent = false; break; - case nir_intrinsic_load_reg: - case nir_intrinsic_load_reg_indirect: { - nir_intrinsic_instr *decl = nir_reg_get_decl(instr->src[0].ssa); - is_divergent = nir_intrinsic_divergent(decl); - if (instr->intrinsic == nir_intrinsic_load_reg_indirect) - is_divergent |= instr->src[1].ssa->divergent; + case nir_intrinsic_decl_reg: + is_divergent = nir_intrinsic_divergent(instr); break; - } /* Intrinsics with divergence depending on shader stage and hardware */ case nir_intrinsic_load_shader_record_ptr: @@ -463,7 +458,9 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr) case nir_intrinsic_load_desc_set_dynamic_index_intel: case nir_intrinsic_load_global_constant_bounded: case nir_intrinsic_load_global_constant_offset: - case nir_intrinsic_resource_intel: { + case nir_intrinsic_resource_intel: + case nir_intrinsic_load_reg: + case nir_intrinsic_load_reg_indirect: { unsigned num_srcs = nir_intrinsic_infos[instr->intrinsic].num_srcs; for (unsigned i = 0; i < num_srcs; i++) { if (instr->src[i].ssa->divergent) { @@ -619,6 +616,7 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr) case nir_intrinsic_isberd_nv: case nir_intrinsic_al2p_nv: case nir_intrinsic_ald_nv: + case nir_intrinsic_printf: is_divergent = true; break; diff --git a/src/compiler/nir/nir_gather_info.c b/src/compiler/nir/nir_gather_info.c index 40a5a421e28..4fcbe552107 100644 --- a/src/compiler/nir/nir_gather_info.c +++ b/src/compiler/nir/nir_gather_info.c @@ -410,10 +410,16 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader, { uint64_t slot_mask = 0; uint16_t slot_mask_16bit = 0; + bool is_patch_special = false; if (nir_intrinsic_infos[instr->intrinsic].index_map[NIR_INTRINSIC_IO_SEMANTICS] > 0) { nir_io_semantics semantics = nir_intrinsic_io_semantics(instr); + is_patch_special = semantics.location == VARYING_SLOT_TESS_LEVEL_INNER || + semantics.location == VARYING_SLOT_TESS_LEVEL_OUTER || + semantics.location == VARYING_SLOT_BOUNDING_BOX0 || + semantics.location == VARYING_SLOT_BOUNDING_BOX1; + if (semantics.location >= VARYING_SLOT_PATCH0 && semantics.location <= VARYING_SLOT_PATCH31) { /* Generic per-patch I/O. */ @@ -516,7 +522,8 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader, case nir_intrinsic_load_input_vertex: case nir_intrinsic_load_interpolated_input: if (shader->info.stage == MESA_SHADER_TESS_EVAL && - instr->intrinsic == nir_intrinsic_load_input) { + instr->intrinsic == nir_intrinsic_load_input && + !is_patch_special) { shader->info.patch_inputs_read |= slot_mask; if (!nir_src_is_const(*nir_get_io_offset_src(instr))) shader->info.patch_inputs_read_indirectly |= slot_mask; @@ -541,7 +548,8 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader, case nir_intrinsic_load_per_vertex_output: case nir_intrinsic_load_per_primitive_output: if (shader->info.stage == MESA_SHADER_TESS_CTRL && - instr->intrinsic == nir_intrinsic_load_output) { + instr->intrinsic == nir_intrinsic_load_output && + !is_patch_special) { shader->info.patch_outputs_read |= slot_mask; if (!nir_src_is_const(*nir_get_io_offset_src(instr))) shader->info.patch_outputs_accessed_indirectly |= slot_mask; @@ -575,7 +583,8 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader, case nir_intrinsic_store_per_vertex_output: case nir_intrinsic_store_per_primitive_output: if (shader->info.stage == MESA_SHADER_TESS_CTRL && - instr->intrinsic == nir_intrinsic_store_output) { + instr->intrinsic == nir_intrinsic_store_output && + !is_patch_special) { shader->info.patch_outputs_written |= slot_mask; if (!nir_src_is_const(*nir_get_io_offset_src(instr))) shader->info.patch_outputs_accessed_indirectly |= slot_mask; diff --git a/src/compiler/nir/nir_loop_analyze.c b/src/compiler/nir/nir_loop_analyze.c index b7114ca9a67..d9c0492a065 100644 --- a/src/compiler/nir/nir_loop_analyze.c +++ b/src/compiler/nir/nir_loop_analyze.c @@ -820,14 +820,46 @@ try_eval_const_alu(nir_const_value *dest, nir_alu_instr *alu, return true; } +static nir_op +invert_comparison_if_needed(nir_op alu_op, bool invert) +{ + if (!invert) + return alu_op; + + switch (alu_op) { + case nir_op_fge: + return nir_op_flt; + case nir_op_ige: + return nir_op_ilt; + case nir_op_uge: + return nir_op_ult; + case nir_op_flt: + return nir_op_fge; + case nir_op_ilt: + return nir_op_ige; + case nir_op_ult: + return nir_op_uge; + case nir_op_feq: + return nir_op_fneu; + case nir_op_ieq: + return nir_op_ine; + case nir_op_fneu: + return nir_op_feq; + case nir_op_ine: + return nir_op_ieq; + default: + unreachable("Unsuported comparison!"); + } +} + static int32_t get_iteration(nir_op cond_op, nir_const_value initial, nir_const_value step, - nir_const_value limit, unsigned bit_size, + nir_const_value limit, bool invert_cond, unsigned bit_size, unsigned execution_mode) { nir_const_value span, iter; - switch (cond_op) { + switch (invert_comparison_if_needed(cond_op, invert_cond)) { case nir_op_ine: /* In order for execution to be here, limit must be the same as initial. * Otherwise will_break_on_first_iteration would have returned false. @@ -1018,6 +1050,10 @@ calculate_iterations(nir_def *basis, nir_def *limit_basis, induction_base_type); } + if (cond.def->num_components != 1 || basis->num_components != 1 || + limit_basis->num_components != 1) + return -1; + /* do-while loops can increment the starting value before the condition is * checked. e.g. * @@ -1060,8 +1096,8 @@ calculate_iterations(nir_def *basis, nir_def *limit_basis, assert(nir_src_bit_size(alu->src[0].src) == nir_src_bit_size(alu->src[1].src)); - iter_int = get_iteration(alu_op, initial, step, limit, bit_size, - execution_mode); + iter_int = get_iteration(alu_op, initial, step, limit, invert_cond, + bit_size, execution_mode); break; case nir_op_fmul: /* Detecting non-zero loop counts when the loop increment is floating @@ -1087,7 +1123,8 @@ calculate_iterations(nir_def *basis, nir_def *limit_basis, if (iter_int < 0) return -1; - if (alu_op == nir_op_ine || alu_op == nir_op_fneu) + nir_op actual_alu_op = invert_comparison_if_needed(alu_op, invert_cond); + if (actual_alu_op == nir_op_ine || actual_alu_op == nir_op_fneu) return iter_int; /* An explanation from the GLSL unrolling pass: @@ -1101,11 +1138,13 @@ calculate_iterations(nir_def *basis, nir_def *limit_basis, */ for (int bias = -1; bias <= 1; bias++) { const int iter_bias = iter_int + bias; + if (iter_bias < 1) + continue; if (test_iterations(iter_bias, step, limit, alu_op, bit_size, induction_base_type, initial, limit_rhs, invert_cond, execution_mode)) { - return iter_bias > 0 ? iter_bias - trip_offset : iter_bias; + return iter_bias - trip_offset; } } diff --git a/src/compiler/nir/nir_lower_bit_size.c b/src/compiler/nir/nir_lower_bit_size.c index 37889a39faf..35097b85d83 100644 --- a/src/compiler/nir/nir_lower_bit_size.c +++ b/src/compiler/nir/nir_lower_bit_size.c @@ -203,7 +203,7 @@ lower_intrinsic_instr(nir_builder *b, nir_intrinsic_instr *intrin, if (intrin->intrinsic != nir_intrinsic_vote_feq && intrin->intrinsic != nir_intrinsic_vote_ieq) - res = nir_u2uN(b, res, old_bit_size); + res = nir_convert_to_bit_size(b, res, type, old_bit_size); nir_def_rewrite_uses(&intrin->def, res); break; diff --git a/src/compiler/nir/nir_lower_io.c b/src/compiler/nir/nir_lower_io.c index d2bca8ad7d3..58d696677fd 100644 --- a/src/compiler/nir/nir_lower_io.c +++ b/src/compiler/nir/nir_lower_io.c @@ -1570,7 +1570,8 @@ build_explicit_io_load(nir_builder *b, nir_intrinsic_instr *intrin, nir_def *zero = nir_imm_zero(b, load->num_components, bit_size); /* TODO: Better handle block_intel. */ - const unsigned load_size = (bit_size / 8) * load->num_components; + assert(load->num_components == 1); + const unsigned load_size = bit_size / 8; nir_push_if(b, addr_is_in_bounds(b, addr, addr_format, load_size)); nir_builder_instr_insert(b, &load->instr); @@ -1755,7 +1756,8 @@ build_explicit_io_store(nir_builder *b, nir_intrinsic_instr *intrin, if (addr_format_needs_bounds_check(addr_format)) { /* TODO: Better handle block_intel. */ - const unsigned store_size = (value->bit_size / 8) * store->num_components; + assert(store->num_components == 1); + const unsigned store_size = value->bit_size / 8; nir_push_if(b, addr_is_in_bounds(b, addr, addr_format, store_size)); nir_builder_instr_insert(b, &store->instr); @@ -1948,8 +1950,12 @@ nir_lower_explicit_io_instr(nir_builder *b, nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]); unsigned vec_stride = glsl_get_explicit_stride(deref->type); unsigned scalar_size = type_scalar_size_bytes(deref->type); - assert(vec_stride == 0 || glsl_type_is_vector(deref->type)); - assert(vec_stride == 0 || vec_stride >= scalar_size); + if (vec_stride == 0) { + vec_stride = scalar_size; + } else { + assert(glsl_type_is_vector(deref->type)); + assert(vec_stride >= scalar_size); + } uint32_t align_mul, align_offset; if (!nir_get_explicit_deref_align(deref, true, &align_mul, &align_offset)) { @@ -1958,10 +1964,27 @@ nir_lower_explicit_io_instr(nir_builder *b, align_offset = 0; } + /* In order for bounds checking to be correct as per the Vulkan spec, + * we need to check at the individual component granularity. Prior to + * robustness2, we're technically allowed to be sloppy by 16B. Even with + * robustness2, UBO loads are allowed to have a granularity as high as 256B + * depending on hardware limits. However, we have none of that information + * here. Short of adding new address formats, the easiest way to do that + * is to just split any loads and stores into individual components here. + * + * TODO: At some point in the future we may want to add more ops similar to + * nir_intrinsic_load_global_constant_bounded and make bouds checking the + * back-end's problem. Another option would be to somehow plumb more of + * that information through to nir_lower_explicit_io. For now, however, + * scalarizing is at least correct. + */ + bool scalarize = vec_stride > scalar_size || + addr_format_needs_bounds_check(addr_format); + switch (intrin->intrinsic) { case nir_intrinsic_load_deref: { nir_def *value; - if (vec_stride > scalar_size) { + if (scalarize) { nir_def *comps[NIR_MAX_VEC_COMPONENTS] = { NULL, }; @@ -1990,7 +2013,7 @@ nir_lower_explicit_io_instr(nir_builder *b, case nir_intrinsic_store_deref: { nir_def *value = intrin->src[1].ssa; nir_component_mask_t write_mask = nir_intrinsic_write_mask(intrin); - if (vec_stride > scalar_size) { + if (scalarize) { for (unsigned i = 0; i < intrin->num_components; i++) { if (!(write_mask & (1 << i))) continue; diff --git a/src/compiler/nir/nir_lower_mem_access_bit_sizes.c b/src/compiler/nir/nir_lower_mem_access_bit_sizes.c index 6d6d38f329b..c0b693a8b56 100644 --- a/src/compiler/nir/nir_lower_mem_access_bit_sizes.c +++ b/src/compiler/nir/nir_lower_mem_access_bit_sizes.c @@ -317,26 +317,26 @@ lower_mem_store(nir_builder *b, nir_intrinsic_instr *intrin, chunk_bytes = MIN2(max_chunk_bytes, requested_bytes - max_pad); unsigned chunk_bits = chunk_bytes * 8; - nir_def *chunk_value = value; - /* The one special case where nir_extract_bits cannot get a scalar by asking for - * 1 component of chunk_bits. - */ + nir_def *data; if (chunk_bits == 24) { - chunk_value = nir_pad_vec4(b, chunk_value); - chunk_bits = 32; + /* This is a bit of a special case because we don't have 24-bit integers */ + data = nir_extract_bits(b, &value, 1, chunk_start * 8, 3, 8); + data = nir_pack_bits(b, nir_pad_vector_imm_int(b, data, 0, 4), 32); + } else { + data = nir_extract_bits(b, &value, 1, chunk_start * 8, 1, chunk_bits); + data = nir_u2u32(b, data); } - nir_def *data = nir_u2u32(b, - nir_extract_bits(b, &chunk_value, 1, chunk_start * 8, - 1, chunk_bits)); nir_def *iand_mask = nir_imm_int(b, (1 << chunk_bits) - 1); if (chunk_align < requested.align) { nir_def *shift = nir_u2u32(b, nir_imul_imm(b, pad, 8)); data = nir_ishl(b, data, shift); - iand_mask = nir_inot(b, nir_ishl(b, iand_mask, shift)); + iand_mask = nir_ishl(b, iand_mask, shift); } + iand_mask = nir_inot(b, iand_mask); + switch (intrin->intrinsic) { case nir_intrinsic_store_ssbo: nir_ssbo_atomic(b, 32, intrin->src[1].ssa, chunk_offset, iand_mask, diff --git a/src/compiler/nir/nir_lower_scratch.c b/src/compiler/nir/nir_lower_scratch.c index 55e58688171..98bb30ee8cb 100644 --- a/src/compiler/nir/nir_lower_scratch.c +++ b/src/compiler/nir/nir_lower_scratch.c @@ -145,13 +145,21 @@ nir_lower_vars_to_scratch(nir_shader *shader, return false; } + bool progress = false; + nir_foreach_function_impl(impl, shader) { nir_foreach_block(block, impl) { - nir_foreach_instr(instr, block) { + nir_foreach_instr_safe(instr, block) { if (instr->type != nir_instr_type_deref) continue; nir_deref_instr *deref = nir_instr_as_deref(instr); + + if (nir_deref_instr_remove_if_unused(deref)) { + progress = true; + continue; + } + if (deref->deref_type != nir_deref_type_var) continue; @@ -178,7 +186,6 @@ nir_lower_vars_to_scratch(nir_shader *shader, var->data.location = INT_MAX; } - bool progress = false; nir_foreach_function_impl(impl, shader) { nir_builder build = nir_builder_create(impl); diff --git a/src/compiler/nir/nir_lower_tex.c b/src/compiler/nir/nir_lower_tex.c index 83f3ebb5c9e..716c5dda7a8 100644 --- a/src/compiler/nir/nir_lower_tex.c +++ b/src/compiler/nir/nir_lower_tex.c @@ -872,10 +872,14 @@ lower_tex_to_txd(nir_builder *b, nir_tex_instr *tex) txd->src[i].src = nir_src_for_ssa(tex->src[i].src.ssa); txd->src[i].src_type = tex->src[i].src_type; } - int coord = nir_tex_instr_src_index(tex, nir_tex_src_coord); - assert(coord >= 0); - nir_def *dfdx = nir_fddx(b, tex->src[coord].src.ssa); - nir_def *dfdy = nir_fddy(b, tex->src[coord].src.ssa); + int coord_idx = nir_tex_instr_src_index(tex, nir_tex_src_coord); + assert(coord_idx >= 0); + nir_def *coord = tex->src[coord_idx].src.ssa; + /* don't take the derivative of the array index */ + if (tex->is_array) + coord = nir_channels(b, coord, nir_component_mask(coord->num_components - 1)); + nir_def *dfdx = nir_fddx(b, coord); + nir_def *dfdy = nir_fddy(b, coord); txd->src[tex->num_srcs] = nir_tex_src_for_ssa(nir_tex_src_ddx, dfdx); txd->src[tex->num_srcs + 1] = nir_tex_src_for_ssa(nir_tex_src_ddy, dfdy); diff --git a/src/compiler/nir/nir_opt_copy_prop_vars.c b/src/compiler/nir/nir_opt_copy_prop_vars.c index 06ebd30b2b8..f291019c341 100644 --- a/src/compiler/nir/nir_opt_copy_prop_vars.c +++ b/src/compiler/nir/nir_opt_copy_prop_vars.c @@ -790,9 +790,15 @@ specialize_wildcards(nir_builder *b, nir_deref_path *specific) { nir_deref_instr **deref_p = &deref->path[1]; + nir_deref_instr *ret_tail = deref->path[0]; + for (; *deref_p; deref_p++) { + if ((*deref_p)->deref_type == nir_deref_type_array_wildcard) + break; + ret_tail = *deref_p; + } + nir_deref_instr **guide_p = &guide->path[1]; nir_deref_instr **spec_p = &specific->path[1]; - nir_deref_instr *ret_tail = deref->path[0]; for (; *deref_p; deref_p++) { if ((*deref_p)->deref_type == nir_deref_type_array_wildcard) { /* This is where things get tricky. We have to search through diff --git a/src/compiler/nir/nir_opt_loop_unroll.c b/src/compiler/nir/nir_opt_loop_unroll.c index 221775071a5..2d342fbb9ce 100644 --- a/src/compiler/nir/nir_opt_loop_unroll.c +++ b/src/compiler/nir/nir_opt_loop_unroll.c @@ -760,12 +760,8 @@ partial_unroll(nir_shader *shader, nir_loop *loop, unsigned trip_count) /* Insert break back into terminator */ nir_jump_instr *brk = nir_jump_instr_create(shader, nir_jump_break); - nir_if *nif = nir_block_get_following_if(nir_loop_first_block(new_loop)); - if (terminator->continue_from_then) { - nir_instr_insert_after_block(nir_if_last_else_block(nif), &brk->instr); - } else { - nir_instr_insert_after_block(nir_if_last_then_block(nif), &brk->instr); - } + nir_block *break_block = _mesa_hash_table_search(remap_table, terminator->break_block)->data; + nir_instr_insert_after_block(break_block, &brk->instr); /* Delete the original loop header and body */ nir_cf_delete(&lp_header); diff --git a/src/compiler/nir/nir_opt_move_discards_to_top.c b/src/compiler/nir/nir_opt_move_discards_to_top.c index 051e271def3..e7f245a37c5 100644 --- a/src/compiler/nir/nir_opt_move_discards_to_top.c +++ b/src/compiler/nir/nir_opt_move_discards_to_top.c @@ -165,10 +165,47 @@ opt_move_discards_to_top_impl(nir_function_impl *impl) instr->pass_flags = STOP_PROCESSING_INSTR_FLAG; goto break_all; } - - if ((intrin->intrinsic == nir_intrinsic_discard_if && consider_discards) || - intrin->intrinsic == nir_intrinsic_demote_if) + switch (intrin->intrinsic) { + case nir_intrinsic_quad_broadcast: + case nir_intrinsic_quad_swap_horizontal: + case nir_intrinsic_quad_swap_vertical: + case nir_intrinsic_quad_swap_diagonal: + case nir_intrinsic_quad_swizzle_amd: + consider_discards = false; + break; + case nir_intrinsic_vote_any: + case nir_intrinsic_vote_all: + case nir_intrinsic_vote_feq: + case nir_intrinsic_vote_ieq: + case nir_intrinsic_ballot: + case nir_intrinsic_first_invocation: + case nir_intrinsic_read_invocation: + case nir_intrinsic_read_first_invocation: + case nir_intrinsic_elect: + case nir_intrinsic_reduce: + case nir_intrinsic_inclusive_scan: + case nir_intrinsic_exclusive_scan: + case nir_intrinsic_shuffle: + case nir_intrinsic_shuffle_xor: + case nir_intrinsic_shuffle_up: + case nir_intrinsic_shuffle_down: + case nir_intrinsic_rotate: + case nir_intrinsic_masked_swizzle_amd: + instr->pass_flags = STOP_PROCESSING_INSTR_FLAG; + goto break_all; + case nir_intrinsic_discard_if: + if (!consider_discards) { + /* assume that a shader either uses discard or demote, but not both */ + instr->pass_flags = STOP_PROCESSING_INSTR_FLAG; + goto break_all; + } + FALLTHROUGH; + case nir_intrinsic_demote_if: moved = moved || try_move_discard(intrin); + break; + default: + break; + } continue; } diff --git a/src/compiler/nir/nir_split_vars.c b/src/compiler/nir/nir_split_vars.c index 165750cd2e2..7cbd6d6a638 100644 --- a/src/compiler/nir/nir_split_vars.c +++ b/src/compiler/nir/nir_split_vars.c @@ -87,7 +87,15 @@ num_array_levels_in_array_of_vector_type(const struct glsl_type *type) if (glsl_type_is_array_or_matrix(type)) { num_levels++; type = glsl_get_array_element(type); - } else if (glsl_type_is_vector_or_scalar(type)) { + } else if (glsl_type_is_vector_or_scalar(type) && + !glsl_type_is_cmat(type)) { + /* glsl_type_is_vector_or_scalar would more accruately be called "can + * be an r-value that isn't an array, structure, or matrix. This + * optimization pass really shouldn't do anything to cooperative + * matrices. These matrices will eventually be lowered to something + * else (dependent on the backend), and that thing may (or may not) + * be handled by this or another pass. + */ return num_levels; } else { /* Not an array of vectors */ diff --git a/src/compiler/nir/tests/loop_analyze_tests.cpp b/src/compiler/nir/tests/loop_analyze_tests.cpp index 2735d4cbcd4..a530b7f226c 100644 --- a/src/compiler/nir/tests/loop_analyze_tests.cpp +++ b/src/compiler/nir/tests/loop_analyze_tests.cpp @@ -284,6 +284,8 @@ COMPARE_REVERSE(ishl) } INOT_COMPARE(ilt_rev) +INOT_COMPARE(ine) +INOT_COMPARE(uge_rev) #define KNOWN_COUNT_TEST(_init_value, _cond_value, _incr_value, cond, incr, count) \ TEST_F(nir_loop_analyze_test, incr ## _ ## cond ## _known_count_ ## count) \ @@ -476,6 +478,26 @@ KNOWN_COUNT_TEST(0x00000000, 0x00000001, 0x00000001, uge, iadd, 1) */ KNOWN_COUNT_TEST(0x00000000, 0x00000000, 0x00000001, ine, iadd, 1) +/* uint i = 0; + * while (true) { + * if (!(i != 6)) + * break; + * + * i++; + * } + */ +KNOWN_COUNT_TEST(0x00000000, 0x00000006, 0x00000001, inot_ine, iadd, 6) + +/* uint i = 0; + * while (true) { + * i++; + * + * if (!(i != 8)) + * break; + * } + */ +KNOWN_COUNT_TEST_INVERT(0x00000000, 0x00000001, 0x00000008, inot_ine, iadd, 7) + /* uint i = 0; * while (true) { * if (i == 1) @@ -486,6 +508,26 @@ KNOWN_COUNT_TEST(0x00000000, 0x00000000, 0x00000001, ine, iadd, 1) */ KNOWN_COUNT_TEST(0x00000000, 0x00000001, 0x00000001, ieq, iadd, 1) +/* uint i = 0; + * while (true) { + * if (i == 6) + * break; + * + * i++; + * } + */ +KNOWN_COUNT_TEST(0x00000000, 0x00000006, 0x00000001, ieq, iadd, 6) + +/* uint i = 0; + * while (true) { + * i++; + * + * if (i == 6) + * break; + * } + */ +KNOWN_COUNT_TEST_INVERT(0x00000000, 0x00000001, 0x00000006, ieq, iadd, 5) + /* float i = 0.0; * while (true) { * if (i != 0.0) @@ -526,6 +568,16 @@ KNOWN_COUNT_TEST_INVERT(0x00000000, 0x00000001, 0x00000006, ige, iadd, 5) */ KNOWN_COUNT_TEST(0x0000000a, 0x00000005, 0xffffffff, inot_ilt_rev, iadd, 5) +/* uint i = 0; + * while (true) { + * if (!(0 >= i)) + * break; + * + * i += 1; + * } + */ +KNOWN_COUNT_TEST(0x00000000, 0x00000000, 0x00000001, inot_uge_rev, iadd, 1) + /* uint i = 0; * while (true) { * if (i != 0) diff --git a/src/compiler/spirv/meson.build b/src/compiler/spirv/meson.build index dfb53d6738c..b1c5b1f16e6 100644 --- a/src/compiler/spirv/meson.build +++ b/src/compiler/spirv/meson.build @@ -81,7 +81,9 @@ idep_vtn = declare_dependency( spirv2nir = executable( 'spirv2nir', - files('spirv2nir.c'), + files('spirv2nir.c') + [ + vtn_generator_ids_h, + ], dependencies : [dep_m, idep_vtn, idep_mesautil], include_directories : [inc_include, inc_src, inc_mapi, inc_mesa], c_args : [c_msvc_compat_args, no_override_init_args], diff --git a/src/compiler/spirv/nir_spirv.h b/src/compiler/spirv/nir_spirv.h index 1369a0e6b47..bfcccdc0fcc 100644 --- a/src/compiler/spirv/nir_spirv.h +++ b/src/compiler/spirv/nir_spirv.h @@ -116,6 +116,8 @@ struct spirv_to_nir_options { /* Force texture sampling to be non-uniform. */ bool force_tex_non_uniform; + /* Force SSBO accesses to be non-uniform. */ + bool force_ssbo_non_uniform; /* In Debug Builds, instead of emitting an OS break on failure, just return NULL from * spirv_to_nir(). This is useful for the unit tests that want to report a test failed diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index 2587c866723..5f36118c704 100644 --- a/src/compiler/spirv/spirv_to_nir.c +++ b/src/compiler/spirv/spirv_to_nir.c @@ -4375,9 +4375,13 @@ vtn_handle_composite(struct vtn_builder *b, SpvOp opcode, w + 5, count - 5); break; - case SpvOpCopyLogical: + case SpvOpCopyLogical: { ssa = vtn_composite_copy(b, vtn_ssa_value(b, w[3])); + struct vtn_type *dst_type = vtn_get_value_type(b, w[2]); + vtn_assert(vtn_types_compatible(b, type, dst_type)); + ssa->type = glsl_get_bare_type(dst_type->type); break; + } case SpvOpCopyObject: vtn_copy_value(b, w[3], w[2]); return; diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c index 04d71ae6eb2..a6b327f6a02 100644 --- a/src/compiler/spirv/vtn_alu.c +++ b/src/compiler/spirv/vtn_alu.c @@ -94,38 +94,16 @@ matrix_multiply(struct vtn_builder *b, transpose_result = true; } - if (src0_transpose && !src1_transpose && - glsl_get_base_type(src0->type) == GLSL_TYPE_FLOAT) { - /* We already have the rows of src0 and the columns of src1 available, - * so we can just take the dot product of each row with each column to - * get the result. - */ - - for (unsigned i = 0; i < src1_columns; i++) { - nir_def *vec_src[4]; - for (unsigned j = 0; j < src0_rows; j++) { - vec_src[j] = nir_fdot(&b->nb, src0_transpose->elems[j]->def, - src1->elems[i]->def); - } - dest->elems[i]->def = nir_vec(&b->nb, vec_src, src0_rows); - } - } else { - /* We don't handle the case where src1 is transposed but not src0, since - * the general case only uses individual components of src1 so the - * optimizer should chew through the transpose we emitted for src1. - */ - - for (unsigned i = 0; i < src1_columns; i++) { - /* dest[i] = sum(src0[j] * src1[i][j] for all j) */ + for (unsigned i = 0; i < src1_columns; i++) { + /* dest[i] = sum(src0[j] * src1[i][j] for all j) */ + dest->elems[i]->def = + nir_fmul(&b->nb, src0->elems[src0_columns - 1]->def, + nir_channel(&b->nb, src1->elems[i]->def, src0_columns - 1)); + for (int j = src0_columns - 2; j >= 0; j--) { dest->elems[i]->def = - nir_fmul(&b->nb, src0->elems[src0_columns - 1]->def, - nir_channel(&b->nb, src1->elems[i]->def, src0_columns - 1)); - for (int j = src0_columns - 2; j >= 0; j--) { - dest->elems[i]->def = - nir_ffma(&b->nb, src0->elems[j]->def, - nir_channel(&b->nb, src1->elems[i]->def, j), - dest->elems[i]->def); - } + nir_ffma(&b->nb, src0->elems[j]->def, + nir_channel(&b->nb, src1->elems[i]->def, j), + dest->elems[i]->def); } } diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_variables.c index d00e3d785fd..651041ad4c0 100644 --- a/src/compiler/spirv/vtn_variables.c +++ b/src/compiler/spirv/vtn_variables.c @@ -2632,6 +2632,9 @@ vtn_handle_variables(struct vtn_builder *b, SpvOp opcode, /* Workaround for https://gitlab.freedesktop.org/mesa/mesa/-/issues/3406 */ access |= base->access & ACCESS_NON_UNIFORM; + if (base->mode == vtn_variable_mode_ssbo && b->options->force_ssbo_non_uniform) + access |= ACCESS_NON_UNIFORM; + struct vtn_pointer *ptr = vtn_pointer_dereference(b, base, chain); ptr->ptr_type = ptr_type; ptr->access |= access; diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c index 50d7dfe0d1f..e0dd739e832 100644 --- a/src/egl/drivers/dri2/egl_dri2.c +++ b/src/egl/drivers/dri2/egl_dri2.c @@ -73,7 +73,7 @@ #include "egl_dri2.h" #include "egldefines.h" -#define NUM_ATTRIBS 12 +#define NUM_ATTRIBS 16 static const struct dri2_pbuffer_visual { const char *format_name; @@ -1067,6 +1067,8 @@ dri2_setup_extensions(_EGLDisplay *disp) dri2_dpy->dri3_major_version != -1 && !dri2_dpy->multibuffers_available && #endif + (disp->Platform == EGL_PLATFORM_X11_KHR || + disp->Platform == EGL_PLATFORM_XCB_EXT) && !debug_get_bool_option("LIBGL_KOPPER_DRI2", false)) return EGL_FALSE; @@ -1075,6 +1077,43 @@ dri2_setup_extensions(_EGLDisplay *disp) return EGL_TRUE; } +EGLBoolean +dri2_setup_device(_EGLDisplay *disp, EGLBoolean software) +{ + struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp); + _EGLDevice *dev; + int render_fd; + + /* Extensions must be loaded before calling this function */ + assert(dri2_dpy->mesa); + /* If we're not software, we need a DRM node FD */ + assert(software || dri2_dpy->fd_render_gpu >= 0); + + /* fd_render_gpu is what we got from WSI, so might actually be a lie and + * not a render node... */ + if (software) { + render_fd = -1; + } else if (loader_is_device_render_capable(dri2_dpy->fd_render_gpu)) { + render_fd = dri2_dpy->fd_render_gpu; + } else { + render_fd = dri2_dpy->mesa->queryCompatibleRenderOnlyDeviceFd( + dri2_dpy->fd_render_gpu); + if (render_fd < 0) + return EGL_FALSE; + } + + dev = _eglFindDevice(render_fd, software); + + if (render_fd >= 0 && render_fd != dri2_dpy->fd_render_gpu) + close(render_fd); + + if (!dev) + return EGL_FALSE; + + disp->Device = dev; + return EGL_TRUE; +} + /** * Called via eglInitialize(), drv->Initialize(). * diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h index bb09ceb8e93..5edd810f476 100644 --- a/src/egl/drivers/dri2/egl_dri2.h +++ b/src/egl/drivers/dri2/egl_dri2.h @@ -483,6 +483,9 @@ dri2_create_screen(_EGLDisplay *disp); EGLBoolean dri2_setup_extensions(_EGLDisplay *disp); +EGLBoolean +dri2_setup_device(_EGLDisplay *disp, EGLBoolean software); + __DRIdrawable * dri2_surface_get_dri_drawable(_EGLSurface *surf); diff --git a/src/egl/drivers/dri2/platform_android.c b/src/egl/drivers/dri2/platform_android.c index b0b327036fe..e530fc9517c 100644 --- a/src/egl/drivers/dri2/platform_android.c +++ b/src/egl/drivers/dri2/platform_android.c @@ -65,6 +65,15 @@ struct droid_yuv_format { int fourcc; /* DRM_FORMAT_ */ }; +/* This enumeration can be deleted if Android defined it in + * system/core/include/system/graphics.h + */ +enum { + HAL_PIXEL_FORMAT_NV12_Y_TILED_INTEL = 0x100, + HAL_PIXEL_FORMAT_NV12 = 0x10F, + HAL_PIXEL_FORMAT_P010_INTEL = 0x110 +}; + /* The following table is used to look up a DRI image FourCC based * on native format and information contained in android_ycbcr struct. */ static const struct droid_yuv_format droid_yuv_formats[] = { @@ -73,6 +82,9 @@ static const struct droid_yuv_format droid_yuv_formats[] = { {HAL_PIXEL_FORMAT_YCbCr_420_888, YCbCr, 1, DRM_FORMAT_YUV420}, {HAL_PIXEL_FORMAT_YCbCr_420_888, YCrCb, 1, DRM_FORMAT_YVU420}, {HAL_PIXEL_FORMAT_YV12, YCrCb, 1, DRM_FORMAT_YVU420}, + {HAL_PIXEL_FORMAT_NV12, YCbCr, 2, DRM_FORMAT_NV12}, + {HAL_PIXEL_FORMAT_NV12_Y_TILED_INTEL, YCbCr, 2, DRM_FORMAT_NV12}, + {HAL_PIXEL_FORMAT_P010_INTEL, YCbCr, 4, DRM_FORMAT_P010}, /* HACK: See droid_create_image_from_prime_fds() and * https://issuetracker.google.com/32077885. */ {HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED, YCbCr, 2, DRM_FORMAT_NV12}, @@ -360,6 +372,7 @@ native_window_buffer_get_buffer_info(struct dri2_egl_display *dri2_dpy, */ static const char cros_gralloc_module_name[] = "CrOS Gralloc"; +static const char gbm_gralloc_module_name[] = "GBM Memory Allocator"; #define CROS_GRALLOC_DRM_GET_BUFFER_INFO 4 #define CROS_GRALLOC_DRM_GET_USAGE 5 @@ -381,7 +394,8 @@ cros_get_buffer_info(struct dri2_egl_display *dri2_dpy, { struct cros_gralloc0_buffer_info info; - if (strcmp(dri2_dpy->gralloc->common.name, cros_gralloc_module_name) == 0 && + if ((strcmp(dri2_dpy->gralloc->common.name, cros_gralloc_module_name) == 0 || + strcmp(dri2_dpy->gralloc->common.name, gbm_gralloc_module_name) == 0) && dri2_dpy->gralloc->perform && dri2_dpy->gralloc->perform(dri2_dpy->gralloc, CROS_GRALLOC_DRM_GET_BUFFER_INFO, buf->handle, @@ -1476,7 +1490,6 @@ droid_open_device(_EGLDisplay *disp, bool swrast) EGLBoolean dri2_initialize_android(_EGLDisplay *disp) { - _EGLDevice *dev; bool device_opened = false; struct dri2_egl_display *dri2_dpy; const char *err; @@ -1505,16 +1518,13 @@ dri2_initialize_android(_EGLDisplay *disp) dri2_dpy->fd_display_gpu = dri2_dpy->fd_render_gpu; - dev = _eglFindDevice(dri2_dpy->fd_render_gpu, false); - if (!dev) { - err = "DRI2: failed to find EGLDevice"; + if (!dri2_setup_extensions(disp)) { + err = "DRI2: failed to setup extensions"; goto cleanup; } - disp->Device = dev; - - if (!dri2_setup_extensions(disp)) { - err = "DRI2: failed to setup extensions"; + if (!dri2_setup_device(disp, false)) { + err = "DRI2: failed to setup EGLDevice"; goto cleanup; } diff --git a/src/egl/drivers/dri2/platform_drm.c b/src/egl/drivers/dri2/platform_drm.c index ec492d5e76d..db679c1355b 100644 --- a/src/egl/drivers/dri2/platform_drm.c +++ b/src/egl/drivers/dri2/platform_drm.c @@ -118,6 +118,9 @@ dri2_drm_config_is_compatible(struct dri2_egl_display *dri2_dpy, break; } + if (visual->is_yuv) + return false; + if (i == dri2_dpy->gbm_dri->num_visuals) return false; @@ -512,6 +515,9 @@ drm_add_configs_for_visuals(_EGLDisplay *disp) for (unsigned j = 0; j < num_visuals; j++) { struct dri2_egl_config *dri2_conf; + if (visuals[j].is_yuv) + continue; + if (visuals[j].rgba_shifts.red != shifts[0] || visuals[j].rgba_shifts.green != shifts[1] || visuals[j].rgba_shifts.blue != shifts[2] || @@ -579,7 +585,6 @@ get_fd_render_gpu_drm(struct gbm_dri_device *gbm_dri, int fd_display_gpu) EGLBoolean dri2_initialize_drm(_EGLDisplay *disp) { - _EGLDevice *dev; struct gbm_device *gbm; const char *err; struct dri2_egl_display *dri2_dpy = dri2_display_create(); @@ -640,14 +645,6 @@ dri2_initialize_drm(_EGLDisplay *disp) goto cleanup; } - dev = _eglFindDevice(dri2_dpy->fd_render_gpu, dri2_dpy->gbm_dri->software); - if (!dev) { - err = "DRI2: failed to find EGLDevice"; - goto cleanup; - } - - disp->Device = dev; - dri2_dpy->driver_name = strdup(dri2_dpy->gbm_dri->driver_name); if (!dri2_load_driver_dri3(disp)) { @@ -681,6 +678,11 @@ dri2_initialize_drm(_EGLDisplay *disp) goto cleanup; } + if (!dri2_setup_device(disp, dri2_dpy->gbm_dri->software)) { + err = "DRI2: failed to setup EGLDevice"; + goto cleanup; + } + dri2_setup_screen(disp); if (!drm_add_configs_for_visuals(disp)) { diff --git a/src/egl/drivers/dri2/platform_wayland.c b/src/egl/drivers/dri2/platform_wayland.c index 8922a1e1a8b..7e85dd682a4 100644 --- a/src/egl/drivers/dri2/platform_wayland.c +++ b/src/egl/drivers/dri2/platform_wayland.c @@ -1146,6 +1146,7 @@ get_back_bo(struct dri2_egl_surface *dri2_surf) int buffer_fds[4]; int strides[4]; int offsets[4]; + unsigned error; if (!dri2_dpy->image->queryImage(linear_copy_display_gpu_image, __DRI_IMAGE_ATTRIB_NUM_PLANES, @@ -1185,12 +1186,17 @@ get_back_bo(struct dri2_egl_surface *dri2_surf) /* The linear buffer was created in the display GPU's vram, so we * need to make it visible to render GPU */ - dri2_surf->back->linear_copy = dri2_dpy->image->createImageFromFds( - dri2_dpy->dri_screen_render_gpu, dri2_surf->base.Width, - dri2_surf->base.Height, - loader_image_format_to_fourcc(linear_dri_image_format), - &buffer_fds[0], num_planes, &strides[0], &offsets[0], - dri2_surf->back); + dri2_surf->back->linear_copy = + dri2_dpy->image->createImageFromDmaBufs3( + dri2_dpy->dri_screen_render_gpu, dri2_surf->base.Width, + dri2_surf->base.Height, + loader_image_format_to_fourcc(linear_dri_image_format), + linear_mod, &buffer_fds[0], num_planes, &strides[0], + &offsets[0], __DRI_YUV_COLOR_SPACE_UNDEFINED, + __DRI_YUV_RANGE_UNDEFINED, __DRI_YUV_CHROMA_SITING_UNDEFINED, + __DRI_YUV_CHROMA_SITING_UNDEFINED, 0, &error, + dri2_surf->back); + for (i = 0; i < num_planes; ++i) { if (buffer_fds[i] != -1) close(buffer_fds[i]); @@ -2161,7 +2167,6 @@ dri2_initialize_wayland_drm_extensions(struct dri2_egl_display *dri2_dpy) static EGLBoolean dri2_initialize_wayland_drm(_EGLDisplay *disp) { - _EGLDevice *dev; struct dri2_egl_display *dri2_dpy = dri2_display_create(); if (!dri2_dpy) return EGL_FALSE; @@ -2205,14 +2210,6 @@ dri2_initialize_wayland_drm(_EGLDisplay *disp) loader_get_user_preferred_fd(&dri2_dpy->fd_render_gpu, &dri2_dpy->fd_display_gpu); - dev = _eglFindDevice(dri2_dpy->fd_render_gpu, false); - if (!dev) { - _eglError(EGL_NOT_INITIALIZED, "DRI2: failed to find EGLDevice"); - goto cleanup; - } - - disp->Device = dev; - if (dri2_dpy->fd_render_gpu != dri2_dpy->fd_display_gpu) { free(dri2_dpy->device_name); dri2_dpy->device_name = @@ -2249,6 +2246,11 @@ dri2_initialize_wayland_drm(_EGLDisplay *disp) if (!dri2_setup_extensions(disp)) goto cleanup; + if (!dri2_setup_device(disp, false)) { + _eglError(EGL_NOT_INITIALIZED, "DRI2: failed to setup EGLDevice"); + goto cleanup; + } + dri2_setup_screen(disp); dri2_wl_setup_swap_interval(disp); @@ -2730,7 +2732,6 @@ static const __DRIextension *swrast_loader_extensions[] = { static EGLBoolean dri2_initialize_wayland_swrast(_EGLDisplay *disp) { - _EGLDevice *dev; struct dri2_egl_display *dri2_dpy = dri2_display_create(); if (!dri2_dpy) return EGL_FALSE; @@ -2776,14 +2777,6 @@ dri2_initialize_wayland_swrast(_EGLDisplay *disp) if (disp->Options.Zink) dri2_initialize_wayland_drm_extensions(dri2_dpy); - dev = _eglFindDevice(dri2_dpy->fd_render_gpu, true); - if (!dev) { - _eglError(EGL_NOT_INITIALIZED, "DRI2: failed to find EGLDevice"); - goto cleanup; - } - - disp->Device = dev; - dri2_dpy->driver_name = strdup(disp->Options.Zink ? "zink" : "swrast"); if (!dri2_load_driver_swrast(disp)) goto cleanup; @@ -2796,6 +2789,11 @@ dri2_initialize_wayland_swrast(_EGLDisplay *disp) if (!dri2_setup_extensions(disp)) goto cleanup; + if (!dri2_setup_device(disp, true)) { + _eglError(EGL_NOT_INITIALIZED, "DRI2: failed to setup EGLDevice"); + goto cleanup; + } + dri2_setup_screen(disp); dri2_wl_setup_swap_interval(disp); diff --git a/src/egl/drivers/dri2/platform_x11.c b/src/egl/drivers/dri2/platform_x11.c index a4c64f8fe08..6af987ed7ad 100644 --- a/src/egl/drivers/dri2/platform_x11.c +++ b/src/egl/drivers/dri2/platform_x11.c @@ -1505,7 +1505,6 @@ dri2_x11_setup_swap_interval(_EGLDisplay *disp) static EGLBoolean dri2_initialize_x11_swrast(_EGLDisplay *disp) { - _EGLDevice *dev; struct dri2_egl_display *dri2_dpy = dri2_display_create(); if (!dri2_dpy) return EGL_FALSE; @@ -1513,14 +1512,6 @@ dri2_initialize_x11_swrast(_EGLDisplay *disp) if (!dri2_get_xcb_connection(disp, dri2_dpy)) goto cleanup; - dev = _eglFindDevice(dri2_dpy->fd_render_gpu, true); - if (!dev) { - _eglError(EGL_NOT_INITIALIZED, "DRI2: failed to find EGLDevice"); - goto cleanup; - } - - disp->Device = dev; - /* * Every hardware driver_name is set using strdup. Doing the same in * here will allow is to simply free the memory at dri2_terminate(). @@ -1540,6 +1531,11 @@ dri2_initialize_x11_swrast(_EGLDisplay *disp) if (!dri2_setup_extensions(disp)) goto cleanup; + if (!dri2_setup_device(disp, true)) { + _eglError(EGL_NOT_INITIALIZED, "DRI2: failed to setup EGLDevice"); + goto cleanup; + } + dri2_setup_screen(disp); if (disp->Options.Zink) { @@ -1595,7 +1591,6 @@ static const __DRIextension *dri3_image_loader_extensions[] = { static EGLBoolean dri2_initialize_x11_dri3(_EGLDisplay *disp) { - _EGLDevice *dev; struct dri2_egl_display *dri2_dpy = dri2_display_create(); if (!dri2_dpy) @@ -1607,14 +1602,6 @@ dri2_initialize_x11_dri3(_EGLDisplay *disp) if (!dri3_x11_connect(dri2_dpy)) goto cleanup; - dev = _eglFindDevice(dri2_dpy->fd_render_gpu, false); - if (!dev) { - _eglError(EGL_NOT_INITIALIZED, "DRI2: failed to find EGLDevice"); - goto cleanup; - } - - disp->Device = dev; - if (!dri2_load_driver_dri3(disp)) goto cleanup; @@ -1629,6 +1616,11 @@ dri2_initialize_x11_dri3(_EGLDisplay *disp) if (!dri2_setup_extensions(disp)) goto cleanup; + if (!dri2_setup_device(disp, false)) { + _eglError(EGL_NOT_INITIALIZED, "DRI2: failed to setup EGLDevice"); + goto cleanup; + } + dri2_setup_screen(disp); dri2_x11_setup_swap_interval(disp); @@ -1705,7 +1697,6 @@ static const __DRIextension *dri2_loader_extensions[] = { static EGLBoolean dri2_initialize_x11_dri2(_EGLDisplay *disp) { - _EGLDevice *dev; struct dri2_egl_display *dri2_dpy = dri2_display_create(); if (!dri2_dpy) return EGL_FALSE; @@ -1716,14 +1707,6 @@ dri2_initialize_x11_dri2(_EGLDisplay *disp) if (!dri2_x11_connect(dri2_dpy)) goto cleanup; - dev = _eglFindDevice(dri2_dpy->fd_render_gpu, false); - if (!dev) { - _eglError(EGL_NOT_INITIALIZED, "DRI2: failed to find EGLDevice"); - goto cleanup; - } - - disp->Device = dev; - if (!dri2_load_driver(disp)) goto cleanup; @@ -1741,6 +1724,11 @@ dri2_initialize_x11_dri2(_EGLDisplay *disp) if (!dri2_setup_extensions(disp)) goto cleanup; + if (!dri2_setup_device(disp, false)) { + _eglError(EGL_NOT_INITIALIZED, "DRI2: failed to setup EGLDevice"); + goto cleanup; + } + dri2_setup_screen(disp); dri2_x11_setup_swap_interval(disp); diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c index b9f179c2ce3..d50be23e871 100644 --- a/src/egl/main/eglapi.c +++ b/src/egl/main/eglapi.c @@ -695,7 +695,7 @@ eglInitialize(EGLDisplay dpy, EGLint *major, EGLint *minor) if (disp->Options.ForceSoftware) RETURN_EGL_ERROR(disp, EGL_NOT_INITIALIZED, EGL_FALSE); else { - bool success = disp->Options.Zink; + bool success = false; if (!disp->Options.Zink && !getenv("GALLIUM_DRIVER")) { disp->Options.Zink = EGL_TRUE; success = _eglDriver.Initialize(disp); diff --git a/src/egl/main/egldisplay.c b/src/egl/main/egldisplay.c index dd4926ce2ab..4eadb8f10aa 100644 --- a/src/egl/main/egldisplay.c +++ b/src/egl/main/egldisplay.c @@ -642,6 +642,7 @@ _EGLDisplay * _eglGetSurfacelessDisplay(void *native_display, const EGLAttrib *attrib_list) { _EGLDisplay *dpy; + _EGLDevice *dev = NULL; /* Any native display must be an EGLDeviceEXT we know about */ if (native_display != NULL) { @@ -657,8 +658,8 @@ _eglGetSurfacelessDisplay(void *native_display, const EGLAttrib *attrib_list) switch (attrib) { case EGL_DEVICE_EXT: - if ((native_display && native_display != (void *)value) || - (native_display != _eglLookupDevice(native_display))) { + dev = _eglLookupDevice((void *)value); + if (!dev) { _eglError(EGL_BAD_DEVICE_EXT, "eglGetPlatformDisplay"); return NULL; } @@ -671,10 +672,9 @@ _eglGetSurfacelessDisplay(void *native_display, const EGLAttrib *attrib_list) } } - dpy = - _eglFindDisplay(_EGL_PLATFORM_SURFACELESS, native_display, attrib_list); + dpy = _eglFindDisplay(_EGL_PLATFORM_SURFACELESS, NULL, attrib_list); if (dpy) { - dpy->Device = native_display; + dpy->Device = dev; } return dpy; diff --git a/src/egl/wayland/wayland-drm/meson.build b/src/egl/wayland/wayland-drm/meson.build index 442d7acd9b4..ac822acec67 100644 --- a/src/egl/wayland/wayland-drm/meson.build +++ b/src/egl/wayland/wayland-drm/meson.build @@ -67,13 +67,13 @@ wp_files = {} foreach name, xml : wp_protos code = custom_target( name + '-protocol.c', - input : join_paths(wp_dir, xml), + input : files(join_paths(wp_dir, xml)), output : name + '-protocol.c', command : [prog_wl_scanner, wl_scanner_arg, '@INPUT@', '@OUTPUT@'], ) header = custom_target( name + '-client-protocol.h', - input : join_paths(wp_dir, xml), + input : files(join_paths(wp_dir, xml)), output : name + '-client-protocol.h', command : [prog_wl_scanner, 'client-header', '@INPUT@', '@OUTPUT@'], ) diff --git a/src/freedreno/ci/freedreno-a530-fails.txt b/src/freedreno/ci/freedreno-a530-fails.txt index a009feb0186..3e130a15bf4 100644 --- a/src/freedreno/ci/freedreno-a530-fails.txt +++ b/src/freedreno/ci/freedreno-a530-fails.txt @@ -208,7 +208,6 @@ spec@arb_separate_shader_objects@400 combinations by location,Fail spec@arb_separate_shader_objects@400 combinations by name,Fail spec@arb_texture_rectangle@1-1-linear-texture,Fail spec@arb_timer_query@query gl_timestamp,Fail -spec@arb_timer_query@timestamp-get,Fail spec@arb_transform_feedback3@gl_skipcomponents1-1,Fail spec@arb_transform_feedback3@gl_skipcomponents1-2,Fail spec@arb_transform_feedback3@gl_skipcomponents1-3,Fail diff --git a/src/freedreno/ci/freedreno-a618-fails.txt b/src/freedreno/ci/freedreno-a618-fails.txt index 71e60f91197..29f0ad12c57 100644 --- a/src/freedreno/ci/freedreno-a618-fails.txt +++ b/src/freedreno/ci/freedreno-a618-fails.txt @@ -91,6 +91,7 @@ spec@arb_sample_shading@samplemask 4@noms mask_in_one,Fail spec@arb_sample_shading@samplemask 4@sample mask_in_one,Fail # Same results w/ zink-on-tu as with freedreno: +spec@arb_post_depth_coverage@arb_post_depth_coverage-multisampling,Fail spec@arb_sample_shading@samplemask 2 all@noms partition,Fail spec@arb_sample_shading@samplemask 2@noms partition,Fail spec@arb_sample_shading@samplemask 4 all@noms partition,Fail @@ -110,8 +111,6 @@ spec@arb_tessellation_shader@execution@variable-indexing@vs-output-array-dvec4-i spec@arb_texture_rectangle@1-1-linear-texture,Fail -spec@arb_timer_query@timestamp-get,Fail - spec@arb_vertex_type_2_10_10_10_rev@attrib-p-type-size-match,Fail # fails unrelated to GL_ARB_enhanced_layouts diff --git a/src/freedreno/ci/freedreno-a630-fails.txt b/src/freedreno/ci/freedreno-a630-fails.txt index ecd5de60ad2..c4c169bdc28 100644 --- a/src/freedreno/ci/freedreno-a630-fails.txt +++ b/src/freedreno/ci/freedreno-a630-fails.txt @@ -881,7 +881,6 @@ dEQP-VK.transform_feedback.primitives_generated_query.concurrent.pipeline_statis dEQP-VK.transform_feedback.primitives_generated_query.concurrent.pipeline_statistics_3.pgq_32bit_xfb_64bit.triangle_strip.indirect,Fail dEQP-VK.transform_feedback.primitives_generated_query.concurrent.pipeline_statistics_3.pgq_64bit_xfb_32bit.point_list.draw,Fail dEQP-VK.transform_feedback.primitives_generated_query.concurrent.pipeline_statistics_3.pgq_64bit_xfb_32bit.triangle_list_with_adjacency.indirect,Fail -dEQP-VK.transform_feedback.simple.backward_dependency_indirect_endqueryindexed_streamid_0,Fail dynamic-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d24_unorm_s8_uint.compatibility_depth_zero_stencil_zero_testing_stencil,Fail gmem-dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image.all_formats.color.2d_to_1d.b4g4r4a4_unorm_pack16.r16_sfloat.optimal_general,Fail gmem-dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image.all_formats.color.2d_to_1d.r16_uint.r16_sfloat.optimal_optimal,Fail diff --git a/src/freedreno/ci/freedreno-a660-fails.txt b/src/freedreno/ci/freedreno-a660-fails.txt index 1b9f84e05c8..dc061f802b3 100644 --- a/src/freedreno/ci/freedreno-a660-fails.txt +++ b/src/freedreno/ci/freedreno-a660-fails.txt @@ -5,34 +5,12 @@ KHR-GL46.shader_image_load_store.basic-allTargets-store,Fail KHR-GL46.shader_subroutine.control_flow_and_returned_subroutine_values_used_as_subroutine_input,Fail KHR-GL46.tessellation_shader.single.max_patch_vertices,Fail -# https://gitlab.freedesktop.org/mesa/mesa/-/issues/8886 -dEQP-GLES31.functional.synchronization.inter_invocation.image_atomic_read_write,Crash - - # Fails when TU_DEBUG=forcebin is set gmem-dEQP-VK.spirv_assembly.instruction.graphics.variable_pointers.graphics.writes_two_buffers_vert,Fail dEQP-VK.binding_model.descriptor_buffer.basic.limits,Fail gmem-dEQP-VK.binding_model.descriptor_buffer.basic.limits,Fail -dEQP-VK.subgroups.vote.frag_helper.subgroupallequal_bvec2_fragment,Fail -dEQP-VK.subgroups.vote.frag_helper.subgroupallequal_bvec3_fragment,Fail -dEQP-VK.subgroups.vote.frag_helper.subgroupallequal_bvec4_fragment,Fail -dEQP-VK.subgroups.vote.frag_helper.subgroupallequal_float_fragment,Fail -dEQP-VK.subgroups.vote.frag_helper.subgroupallequal_ivec2_fragment,Fail -dEQP-VK.subgroups.vote.frag_helper.subgroupallequal_ivec3_fragment,Fail -dEQP-VK.subgroups.vote.frag_helper.subgroupallequal_ivec4_fragment,Fail -dEQP-VK.subgroups.vote.frag_helper.subgroupallequal_uvec2_fragment,Fail -dEQP-VK.subgroups.vote.frag_helper.subgroupallequal_uvec3_fragment,Fail -dEQP-VK.subgroups.vote.frag_helper.subgroupallequal_uvec4_fragment,Fail -dEQP-VK.subgroups.vote.frag_helper.subgroupallequal_vec2_fragment,Fail -dEQP-VK.subgroups.vote.frag_helper.subgroupallequal_vec3_fragment,Fail -dEQP-VK.subgroups.vote.frag_helper.subgroupallequal_vec4_fragment,Fail -gmem-dEQP-VK.subgroups.vote.frag_helper.subgroupallequal_ivec4_fragment,Fail -gmem-dEQP-VK.subgroups.vote.frag_helper.subgroupallequal_uvec2_fragment,Fail -gmem-dEQP-VK.subgroups.vote.frag_helper.subgroupallequal_vec2_fragment,Fail -gmem-dEQP-VK.subgroups.vote.frag_helper.subgroupallequal_vec4_fragment,Fail - # New CTS fails in 1.3.6.3 gmem-dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage:struct_mixed_types.uniform_buffer_block_geom,Fail gmem-dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.struct_mixed_types.uniform_buffer_block_geom,Fail @@ -1057,8 +1035,6 @@ dEQP-VK.transform_feedback.primitives_generated_query.concurrent.pipeline_statis dEQP-VK.transform_feedback.primitives_generated_query.concurrent.pipeline_statistics_3.pgq_64bit_xfb_32bit.triangle_strip.indirect,Fail dEQP-VK.transform_feedback.primitives_generated_query.concurrent.pipeline_statistics_3.pgq_64bit_xfb_32bit.triangle_strip_with_adjacency.draw,Fail dEQP-VK.transform_feedback.primitives_generated_query.concurrent.pipeline_statistics_3.pgq_64bit_xfb_32bit.triangle_strip_with_adjacency.indirect,Fail -dEQP-VK.transform_feedback.simple.backward_dependency_indirect_beginqueryindexed_streamid_0,Fail -dEQP-VK.transform_feedback.simple.backward_dependency_indirect_no_offset_array,Fail gmem-dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image.all_formats.color.2d_to_1d.b4g4r4a4_unorm_pack16.r16_sfloat.general_general,Fail gmem-dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image.all_formats.color.2d_to_1d.b4g4r4a4_unorm_pack16.r16_sfloat.optimal_general,Fail gmem-dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image.all_formats.color.2d_to_1d.b4g4r4a4_unorm_pack16.r16_sfloat.optimal_optimal,Fail diff --git a/src/freedreno/ci/traces-freedreno.yml b/src/freedreno/ci/traces-freedreno.yml index 6887ae78ef0..2aca3af1dd7 100644 --- a/src/freedreno/ci/traces-freedreno.yml +++ b/src/freedreno/ci/traces-freedreno.yml @@ -16,7 +16,6 @@ text: |- stk: 11.15s 0ad: 10.93s counterstrike: 9.87s - minetest: 8.24s neverball: 8.53s traces: @@ -234,39 +233,6 @@ traces: zink-a630: checksum: d25edb433abfcde517b626b3071906ff - minetest/minetest-high-v2.trace: - freedreno-a306: - label: [crash] - freedreno-a530: - checksum: 48d4d4776885fd120429cd36a35ddaf2 - freedreno-a618: - checksum: 2aebe86d6c0488b953bfaacd8000c01a - freedreno-a630: - checksum: 2aebe86d6c0488b953bfaacd8000c01a - zink-a618: - label: [skip, flakes] - checksum: c167b29121b4bbba7675070b2ab1f51a - zink-a630: - label: [skip, flakes] - checksum: c167b29121b4bbba7675070b2ab1f51a - - minetest/minetest-v2.trace: - freedreno-a306: - checksum: 37081a69137df415cfda13dac62966c4 - freedreno-a530: - checksum: 824672b1eef72c0223ac754dfc46e2d5 - freedreno-a618: - checksum: e9b5d984b49f888ff1a4787fe2baea71 - freedreno-a630: - label: [skip, flakes] - checksum: 1db3e8a057748109bd06734860396abf - zink-a618: - checksum: f534d68a62934453325f11ff19e2241a - zink-a630: - label: [skip, flakes] - checksum: f534d68a62934453325f11ff19e2241a - text: occasional Different pixels 1 (no tolerance), 0 (1% tol.) - filament/filament-default.trace: freedreno-a306: label: [unsupported] @@ -738,27 +704,6 @@ traces: label: [skip, flakes] text: Inconsistent rendering, but looks good. - freedoom/freedoom-phase2-gl-high.trace: - freedreno-a306: - label: [unsupported] - freedreno-a530: - label: [unsupported] - text: needs GL 4.6 - freedreno-a618: - checksum: a2dbcd27c404a1bb0f7d60476d93d22c - freedreno-a630: - checksum: a2dbcd27c404a1bb0f7d60476d93d22c - zink-a618: - label: [crash] - text: |- - ../src/gallium/drivers/zink/zink_context.c:541: update_descriptor_state_ubo: - Assertion `ctx->di.ubos[shader][slot].range <= screen->info.props.limits.maxUniformBufferRange' failed. - zink-a630: - label: [crash] - text: |- - ../src/gallium/drivers/zink/zink_context.c:541: update_descriptor_state_ubo: - Assertion `ctx->di.ubos[shader][slot].range <= screen->info.props.limits.maxUniformBufferRange' failed. - unvanquished/unvanquished-lowest.trace: freedreno-a306: label: [skip] diff --git a/src/freedreno/drm/freedreno_bo.c b/src/freedreno/drm/freedreno_bo.c index 3f15f52e799..7f4b57a6e56 100644 --- a/src/freedreno/drm/freedreno_bo.c +++ b/src/freedreno/drm/freedreno_bo.c @@ -61,15 +61,21 @@ lookup_bo(struct hash_table *tbl, uint32_t key) * remove an object it is about to free. Fortunately since table * lookup and removal are protected by the same lock (and table * removal happens before obj free) we can easily detect this by - * checking for refcnt==0. + * checking for refcnt==0 (ie. 1 after p_atomic_inc_return). */ - if (bo->refcnt == 0) { + if (p_atomic_inc_return(&bo->refcnt) == 1) { + /* Restore the zombified reference count, so if another thread + * that ends up calling lookup_bo() gets the table_lock before + * the thread deleting the bo does, it doesn't mistakenly see + * that the BO is live. + * + * We are holding the table_lock here so we can't be racing + * with another caller of lookup_bo() + */ + p_atomic_dec(&bo->refcnt); return &zombie; } - /* found, incr refcnt and return: */ - fd_bo_ref(bo); - if (!list_is_empty(&bo->node)) { mesa_logw("bo was in cache, size=%u, alloc_flags=0x%x\n", bo->size, bo->alloc_flags); diff --git a/src/freedreno/ir3/ir3_legalize.c b/src/freedreno/ir3/ir3_legalize.c index 604e5bf2962..e7db858ba28 100644 --- a/src/freedreno/ir3/ir3_legalize.c +++ b/src/freedreno/ir3/ir3_legalize.c @@ -998,6 +998,7 @@ helper_sched(struct ir3_legalize_ctx *ctx, struct ir3 *ir, if (block->brtype == IR3_BRANCH_ALL || block->brtype == IR3_BRANCH_ANY || block->brtype == IR3_BRANCH_GETONE) { + bd->uses_helpers_beginning = true; bd->uses_helpers_end = true; } diff --git a/src/freedreno/ir3/ir3_ra.c b/src/freedreno/ir3/ir3_ra.c index 0ec4530d48e..6ad5b8c1902 100644 --- a/src/freedreno/ir3/ir3_ra.c +++ b/src/freedreno/ir3/ir3_ra.c @@ -879,9 +879,13 @@ try_evict_regs(struct ra_ctx *ctx, struct ra_file *file, if (evicted) continue; - /* If we couldn't evict this range, we may be able to swap it with a - * killed range to acheive the same effect. + /* If we couldn't evict this range, but the register we're allocating is + * allowed to overlap with a killed range, then we may be able to swap it + * with a killed range to acheive the same effect. */ + if (is_early_clobber(reg) || is_source) + return false; + foreach_interval (killed, file) { if (!killed->is_killed) continue; diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc index f07e8615735..4aa3ab770d0 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.cc +++ b/src/freedreno/vulkan/tu_cmd_buffer.cc @@ -1610,6 +1610,11 @@ tu_emit_renderpass_begin(struct tu_cmd_buffer *cmd) */ BITSET_SET(cmd->vk.dynamic_graphics_state.dirty, MESA_VK_DYNAMIC_MS_RASTERIZATION_SAMPLES); + /* PC_PRIMITIVE_CNTL_0 isn't a part of a draw state and may be changed + * by blits. + */ + BITSET_SET(cmd->vk.dynamic_graphics_state.dirty, + MESA_VK_DYNAMIC_IA_PRIMITIVE_RESTART_ENABLE); } template @@ -4971,10 +4976,12 @@ tu6_emit_vs_params(struct tu_cmd_buffer *cmd, uint32_t offset = vs_params_offset(cmd); /* Beside re-emitting params when they are changed, we should re-emit - * them after constants are invalidated via HLSQ_INVALIDATE_CMD. + * them after constants are invalidated via HLSQ_INVALIDATE_CMD or after we + * emit an empty vs params. */ if (!(cmd->state.dirty & (TU_CMD_DIRTY_DRAW_STATE | TU_CMD_DIRTY_VS_PARAMS | TU_CMD_DIRTY_PROGRAM)) && + cmd->state.vs_params.iova && (offset == 0 || draw_id == cmd->state.last_vs_params.draw_id) && vertex_offset == cmd->state.last_vs_params.vertex_offset && first_instance == cmd->state.last_vs_params.first_instance) { diff --git a/src/freedreno/vulkan/tu_knl_drm_msm.cc b/src/freedreno/vulkan/tu_knl_drm_msm.cc index 3a5e3563bd6..e8fe7a9f82c 100644 --- a/src/freedreno/vulkan/tu_knl_drm_msm.cc +++ b/src/freedreno/vulkan/tu_knl_drm_msm.cc @@ -1028,6 +1028,7 @@ msm_queue_submit(struct tu_queue *queue, struct vk_queue_submit *submit) in_syncobjs[nr_in_syncobjs++] = (struct drm_msm_gem_submit_syncobj) { .handle = tu_syncobj_from_vk_sync(sync), .flags = 0, + .point = submit->waits[i].wait_value, }; } @@ -1037,6 +1038,7 @@ msm_queue_submit(struct tu_queue *queue, struct vk_queue_submit *submit) out_syncobjs[nr_out_syncobjs++] = (struct drm_msm_gem_submit_syncobj) { .handle = tu_syncobj_from_vk_sync(sync), .flags = 0, + .point = submit->signals[i].signal_value, }; } diff --git a/src/freedreno/vulkan/tu_knl_drm_virtio.cc b/src/freedreno/vulkan/tu_knl_drm_virtio.cc index 8f43bf83a99..d944d079dd4 100644 --- a/src/freedreno/vulkan/tu_knl_drm_virtio.cc +++ b/src/freedreno/vulkan/tu_knl_drm_virtio.cc @@ -1445,6 +1445,7 @@ virtio_queue_submit(struct tu_queue *queue, struct vk_queue_submit *submit) in_syncobjs[nr_in_syncobjs++] = (struct drm_virtgpu_execbuffer_syncobj) { .handle = tu_syncobj_from_vk_sync(sync), .flags = 0, + .point = submit->waits[i].wait_value, }; } @@ -1454,6 +1455,7 @@ virtio_queue_submit(struct tu_queue *queue, struct vk_queue_submit *submit) out_syncobjs[nr_out_syncobjs++] = (struct drm_virtgpu_execbuffer_syncobj) { .handle = tu_syncobj_from_vk_sync(sync), .flags = 0, + .point = submit->signals[i].signal_value, }; } diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp index e213f7e4be1..a5e84d708f2 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp +++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp @@ -62,6 +62,7 @@ #include #include #include +#include #if LLVM_VERSION_MAJOR >= 15 #include #endif @@ -100,6 +101,8 @@ #include "lp_bld_misc.h" #include "lp_bld_debug.h" +static void lp_run_atexit_for_destructors(void); + namespace { class LLVMEnsureMultithreaded { @@ -147,6 +150,7 @@ static void init_native_targets() } } #endif + lp_run_atexit_for_destructors(); } extern "C" void @@ -623,3 +627,33 @@ lp_set_module_stack_alignment_override(LLVMModuleRef MRef, unsigned align) M->setOverrideStackAlignment(align); #endif } + +using namespace llvm; + +class GallivmRunAtExitForStaticDestructors : public SDNode +{ +public: + /* getSDVTList (protected) calls getValueTypeList (private), which contains static variables. */ + GallivmRunAtExitForStaticDestructors(): SDNode(0, 0, DebugLoc(), getSDVTList(MVT::Other)) + { + } +}; + +static void +lp_run_atexit_for_destructors(void) +{ + /* LLVM >= 16 registers static variable destructors on the first compile, which gcc + * implements by calling atexit there. Before that, u_queue registers its atexit + * handler to kill all threads. Since exit() runs atexit handlers in the reverse order, + * the LLVM destructors are called first while shader compiler threads may still be + * running, which crashes in LLVM in SelectionDAG.cpp. + * + * The solution is to run the code that declares the LLVM static variables first, + * so that atexit for LLVM is registered first and u_queue is registered after that, + * which ensures that all u_queue threads are terminated before LLVM destructors are + * called. + * + * This just executes the code that declares static variables. + */ + GallivmRunAtExitForStaticDestructors(); +} diff --git a/src/gallium/auxiliary/nir/nir_to_tgsi.c b/src/gallium/auxiliary/nir/nir_to_tgsi.c index 521a643d0fb..4cf7fbc20c4 100644 --- a/src/gallium/auxiliary/nir/nir_to_tgsi.c +++ b/src/gallium/auxiliary/nir/nir_to_tgsi.c @@ -3898,6 +3898,15 @@ const void *nir_to_tgsi_options(struct nir_shader *s, NIR_PASS_V(s, nir_remove_dead_variables, nir_var_shader_in, NULL); } + /* Lower tesslevel indirect derefs for tessellation shader. + * tesslevels are now a compact array variable and nir expects a constant + * array index into the compact array variable. + */ + if (s->info.stage == MESA_SHADER_TESS_CTRL || + s->info.stage == MESA_SHADER_TESS_EVAL) { + NIR_PASS_V(s, nir_lower_indirect_derefs, 0 , UINT32_MAX); + } + NIR_PASS_V(s, nir_lower_io, nir_var_shader_in | nir_var_shader_out, type_size, (nir_lower_io_options)0); diff --git a/src/gallium/auxiliary/util/u_compute.c b/src/gallium/auxiliary/util/u_compute.c index df00df52585..518f628d55d 100644 --- a/src/gallium/auxiliary/util/u_compute.c +++ b/src/gallium/auxiliary/util/u_compute.c @@ -106,8 +106,10 @@ void util_compute_blit(struct pipe_context *ctx, struct pipe_blit_info *blit_inf blit_info->dst.box.y, blit_info->dst.box.z, 0, - u_bitcast_f2u((blit_info->src.box.width - 0.5) / (float)src->width0), - u_bitcast_f2u((blit_info->src.box.height - 0.5) / (float)src->height0), + u_bitcast_f2u((blit_info->src.box.x + blit_info->src.box.width - 0.5) / + (float)src->width0), + u_bitcast_f2u((blit_info->src.box.y + blit_info->src.box.height - 0.5) / + (float)src->height0), 0, 0}; diff --git a/src/gallium/auxiliary/util/u_resource.c b/src/gallium/auxiliary/util/u_resource.c index b27c3f3c80b..728a662f09b 100644 --- a/src/gallium/auxiliary/util/u_resource.c +++ b/src/gallium/auxiliary/util/u_resource.c @@ -64,3 +64,35 @@ util_resource_size(const struct pipe_resource *res) return size; } + +/** + * Return the number of the resources. + */ +unsigned +util_resource_num(const struct pipe_resource *res) +{ + const struct pipe_resource *cur; + unsigned count; + + for (count = 0, cur = res; cur; cur = cur->next) + count++; + + return count; +} + +/** + * Return the resource at the given index. + */ +struct pipe_resource * +util_resource_at_index(const struct pipe_resource *res, unsigned index) +{ + const struct pipe_resource *cur; + unsigned count; + + for (count = 0, cur = res; cur; cur = cur->next) { + if (count++ == index) + return (struct pipe_resource *)cur; + } + + return NULL; +} diff --git a/src/gallium/auxiliary/util/u_resource.h b/src/gallium/auxiliary/util/u_resource.h index fe9c1c4d7f0..32e9d158ad0 100644 --- a/src/gallium/auxiliary/util/u_resource.h +++ b/src/gallium/auxiliary/util/u_resource.h @@ -31,6 +31,12 @@ unsigned util_resource_size(const struct pipe_resource *res); +unsigned +util_resource_num(const struct pipe_resource *res); + +struct pipe_resource * +util_resource_at_index(const struct pipe_resource *res, unsigned index); + /** * Return true if the texture target is an array type. * diff --git a/src/gallium/auxiliary/util/u_transfer_helper.c b/src/gallium/auxiliary/util/u_transfer_helper.c index ec38b8d6706..9d5b7c4b1df 100644 --- a/src/gallium/auxiliary/util/u_transfer_helper.c +++ b/src/gallium/auxiliary/util/u_transfer_helper.c @@ -208,6 +208,10 @@ transfer_map_msaa(struct pipe_context *pctx, .depth0 = 1, .array_size = 1, }; + if (util_format_is_depth_or_stencil(tmpl.format)) + tmpl.bind |= PIPE_BIND_DEPTH_STENCIL; + else + tmpl.bind |= PIPE_BIND_RENDER_TARGET; trans->ss = pscreen->resource_create(pscreen, &tmpl); if (!trans->ss) { free(trans); diff --git a/src/gallium/auxiliary/vl/vl_compositor.c b/src/gallium/auxiliary/vl/vl_compositor.c index 91a10a678c4..4d791f1afb6 100644 --- a/src/gallium/auxiliary/vl/vl_compositor.c +++ b/src/gallium/auxiliary/vl/vl_compositor.c @@ -691,6 +691,8 @@ vl_compositor_yuv_deint_full(struct vl_compositor_state *s, vl_compositor_render(s, c, dst_surfaces[0], NULL, false); if (dst_rect) { + dst_rect->x0 /= 2; + dst_rect->y0 /= 2; dst_rect->x1 /= 2; dst_rect->y1 /= 2; } @@ -727,6 +729,8 @@ vl_compositor_convert_rgb_to_yuv(struct vl_compositor_state *s, vl_compositor_render(s, c, dst_surfaces[0], NULL, false); if (dst_rect) { + dst_rect->x0 /= 2; + dst_rect->y0 /= 2; dst_rect->x1 /= 2; dst_rect->y1 /= 2; } diff --git a/src/gallium/auxiliary/vl/vl_compositor_cs.c b/src/gallium/auxiliary/vl/vl_compositor_cs.c index 3f4f0cee79c..35755081f26 100644 --- a/src/gallium/auxiliary/vl/vl_compositor_cs.c +++ b/src/gallium/auxiliary/vl/vl_compositor_cs.c @@ -956,14 +956,10 @@ draw_layers(struct vl_compositor *c, drawn.translate_y = layer->viewport.translate[1]; drawn.sampler0_w = (float)layer->sampler_views[0]->texture->width0; drawn.sampler0_h = (float)layer->sampler_views[0]->texture->height0; - drawn.clamp_x = (float)samplers[0]->texture->width0 * - (layer->src.br.x - layer->src.tl.x) - 0.5; - drawn.clamp_y = (float)samplers[0]->texture->height0 * - (layer->src.br.y - layer->src.tl.y) - 0.5; - drawn.chroma_clamp_x = (float)sampler1->texture->width0 * - (layer->src.br.x - layer->src.tl.x) - 0.5; - drawn.chroma_clamp_y = (float)sampler1->texture->height0 * - (layer->src.br.y - layer->src.tl.y) - 0.5; + drawn.clamp_x = (float)samplers[0]->texture->width0 * layer->src.br.x - 0.5; + drawn.clamp_y = (float)samplers[0]->texture->height0 * layer->src.br.y - 0.5; + drawn.chroma_clamp_x = (float)sampler1->texture->width0 * layer->src.br.x - 0.5; + drawn.chroma_clamp_y = (float)sampler1->texture->height0 * layer->src.br.y - 0.5; drawn.chroma_offset_x = chroma_offset_x(s->chroma_location); drawn.chroma_offset_y = chroma_offset_y(s->chroma_location); set_viewport(s, &drawn, samplers); diff --git a/src/gallium/auxiliary/vl/vl_video_buffer.c b/src/gallium/auxiliary/vl/vl_video_buffer.c index a3d6109c335..4d95f762510 100644 --- a/src/gallium/auxiliary/vl/vl_video_buffer.c +++ b/src/gallium/auxiliary/vl/vl_video_buffer.c @@ -296,13 +296,19 @@ vl_video_buffer_sampler_view_components(struct pipe_video_buffer *buffer) nr_components = 3; for (j = 0; j < nr_components && component < VL_NUM_COMPONENTS; ++j, ++component) { + unsigned pipe_swizzle; + if (buf->sampler_view_components[component]) continue; memset(&sv_templ, 0, sizeof(sv_templ)); u_sampler_view_default_template(&sv_templ, res, sampler_format[plane_order[i]]); - sv_templ.swizzle_r = sv_templ.swizzle_g = sv_templ.swizzle_b = PIPE_SWIZZLE_X + j; + pipe_swizzle = (buf->base.buffer_format == PIPE_FORMAT_YUYV || buf->base.buffer_format == PIPE_FORMAT_UYVY) ? + (PIPE_SWIZZLE_X + j + 1) % 3 : + (PIPE_SWIZZLE_X + j); + sv_templ.swizzle_r = sv_templ.swizzle_g = sv_templ.swizzle_b = pipe_swizzle; sv_templ.swizzle_a = PIPE_SWIZZLE_1; + buf->sampler_view_components[component] = pipe->create_sampler_view(pipe, res, &sv_templ); if (!buf->sampler_view_components[component]) goto error; diff --git a/src/gallium/drivers/crocus/ci/traces-crocus.yml b/src/gallium/drivers/crocus/ci/traces-crocus.yml index 4da4f03293d..fac535e6009 100644 --- a/src/gallium/drivers/crocus/ci/traces-crocus.yml +++ b/src/gallium/drivers/crocus/ci/traces-crocus.yml @@ -164,13 +164,6 @@ traces: label: [unsupported] crocus-hsw: checksum: c07530897dc5a6882cbf35737334336b - freedoom/freedoom-phase2-gl-high.trace: - crocus-g41: - label: [unsupported] - crocus-hsw: - label: [skip, crash] - checksum: 997ec70d945fdbda8a98efe831000338 - text: "abort() called" unvanquished/unvanquished-lowest.trace: crocus-g41: label: [unsupported] diff --git a/src/gallium/drivers/crocus/crocus_bufmgr.c b/src/gallium/drivers/crocus/crocus_bufmgr.c index 62333703996..e8b4220be3f 100644 --- a/src/gallium/drivers/crocus/crocus_bufmgr.c +++ b/src/gallium/drivers/crocus/crocus_bufmgr.c @@ -895,7 +895,9 @@ crocus_bo_map_cpu(struct util_debug_callback *dbg, * LLC entirely requiring us to keep dirty pixels for the scanout * out of any cache.) */ +#ifdef SUPPORT_INTEL_INTEGRATED_GPUS intel_invalidate_range(bo->map_cpu, bo->size); +#endif } return bo->map_cpu; diff --git a/src/gallium/drivers/d3d12/d3d12_bufmgr.h b/src/gallium/drivers/d3d12/d3d12_bufmgr.h index ee70fa6bde0..78f716fb508 100644 --- a/src/gallium/drivers/d3d12/d3d12_bufmgr.h +++ b/src/gallium/drivers/d3d12/d3d12_bufmgr.h @@ -71,7 +71,7 @@ struct d3d12_bo { uint8_t local_reference_mask[16]; d3d12_context_state_table_entry local_context_states[16]; - uint8_t local_reference_state[8][16]; + uint8_t local_reference_state[16][8]; }; struct d3d12_buffer { diff --git a/src/gallium/drivers/d3d12/d3d12_context.cpp b/src/gallium/drivers/d3d12/d3d12_context.cpp index 8e0a7753a53..85940d29a4c 100644 --- a/src/gallium/drivers/d3d12/d3d12_context.cpp +++ b/src/gallium/drivers/d3d12/d3d12_context.cpp @@ -105,6 +105,7 @@ d3d12_context_destroy(struct pipe_context *pctx) slab_destroy_child(&ctx->transfer_pool); slab_destroy_child(&ctx->transfer_pool_unsync); d3d12_gs_variant_cache_destroy(ctx); + d3d12_tcs_variant_cache_destroy(ctx); d3d12_gfx_pipeline_state_cache_destroy(ctx); d3d12_compute_pipeline_state_cache_destroy(ctx); d3d12_root_signature_cache_destroy(ctx); diff --git a/src/gallium/drivers/d3d12/d3d12_screen.cpp b/src/gallium/drivers/d3d12/d3d12_screen.cpp index 4377361f826..86faa25a074 100644 --- a/src/gallium/drivers/d3d12/d3d12_screen.cpp +++ b/src/gallium/drivers/d3d12/d3d12_screen.cpp @@ -1185,10 +1185,9 @@ d3d12_get_node_mask(struct pipe_screen *pscreen) static void d3d12_create_fence_win32(struct pipe_screen *pscreen, struct pipe_fence_handle **pfence, void *handle, const void *name, enum pipe_fd_type type) { - d3d12_fence_reference((struct d3d12_fence **)pfence, - type == PIPE_FD_TYPE_TIMELINE_SEMAPHORE ? - d3d12_open_fence(d3d12_screen(pscreen), handle, name) : - nullptr); + d3d12_fence_reference((struct d3d12_fence **)pfence, nullptr); + if(type == PIPE_FD_TYPE_TIMELINE_SEMAPHORE) + *pfence = (struct pipe_fence_handle*) d3d12_open_fence(d3d12_screen(pscreen), handle, name); } static void diff --git a/src/gallium/drivers/d3d12/d3d12_video_buffer.cpp b/src/gallium/drivers/d3d12/d3d12_video_buffer.cpp index a801ce11c0f..14dc1a6156d 100644 --- a/src/gallium/drivers/d3d12/d3d12_video_buffer.cpp +++ b/src/gallium/drivers/d3d12/d3d12_video_buffer.cpp @@ -73,10 +73,20 @@ d3d12_video_buffer_create_impl(struct pipe_context *pipe, templ.target = PIPE_TEXTURE_2D; templ.bind = pD3D12VideoBuffer->base.bind; templ.format = pD3D12VideoBuffer->base.buffer_format; - // YUV 4:2:0 formats in D3D12 need to at least be multiple of 2 dimensions - // However, we allocate with a higher alignment to maximize HW compatibility - templ.width0 = align(pD3D12VideoBuffer->base.width, 2); - templ.height0 = align(pD3D12VideoBuffer->base.height, 16); + if (handle) + { + // YUV 4:2:0 formats in D3D12 always require multiple of 2 dimensions + // We must respect the input dimensions of the imported resource handle (e.g no extra aligning) + templ.width0 = align(pD3D12VideoBuffer->base.width, 2); + templ.height0 = align(pD3D12VideoBuffer->base.height, 2); + } + else + { + // When creating (e.g not importing) resources we allocate + // with a higher alignment to maximize HW compatibility + templ.width0 = align(pD3D12VideoBuffer->base.width, 2); + templ.height0 = align(pD3D12VideoBuffer->base.height, 16); + } templ.depth0 = 1; templ.array_size = 1; templ.flags = 0; diff --git a/src/gallium/drivers/d3d12/d3d12_video_enc_av1.cpp b/src/gallium/drivers/d3d12/d3d12_video_enc_av1.cpp index 2c1964aa274..a5e2a2e3d39 100644 --- a/src/gallium/drivers/d3d12/d3d12_video_enc_av1.cpp +++ b/src/gallium/drivers/d3d12/d3d12_video_enc_av1.cpp @@ -2189,7 +2189,7 @@ d3d12_video_encoder_build_post_encode_codec_bitstream_av1(struct d3d12_video_enc writtenTemporalDelimBytes // Bytes Written AFTER placingPositionStart arg above ); assert(pD3D12Enc->m_BitstreamHeadersBuffer.size() == writtenTemporalDelimBytes); - debug_printf("Written OBU_TEMPORAL_DELIMITER bytes: %" PRIu64 "\n", writtenTemporalDelimBytes); + debug_printf("Written OBU_TEMPORAL_DELIMITER bytes: %" PRIu64 "\n", static_cast(writtenTemporalDelimBytes)); } size_t writtenSequenceBytes = 0; @@ -2208,7 +2208,7 @@ d3d12_video_encoder_build_post_encode_codec_bitstream_av1(struct d3d12_video_enc writtenSequenceBytes // Bytes Written AFTER placingPositionStart arg above ); assert(pD3D12Enc->m_BitstreamHeadersBuffer.size() == (writtenSequenceBytes + writtenTemporalDelimBytes)); - debug_printf("Written OBU_SEQUENCE_HEADER bytes: %" PRIu64 "\n", writtenSequenceBytes); + debug_printf("Written OBU_SEQUENCE_HEADER bytes: %" PRIu64 "\n", static_cast(writtenSequenceBytes)); } // Only supported bitstream format is with obu_size for now. @@ -2254,14 +2254,14 @@ d3d12_video_encoder_build_post_encode_codec_bitstream_av1(struct d3d12_video_enc writtenFrameBytes // Bytes Written AFTER placingPositionStart arg above ); - debug_printf("Written OBU_FRAME bytes: %" PRIu64 "\n", writtenFrameBytes); + debug_printf("Written OBU_FRAME bytes: %" PRIu64 "\n", static_cast(writtenFrameBytes)); assert(pD3D12Enc->m_BitstreamHeadersBuffer.size() == (writtenSequenceBytes + writtenTemporalDelimBytes + writtenFrameBytes)); debug_printf("Uploading %" PRIu64 " bytes from OBU sequence and/or picture headers to comp_bit_destination %p at offset 0\n", - pD3D12Enc->m_BitstreamHeadersBuffer.size(), + static_cast(pD3D12Enc->m_BitstreamHeadersBuffer.size()), associatedMetadata.comp_bit_destination); // Upload headers to the finalized compressed bitstream buffer @@ -2330,13 +2330,13 @@ d3d12_video_encoder_build_post_encode_codec_bitstream_av1(struct d3d12_video_enc writtenFrameBytes // Bytes Written AFTER placingPositionStart arg above ); - debug_printf("Written OBU_FRAME_HEADER bytes: %" PRIu64 "\n", writtenFrameBytes); + debug_printf("Written OBU_FRAME_HEADER bytes: %" PRIu64 "\n", static_cast(writtenFrameBytes)); assert(pD3D12Enc->m_BitstreamHeadersBuffer.size() == (writtenSequenceBytes + writtenTemporalDelimBytes + writtenFrameBytes)); debug_printf("Uploading %" PRIu64 " bytes from OBU headers to comp_bit_destination %p at offset 0\n", - pD3D12Enc->m_BitstreamHeadersBuffer.size(), + static_cast(pD3D12Enc->m_BitstreamHeadersBuffer.size()), associatedMetadata.comp_bit_destination); // Upload headers to the finalized compressed bitstream buffer @@ -2361,7 +2361,7 @@ d3d12_video_encoder_build_post_encode_codec_bitstream_av1(struct d3d12_video_enc debug_printf("Uploading tile group %d to comp_bit_destination %p at offset %" PRIu64 "\n", tg_idx, associatedMetadata.comp_bit_destination, - comp_bitstream_offset); + static_cast(comp_bitstream_offset)); size_t tile_group_obu_size = 0; size_t decode_tile_elements_size = 0; @@ -2387,9 +2387,9 @@ d3d12_video_encoder_build_post_encode_codec_bitstream_av1(struct d3d12_video_enc debug_printf("Written %" PRIu64 " bytes for OBU_TILE_GROUP open_bitstream_unit() prefix with obu_header() and " "obu_size to staging_bitstream_buffer %p at offset %" PRIu64 "\n", - writtenTileObuPrefixBytes, + static_cast(writtenTileObuPrefixBytes), associatedMetadata.m_StagingBitstreamConstruction.data(), - staging_bitstream_buffer_offset); + static_cast(staging_bitstream_buffer_offset)); writtenTileBytes += writtenTileObuPrefixBytes; @@ -2404,10 +2404,10 @@ d3d12_video_encoder_build_post_encode_codec_bitstream_av1(struct d3d12_video_enc debug_printf("Uploading %" PRIu64 " bytes for OBU_TILE_GROUP open_bitstream_unit() prefix with obu_header() " "and obu_size: %" PRIu64 " to comp_bit_destination %p at offset %" PRIu64 "\n", - writtenTileObuPrefixBytes, - tile_group_obu_size, + static_cast(writtenTileObuPrefixBytes), + static_cast(tile_group_obu_size), associatedMetadata.comp_bit_destination, - comp_bitstream_offset); + static_cast(comp_bitstream_offset)); staging_bitstream_buffer_offset += writtenTileObuPrefixBytes; @@ -2517,7 +2517,7 @@ d3d12_video_encoder_build_post_encode_codec_bitstream_av1(struct d3d12_video_enc // Add current pending frame being processed in the loop extra_show_existing_frame_payload_bytes += writtenTemporalDelimBytes; - debug_printf("Written OBU_TEMPORAL_DELIMITER bytes: %" PRIu64 "\n", writtenTemporalDelimBytes); + debug_printf("Written OBU_TEMPORAL_DELIMITER bytes: %" PRIu64 "\n", static_cast(writtenTemporalDelimBytes)); size_t writtenShowExistingFrameBytes = 0; av1_pic_header_t showExistingPicHdr = {}; @@ -2561,7 +2561,7 @@ d3d12_video_encoder_build_post_encode_codec_bitstream_av1(struct d3d12_video_enc "in current frame ref_frame_idx[%" PRIu32 "]) bytes: %" PRIu64 "\n", *pendingFrameIt /*PictureIndex*/, showExistingPicHdr.frame_to_show_map_idx, - writtenShowExistingFrameBytes); + static_cast(writtenShowExistingFrameBytes)); // Remove it from the list of pending frames pendingFrameIt = @@ -2628,7 +2628,7 @@ upload_tile_group_obu(struct d3d12_video_encoder *pD3D12Enc, tileGroup.tg_start, tileGroup.tg_end, comp_bit_destination, - comp_bit_destination_offset); + static_cast(comp_bit_destination_offset)); debug_printf("[Tile group start %d to end %d] Using staging_bitstream_buffer %p at offset %" PRIu64 " to write the tile_obu_group() prefix syntax: tile_start_and_end_present_flag, tg_start, tg_end and " @@ -2636,7 +2636,7 @@ upload_tile_group_obu(struct d3d12_video_encoder *pD3D12Enc, tileGroup.tg_start, tileGroup.tg_end, staging_bitstream_buffer.data(), - staging_bitstream_buffer_offset); + static_cast(staging_bitstream_buffer_offset)); // Reserve space upfront in the scratch storage // Do not modify anything before staging_bitstream_buffer_offset @@ -2673,9 +2673,9 @@ upload_tile_group_obu(struct d3d12_video_encoder *pD3D12Enc, " for tile_obu_group() prefix syntax: tile_start_and_end_present_flag, tg_start, tg_end\n", tileGroup.tg_start, tileGroup.tg_end, - bitstream_tile_group_obu_bytes, + static_cast(bitstream_tile_group_obu_bytes), staging_bitstream_buffer.data(), - staging_bitstream_buffer_offset); + static_cast(staging_bitstream_buffer_offset)); // Save this to compare the final written destination byte size against the expected tile_group_obu_size @@ -2699,11 +2699,11 @@ upload_tile_group_obu(struct d3d12_video_encoder *pD3D12Enc, " to comp_bit_destination %p at offset %" PRIu64 "\n", tileGroup.tg_start, tileGroup.tg_end, - bitstream_tile_group_obu_bytes, + static_cast(bitstream_tile_group_obu_bytes), staging_bitstream_buffer.data(), - staging_bitstream_buffer_offset, + static_cast(staging_bitstream_buffer_offset), comp_bit_destination, - comp_bit_destination_offset); + static_cast(comp_bit_destination_offset)); comp_bit_destination_offset += bitstream_tile_group_obu_bytes; written_bytes_to_staging_bitstream_buffer += bitstream_tile_group_obu_bytes; @@ -2729,9 +2729,9 @@ upload_tile_group_obu(struct d3d12_video_encoder *pD3D12Enc, tileGroup.tg_start, tileGroup.tg_end, TileIdx, - TileSizeBytes, + static_cast(TileSizeBytes), staging_bitstream_buffer.data(), - (written_bytes_to_staging_bitstream_buffer + staging_bitstream_buffer_offset)); + static_cast(written_bytes_to_staging_bitstream_buffer + staging_bitstream_buffer_offset)); // Upload current tile_size_minus_1 // Note: The buffer_subdata is queued in pD3D12Enc->base.context but doesn't execute immediately @@ -2751,11 +2751,11 @@ upload_tile_group_obu(struct d3d12_video_encoder *pD3D12Enc, tileGroup.tg_start, tileGroup.tg_end, TileIdx, - TileSizeBytes, + static_cast(TileSizeBytes), staging_bitstream_buffer.data(), - (written_bytes_to_staging_bitstream_buffer + staging_bitstream_buffer_offset), + static_cast(written_bytes_to_staging_bitstream_buffer + staging_bitstream_buffer_offset), comp_bit_destination, - comp_bit_destination_offset); + static_cast(comp_bit_destination_offset)); comp_bit_destination_offset += TileSizeBytes; written_bytes_to_staging_bitstream_buffer += TileSizeBytes; @@ -2788,11 +2788,11 @@ upload_tile_group_obu(struct d3d12_video_encoder *pD3D12Enc, tileGroup.tg_start, tileGroup.tg_end, TileIdx, - tile_size, + static_cast(tile_size), src_driver_bitstream, - src_buf_tile_position, + static_cast(src_buf_tile_position), comp_bit_destination, - comp_bit_destination_offset); + static_cast(comp_bit_destination_offset)); comp_bit_destination_offset += tile_size; } diff --git a/src/gallium/drivers/d3d12/d3d12_video_encoder_bitstream_builder_av1.cpp b/src/gallium/drivers/d3d12/d3d12_video_encoder_bitstream_builder_av1.cpp index 25550a2b4fb..96b7e32eb8e 100644 --- a/src/gallium/drivers/d3d12/d3d12_video_encoder_bitstream_builder_av1.cpp +++ b/src/gallium/drivers/d3d12/d3d12_video_encoder_bitstream_builder_av1.cpp @@ -153,7 +153,7 @@ d3d12_video_bitstream_builder_av1::write_temporal_delimiter_obu(std::vector(bitstream_seq.get_byte_count()); + const uint64_t obu_size_in_bytes = bitstream_seq.get_byte_count(); debug_printf("obu_size: %" PRIu64 "\n", obu_size_in_bytes); pack_obu_header_size(&bitstream_full_obu, obu_size_in_bytes); @@ -802,7 +802,7 @@ d3d12_video_bitstream_builder_av1::write_frame_header(const av1_seq_header_t *pS debug_printf("frame_header_obu() bytes (without OBU_FRAME nor OBU_FRAME_HEADER alignment padding): %" PRId32 "\n", bitstream_pic.get_byte_count()); // May be bit unaligned at this point (see padding below) debug_printf("extra_obu_size_bytes (ie. tile_group_obu_size if writing OBU_FRAME ): %" PRIu64 "\n", - extra_obu_size_bytes); + static_cast(extra_obu_size_bytes)); // Write the obu_header constexpr uint32_t obu_extension_flag = 0; @@ -825,7 +825,7 @@ d3d12_video_bitstream_builder_av1::write_frame_header(const av1_seq_header_t *pS bitstream_pic.flush(); // Write the obu_size element - const size_t obu_size_in_bytes = bitstream_pic.get_byte_count() + extra_obu_size_bytes; + const uint64_t obu_size_in_bytes = bitstream_pic.get_byte_count() + extra_obu_size_bytes; debug_printf("obu_size: %" PRIu64 "\n", obu_size_in_bytes); pack_obu_header_size(&bitstream_full_obu, obu_size_in_bytes); @@ -913,7 +913,7 @@ d3d12_video_bitstream_builder_av1::write_obu_tile_group_header(size_t tile_group // Write the obu_size element pack_obu_header_size(&bitstream_full_obu, tile_group_obu_size); - debug_printf("obu_size: %" PRIu64 "\n", tile_group_obu_size); + debug_printf("obu_size: %" PRIu64 "\n", static_cast(tile_group_obu_size)); bitstream_full_obu.flush(); diff --git a/src/gallium/drivers/d3d12/d3d12_video_encoder_references_manager_av1.cpp b/src/gallium/drivers/d3d12/d3d12_video_encoder_references_manager_av1.cpp index 49892338984..2f4bcf0e1eb 100644 --- a/src/gallium/drivers/d3d12/d3d12_video_encoder_references_manager_av1.cpp +++ b/src/gallium/drivers/d3d12/d3d12_video_encoder_references_manager_av1.cpp @@ -213,7 +213,7 @@ d3d12_video_encoder_references_manager_av1::print_virtual_dpb_entries() "Number of DPB virtual entries is %" PRIu64 " entries for frame with OrderHint " "%d (PictureIndex %d) are: \n%s \n", m_PhysicalAllocationsStorage.get_number_of_pics_in_dpb(), - m_CurrentFrameReferencesData.pVirtualDPBEntries.size(), + static_cast(m_CurrentFrameReferencesData.pVirtualDPBEntries.size()), m_CurrentFramePicParams.OrderHint, m_CurrentFramePicParams.PictureIndex, dpbContents.c_str()); diff --git a/src/gallium/drivers/etnaviv/etnaviv_compiler.c b/src/gallium/drivers/etnaviv/etnaviv_compiler.c index f25250c12a8..afc70cfcb3c 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_compiler.c +++ b/src/gallium/drivers/etnaviv/etnaviv_compiler.c @@ -54,8 +54,6 @@ etna_compiler_create(const char *renderer, const struct etna_specs *specs) .lower_fmod = true, .lower_vector_cmp = true, .lower_fdph = true, - .lower_extract_byte = true, - .lower_extract_word = true, .lower_insert_byte = true, .lower_insert_word = true, .lower_fdiv = true, /* !specs->has_new_transcendentals */ diff --git a/src/gallium/drivers/etnaviv/etnaviv_shader.c b/src/gallium/drivers/etnaviv/etnaviv_shader.c index e0054f94332..d0567d717a3 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_shader.c +++ b/src/gallium/drivers/etnaviv/etnaviv_shader.c @@ -147,6 +147,7 @@ etna_link_shaders(struct etna_context *ctx, struct compiled_shader_state *cs, COND(last_varying_2x, VIVS_RA_CONTROL_LAST_VARYING_2X); cs->PA_ATTRIBUTE_ELEMENT_COUNT = VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT(link.num_varyings); + STATIC_ASSERT(VIVS_PA_SHADER_ATTRIBUTES__LEN >= ETNA_NUM_VARYINGS); for (int idx = 0; idx < link.num_varyings; ++idx) cs->PA_SHADER_ATTRIBUTES[idx] = link.varyings[idx].pa_attributes; diff --git a/src/gallium/drivers/etnaviv/hw/cmdstream.xml.h b/src/gallium/drivers/etnaviv/hw/cmdstream.xml.h index bfab938691b..cc8f351e0bd 100644 --- a/src/gallium/drivers/etnaviv/hw/cmdstream.xml.h +++ b/src/gallium/drivers/etnaviv/hw/cmdstream.xml.h @@ -10,7 +10,7 @@ git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: - cmdstream.xml ( 16930 bytes, from 2019-01-04 11:37:39) - copyright.xml ( 1597 bytes, from 2018-02-10 13:09:26) -- common.xml ( 35468 bytes, from 2020-01-04 20:02:31) +- common.xml ( 35465 bytes, from 2023-11-13 11:29:31) Copyright (C) 2012-2019 by the following authors: - Wladimir J. van der Laan diff --git a/src/gallium/drivers/etnaviv/hw/common.xml.h b/src/gallium/drivers/etnaviv/hw/common.xml.h index f3a2143ec26..0a01ac20d8c 100644 --- a/src/gallium/drivers/etnaviv/hw/common.xml.h +++ b/src/gallium/drivers/etnaviv/hw/common.xml.h @@ -10,10 +10,10 @@ git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: - texdesc_3d.xml ( 3183 bytes, from 2018-02-10 13:09:26) - copyright.xml ( 1597 bytes, from 2018-02-10 13:09:26) -- common.xml ( 35468 bytes, from 2020-01-04 20:02:31) -- common_3d.xml ( 15058 bytes, from 2022-10-07 06:11:53) +- common.xml ( 35465 bytes, from 2023-11-13 11:29:31) +- common_3d.xml ( 15069 bytes, from 2023-11-13 11:29:31) -Copyright (C) 2012-2020 by the following authors: +Copyright (C) 2012-2023 by the following authors: - Wladimir J. van der Laan - Christian Gmeiner - Lucas Stach diff --git a/src/gallium/drivers/etnaviv/hw/common_3d.xml.h b/src/gallium/drivers/etnaviv/hw/common_3d.xml.h index 39291967158..60474a22479 100644 --- a/src/gallium/drivers/etnaviv/hw/common_3d.xml.h +++ b/src/gallium/drivers/etnaviv/hw/common_3d.xml.h @@ -10,10 +10,10 @@ git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: - texdesc_3d.xml ( 3183 bytes, from 2018-02-10 13:09:26) - copyright.xml ( 1597 bytes, from 2018-02-10 13:09:26) -- common.xml ( 35468 bytes, from 2020-01-04 20:02:31) -- common_3d.xml ( 15058 bytes, from 2022-10-07 06:11:53) +- common.xml ( 35465 bytes, from 2023-11-13 11:29:31) +- common_3d.xml ( 15069 bytes, from 2023-11-13 11:29:31) -Copyright (C) 2012-2022 by the following authors: +Copyright (C) 2012-2023 by the following authors: - Wladimir J. van der Laan - Christian Gmeiner - Lucas Stach diff --git a/src/gallium/drivers/etnaviv/hw/isa.xml.h b/src/gallium/drivers/etnaviv/hw/isa.xml.h index c7134cf3028..5270cfca2a8 100644 --- a/src/gallium/drivers/etnaviv/hw/isa.xml.h +++ b/src/gallium/drivers/etnaviv/hw/isa.xml.h @@ -8,10 +8,10 @@ This file was generated by the rules-ng-ng headergen tool in this git repository git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: -- isa.xml ( 38205 bytes, from 2022-09-03 22:41:40) +- isa.xml ( 39261 bytes, from 2023-11-13 11:29:31) - copyright.xml ( 1597 bytes, from 2018-02-10 13:09:26) -Copyright (C) 2012-2022 by the following authors: +Copyright (C) 2012-2023 by the following authors: - Wladimir J. van der Laan - Christian Gmeiner - Lucas Stach @@ -90,8 +90,8 @@ DEALINGS IN THE SOFTWARE. #define INST_OPCODE_CMP 0x00000031 #define INST_OPCODE_LOAD 0x00000032 #define INST_OPCODE_STORE 0x00000033 -#define INST_OPCODE_COPYSIGN 0x00000034 -#define INST_OPCODE_GETEXP 0x00000035 +#define INST_OPCODE_IMG_LOAD_3D 0x00000034 +#define INST_OPCODE_IMG_STORE_3D 0x00000035 #define INST_OPCODE_GETMANT 0x00000036 #define INST_OPCODE_NAN 0x00000037 #define INST_OPCODE_NEXTAFTER 0x00000038 @@ -159,8 +159,8 @@ DEALINGS IN THE SOFTWARE. #define INST_OPCODE_NORM_DP4 0x00000076 #define INST_OPCODE_NORM_MUL 0x00000077 #define INST_OPCODE_STORE_ATTR 0x00000078 -#define INST_OPCODE_LOAD_ATTR 0x00000079 -#define INST_OPCODE_EMIT 0x0000007a +#define INST_OPCODE_IMG_LOAD 0x00000079 +#define INST_OPCODE_IMG_STORE 0x0000007a #define INST_OPCODE_RESTART 0x0000007b #define INST_OPCODE_NOP7C 0x0000007c #define INST_OPCODE_NOP7D 0x0000007d diff --git a/src/gallium/drivers/etnaviv/hw/state.xml.h b/src/gallium/drivers/etnaviv/hw/state.xml.h index 22dd83efc4d..c8f710e4196 100644 --- a/src/gallium/drivers/etnaviv/hw/state.xml.h +++ b/src/gallium/drivers/etnaviv/hw/state.xml.h @@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: -- state.xml ( 27198 bytes, from 2022-08-16 16:28:18) -- common.xml ( 35468 bytes, from 2020-01-04 20:02:31) -- common_3d.xml ( 15058 bytes, from 2022-10-07 06:11:53) -- state_hi.xml ( 34803 bytes, from 2022-08-16 16:28:18) +- state.xml ( 28218 bytes, from 2023-11-13 11:29:31) +- common.xml ( 35465 bytes, from 2023-11-13 11:29:31) +- common_3d.xml ( 15069 bytes, from 2023-11-13 11:29:31) +- state_hi.xml ( 34935 bytes, from 2023-11-13 11:29:31) - copyright.xml ( 1597 bytes, from 2018-02-10 13:09:26) -- state_2d.xml ( 51552 bytes, from 2018-02-10 13:09:26) -- state_3d.xml ( 84326 bytes, from 2022-10-07 06:11:53) -- state_blt.xml ( 14424 bytes, from 2022-10-07 06:11:53) +- state_2d.xml ( 52271 bytes, from 2023-09-13 13:37:23) +- state_3d.xml ( 86123 bytes, from 2023-11-13 12:42:26) +- state_blt.xml ( 14424 bytes, from 2023-09-13 13:37:23) - state_vg.xml ( 5975 bytes, from 2018-02-10 13:09:26) -Copyright (C) 2012-2022 by the following authors: +Copyright (C) 2012-2023 by the following authors: - Wladimir J. van der Laan - Christian Gmeiner - Lucas Stach @@ -400,7 +400,16 @@ DEALINGS IN THE SOFTWARE. #define VIVS_GL_FENCE_OUT_DATA_LOW 0x0000386c -#define VIVS_GL_HALTI5_UNK03884 0x00003884 +#define VIVS_GL_USC_CONTROL 0x00003884 +#define VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__MASK 0x00000007 +#define VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__SHIFT 0 +#define VIVS_GL_USC_CONTROL_L1_CACHE_RATIO(x) (((x) << VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__SHIFT) & VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__MASK) +#define VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__MASK 0x00000f00 +#define VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__SHIFT 8 +#define VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO(x) (((x) << VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__SHIFT) & VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__MASK) +#define VIVS_GL_USC_CONTROL_UNK16__MASK 0x001f0000 +#define VIVS_GL_USC_CONTROL_UNK16__SHIFT 16 +#define VIVS_GL_USC_CONTROL_UNK16(x) (((x) << VIVS_GL_USC_CONTROL_UNK16__SHIFT) & VIVS_GL_USC_CONTROL_UNK16__MASK) #define VIVS_GL_HALTI5_SH_SPECIALS 0x00003888 #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK 0x0000007f @@ -434,6 +443,30 @@ DEALINGS IN THE SOFTWARE. #define VIVS_GL_SECURITY_UNK3904 0x00003904 +#define VIVS_GL_NN_CONFIG 0x00003930 +#define VIVS_GL_NN_CONFIG_UNK0__MASK 0x00000003 +#define VIVS_GL_NN_CONFIG_UNK0__SHIFT 0 +#define VIVS_GL_NN_CONFIG_UNK0(x) (((x) << VIVS_GL_NN_CONFIG_UNK0__SHIFT) & VIVS_GL_NN_CONFIG_UNK0__MASK) +#define VIVS_GL_NN_CONFIG_DISABLE_ZDPN 0x00000004 +#define VIVS_GL_NN_CONFIG_DISABLE_SWTILING 0x00000008 +#define VIVS_GL_NN_CONFIG_SMALL_BATCH 0x00000010 +#define VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__MASK 0x00000060 +#define VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__SHIFT 5 +#define VIVS_GL_NN_CONFIG_DDR_BURST_SIZE(x) (((x) << VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__SHIFT) & VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__MASK) +#define VIVS_GL_NN_CONFIG_UNK7 0x00000080 +#define VIVS_GL_NN_CONFIG_NN_CORE_COUNT__MASK 0x00000f00 +#define VIVS_GL_NN_CONFIG_NN_CORE_COUNT__SHIFT 8 +#define VIVS_GL_NN_CONFIG_NN_CORE_COUNT(x) (((x) << VIVS_GL_NN_CONFIG_NN_CORE_COUNT__SHIFT) & VIVS_GL_NN_CONFIG_NN_CORE_COUNT__MASK) +#define VIVS_GL_NN_CONFIG_UNK12 0x00001000 + +#define VIVS_GL_SRAM_REMAP_ADDRESS 0x00003938 + +#define VIVS_GL_OCB_REMAP_START 0x0000393c + +#define VIVS_GL_OCB_REMAP_END 0x00003940 + +#define VIVS_GL_TP_CONFIG 0x0000394c + #define VIVS_GL_UNK03A00 0x00003a00 #define VIVS_GL_UNK03A04 0x00003a04 diff --git a/src/gallium/drivers/etnaviv/hw/state_3d.xml.h b/src/gallium/drivers/etnaviv/hw/state_3d.xml.h index da764bb8649..2409c8c12a5 100644 --- a/src/gallium/drivers/etnaviv/hw/state_3d.xml.h +++ b/src/gallium/drivers/etnaviv/hw/state_3d.xml.h @@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: -- state.xml ( 27198 bytes, from 2022-04-22 10:35:24) -- common.xml ( 35468 bytes, from 2020-10-28 12:56:03) -- common_3d.xml ( 15058 bytes, from 2020-10-28 12:56:03) -- state_hi.xml ( 34803 bytes, from 2020-10-28 12:56:03) -- copyright.xml ( 1597 bytes, from 2020-10-28 12:56:03) -- state_2d.xml ( 51552 bytes, from 2020-10-28 12:56:03) -- state_3d.xml ( 84445 bytes, from 2022-11-15 15:59:38) -- state_blt.xml ( 14424 bytes, from 2022-11-07 11:18:41) -- state_vg.xml ( 5975 bytes, from 2020-10-28 12:56:03) - -Copyright (C) 2012-2022 by the following authors: +- state.xml ( 28218 bytes, from 2023-11-13 11:29:31) +- common.xml ( 35465 bytes, from 2023-11-13 11:29:31) +- common_3d.xml ( 15069 bytes, from 2023-11-13 11:29:31) +- state_hi.xml ( 34935 bytes, from 2023-11-13 11:29:31) +- copyright.xml ( 1597 bytes, from 2018-02-10 13:09:26) +- state_2d.xml ( 52271 bytes, from 2023-09-13 13:37:23) +- state_3d.xml ( 86123 bytes, from 2023-11-13 12:42:26) +- state_blt.xml ( 14424 bytes, from 2023-09-13 13:37:23) +- state_vg.xml ( 5975 bytes, from 2018-02-10 13:09:26) + +Copyright (C) 2012-2023 by the following authors: - Wladimir J. van der Laan - Christian Gmeiner - Lucas Stach @@ -159,6 +159,15 @@ DEALINGS IN THE SOFTWARE. #define VIVS_VS_END_PC 0x00000800 #define VIVS_VS_OUTPUT_COUNT 0x00000804 +#define VIVS_VS_OUTPUT_COUNT_COUNT__MASK 0x000000ff +#define VIVS_VS_OUTPUT_COUNT_COUNT__SHIFT 0 +#define VIVS_VS_OUTPUT_COUNT_COUNT(x) (((x) << VIVS_VS_OUTPUT_COUNT_COUNT__SHIFT) & VIVS_VS_OUTPUT_COUNT_COUNT__MASK) +#define VIVS_VS_OUTPUT_COUNT_OUTPUT16_REG__MASK 0x0000ff00 +#define VIVS_VS_OUTPUT_COUNT_OUTPUT16_REG__SHIFT 8 +#define VIVS_VS_OUTPUT_COUNT_OUTPUT16_REG(x) (((x) << VIVS_VS_OUTPUT_COUNT_OUTPUT16_REG__SHIFT) & VIVS_VS_OUTPUT_COUNT_OUTPUT16_REG__MASK) +#define VIVS_VS_OUTPUT_COUNT_OUTPUT17_REG__MASK 0x00ff0000 +#define VIVS_VS_OUTPUT_COUNT_OUTPUT17_REG__SHIFT 16 +#define VIVS_VS_OUTPUT_COUNT_OUTPUT17_REG(x) (((x) << VIVS_VS_OUTPUT_COUNT_OUTPUT17_REG__SHIFT) & VIVS_VS_OUTPUT_COUNT_OUTPUT17_REG__MASK) #define VIVS_VS_INPUT_COUNT 0x00000808 #define VIVS_VS_INPUT_COUNT_COUNT__MASK 0x0000000f @@ -270,7 +279,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_VS_ICACHE_PREFETCH 0x0000088c -#define VIVS_VS_ICACHE_UNK00890 0x00000890 +#define VIVS_VS_ICACHE_PREFETCH_INSTRUCTIONS 0x00000890 #define VIVS_VS_HALTI5_UNK00898(i0) (0x00000898 + 0x4*(i0)) #define VIVS_VS_HALTI5_UNK00898__ESIZE 0x00000004 @@ -421,17 +430,23 @@ DEALINGS IN THE SOFTWARE. #define VIVS_CL_UNK00924 0x00000924 -#define VIVS_CL_UNK00940 0x00000940 +#define VIVS_CL_GLOBAL_WORK_OFFSET_X 0x0000092c -#define VIVS_CL_UNK00944 0x00000944 +#define VIVS_CL_GLOBAL_WORK_OFFSET_Y 0x00000934 -#define VIVS_CL_UNK00948 0x00000948 +#define VIVS_CL_GLOBAL_WORK_OFFSET_Z 0x0000093c -#define VIVS_CL_UNK0094C 0x0000094c +#define VIVS_CL_WORKGROUP_COUNT_X 0x00000940 -#define VIVS_CL_UNK00950 0x00000950 +#define VIVS_CL_WORKGROUP_COUNT_Y 0x00000944 -#define VIVS_CL_UNK00954 0x00000954 +#define VIVS_CL_WORKGROUP_COUNT_Z 0x00000948 + +#define VIVS_CL_WORKGROUP_SIZE_X 0x0000094c + +#define VIVS_CL_WORKGROUP_SIZE_Y 0x00000950 + +#define VIVS_CL_WORKGROUP_SIZE_Z 0x00000954 #define VIVS_CL_HALTI5_UNK00958 0x00000958 @@ -504,7 +519,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_PA_SHADER_ATTRIBUTES(i0) (0x00000a40 + 0x4*(i0)) #define VIVS_PA_SHADER_ATTRIBUTES__ESIZE 0x00000004 -#define VIVS_PA_SHADER_ATTRIBUTES__LEN 0x0000000a +#define VIVS_PA_SHADER_ATTRIBUTES__LEN 0x00000010 #define VIVS_PA_SHADER_ATTRIBUTES_BYPASS_FLAT 0x00000001 #define VIVS_PA_SHADER_ATTRIBUTES_UNK4__MASK 0x000000f0 #define VIVS_PA_SHADER_ATTRIBUTES_UNK4__SHIFT 4 @@ -593,7 +608,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_PS_OUTPUT_REG 0x00001004 #define VIVS_PS_INPUT_COUNT 0x00001008 -#define VIVS_PS_INPUT_COUNT_COUNT__MASK 0x0000000f +#define VIVS_PS_INPUT_COUNT_COUNT__MASK 0x0000001f #define VIVS_PS_INPUT_COUNT_COUNT__SHIFT 0 #define VIVS_PS_INPUT_COUNT_COUNT(x) (((x) << VIVS_PS_INPUT_COUNT_COUNT__SHIFT) & VIVS_PS_INPUT_COUNT_COUNT__MASK) #define VIVS_PS_INPUT_COUNT_UNK8__MASK 0x00001f00 @@ -628,6 +643,8 @@ DEALINGS IN THE SOFTWARE. #define VIVS_PS_RANGE_HIGH__SHIFT 16 #define VIVS_PS_RANGE_HIGH(x) (((x) << VIVS_PS_RANGE_HIGH__SHIFT) & VIVS_PS_RANGE_HIGH__MASK) +#define VIVS_PS_REG_COUNT 0x0000101e + #define VIVS_PS_UNIFORM_BASE 0x00001024 #define VIVS_PS_INST_ADDR 0x00001028 @@ -676,7 +693,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_PS_ICACHE_PREFETCH 0x00001048 -#define VIVS_PS_ICACHE_UNK0104C 0x0000104c +#define VIVS_PS_ICACHE_PREFETCH_INSTRUCTIONS 0x0000104c #define VIVS_PS_MSAA_CONFIG 0x00001054 @@ -694,6 +711,12 @@ DEALINGS IN THE SOFTWARE. #define VIVS_PS_HALTI5_UNK01098 0x00001098 +#define VIVS_PS_PSCS_THROTTLE 0x0000109c + +#define VIVS_PS_NN_INST_ADDR 0x000010a0 + +#define VIVS_PS_TP_INST_ADDR 0x000010b8 + #define VIVS_PS_INST_MEM(i0) (0x00006000 + 0x4*(i0)) #define VIVS_PS_INST_MEM__ESIZE 0x00000004 #define VIVS_PS_INST_MEM__LEN 0x00000400 diff --git a/src/gallium/drivers/etnaviv/hw/state_blt.xml.h b/src/gallium/drivers/etnaviv/hw/state_blt.xml.h index 1c7f78d95dc..06c2ae3a332 100644 --- a/src/gallium/drivers/etnaviv/hw/state_blt.xml.h +++ b/src/gallium/drivers/etnaviv/hw/state_blt.xml.h @@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: -- state.xml ( 27198 bytes, from 2022-08-16 16:28:18) -- common.xml ( 35468 bytes, from 2020-01-04 20:02:31) -- common_3d.xml ( 15058 bytes, from 2022-10-07 06:11:53) -- state_hi.xml ( 34803 bytes, from 2022-08-16 16:28:18) +- state.xml ( 28218 bytes, from 2023-11-13 11:29:31) +- common.xml ( 35465 bytes, from 2023-11-13 11:29:31) +- common_3d.xml ( 15069 bytes, from 2023-11-13 11:29:31) +- state_hi.xml ( 34935 bytes, from 2023-11-13 11:29:31) - copyright.xml ( 1597 bytes, from 2018-02-10 13:09:26) -- state_2d.xml ( 51552 bytes, from 2018-02-10 13:09:26) -- state_3d.xml ( 84326 bytes, from 2022-10-07 06:11:53) -- state_blt.xml ( 14424 bytes, from 2022-10-07 06:11:53) +- state_2d.xml ( 52271 bytes, from 2023-09-13 13:37:23) +- state_3d.xml ( 86123 bytes, from 2023-11-13 12:42:26) +- state_blt.xml ( 14424 bytes, from 2023-09-13 13:37:23) - state_vg.xml ( 5975 bytes, from 2018-02-10 13:09:26) -Copyright (C) 2012-2022 by the following authors: +Copyright (C) 2012-2023 by the following authors: - Wladimir J. van der Laan - Christian Gmeiner - Lucas Stach diff --git a/src/gallium/drivers/etnaviv/hw/texdesc_3d.xml.h b/src/gallium/drivers/etnaviv/hw/texdesc_3d.xml.h index 8a0e7df3367..15af0af1540 100644 --- a/src/gallium/drivers/etnaviv/hw/texdesc_3d.xml.h +++ b/src/gallium/drivers/etnaviv/hw/texdesc_3d.xml.h @@ -10,8 +10,8 @@ git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: - texdesc_3d.xml ( 3183 bytes, from 2018-02-10 13:09:26) - copyright.xml ( 1597 bytes, from 2018-02-10 13:09:26) -- common.xml ( 35468 bytes, from 2020-01-04 20:02:31) -- common_3d.xml ( 15058 bytes, from 2022-10-07 06:11:53) +- common.xml ( 35465 bytes, from 2023-11-13 11:29:31) +- common_3d.xml ( 15069 bytes, from 2023-11-13 11:29:31) Copyright (C) 2012-2018 by the following authors: - Wladimir J. van der Laan diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_resource.cc b/src/gallium/drivers/freedreno/a6xx/fd6_resource.cc index b8f96bee616..0ed5a191e26 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_resource.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_resource.cc @@ -55,6 +55,13 @@ ok_ubwc_format(struct pipe_screen *pscreen, enum pipe_format pfmt) return info->a6xx.has_z24uint_s8uint; case PIPE_FORMAT_R8_G8B8_420_UNORM: + /* The difference between NV12 and R8_G8B8_420_UNORM is only where the + * conversion to RGB happens, with the latter it happens _after_ the + * texture samp instruction. But dri2_get_mapping_by_fourcc() doesn't + * know this, so it asks for NV12 when it really meant to ask for + * R8_G8B8_420_UNORM. Just treat them the same here to work around it: + */ + case PIPE_FORMAT_NV12: return true; default: diff --git a/src/gallium/drivers/freedreno/freedreno_batch.c b/src/gallium/drivers/freedreno/freedreno_batch.c index 6af2c7af5b0..9c458e33e7d 100644 --- a/src/gallium/drivers/freedreno/freedreno_batch.c +++ b/src/gallium/drivers/freedreno/freedreno_batch.c @@ -549,8 +549,10 @@ fd_batch_resource_write(struct fd_batch *batch, struct fd_resource *rsc) * ctx dependencies and let the app have the undefined behavior * it asked for: */ - if (track->write_batch->ctx != batch->ctx) + if (track->write_batch->ctx != batch->ctx) { + fd_ringbuffer_attach_bo(batch->draw, rsc->bo); return; + } flush_write_batch(rsc); } @@ -599,6 +601,7 @@ fd_batch_resource_read_slowpath(struct fd_batch *batch, struct fd_resource *rsc) * by avoiding cross-ctx dependencies and let the app have the * undefined behavior it asked for: */ + fd_ringbuffer_attach_bo(batch->draw, rsc->bo); return; } diff --git a/src/gallium/drivers/iris/iris_batch.c b/src/gallium/drivers/iris/iris_batch.c index d1f75a5981d..293a3b8951d 100644 --- a/src/gallium/drivers/iris/iris_batch.c +++ b/src/gallium/drivers/iris/iris_batch.c @@ -278,6 +278,9 @@ find_exec_index(struct iris_batch *batch, struct iris_bo *bo) { unsigned index = READ_ONCE(bo->index); + if (index == -1) + return -1; + if (index < batch->exec_count && batch->exec_bos[index] == bo) return index; diff --git a/src/gallium/drivers/iris/iris_bufmgr.c b/src/gallium/drivers/iris/iris_bufmgr.c index e7e55049f36..f76ef870e1e 100644 --- a/src/gallium/drivers/iris/iris_bufmgr.c +++ b/src/gallium/drivers/iris/iris_bufmgr.c @@ -1413,6 +1413,7 @@ iris_bo_gem_create_from_name(struct iris_bufmgr *bufmgr, bo->bufmgr = bufmgr; bo->gem_handle = open_arg.handle; bo->name = name; + bo->index = -1; bo->real.global_name = handle; bo->real.prime_fd = -1; bo->real.reusable = false; @@ -1974,6 +1975,7 @@ iris_bo_import_dmabuf(struct iris_bufmgr *bufmgr, int prime_fd, bo->bufmgr = bufmgr; bo->name = "prime"; + bo->index = -1; bo->real.reusable = false; bo->real.imported = true; bo->real.mmap_mode = IRIS_MMAP_NONE; diff --git a/src/gallium/drivers/iris/iris_resolve.c b/src/gallium/drivers/iris/iris_resolve.c index 14a6d95d583..525953b2544 100644 --- a/src/gallium/drivers/iris/iris_resolve.c +++ b/src/gallium/drivers/iris/iris_resolve.c @@ -679,6 +679,13 @@ iris_hiz_exec(struct iris_context *ice, //DBG("%s %s to mt %p level %d layers %d-%d\n", //__func__, name, mt, level, start_layer, start_layer + num_layers - 1); + /* A data cache flush is not suggested by HW docs, but we found it to fix + * a number of failures. + */ + unsigned wa_flush = intel_device_info_is_dg2(batch->screen->devinfo) && + res->aux.usage == ISL_AUX_USAGE_HIZ_CCS ? + PIPE_CONTROL_DATA_CACHE_FLUSH : 0; + /* The following stalls and flushes are only documented to be required * for HiZ clear operations. However, they also seem to be required for * resolve operations. @@ -695,6 +702,7 @@ iris_hiz_exec(struct iris_context *ice, iris_emit_pipe_control_flush(batch, "hiz op: pre-flush", PIPE_CONTROL_DEPTH_CACHE_FLUSH | + wa_flush | PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_CS_STALL); diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index b7c194ab96e..7f7d387db16 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -6806,13 +6806,16 @@ iris_upload_dirty_render_state(struct iris_context *ice, bool program_needs_wa_14015055625 = false; +#if INTEL_WA_14015055625_GFX_VER /* Check if FS stage will use primitive ID overrides for Wa_14015055625. */ const struct brw_vue_map *last_vue_map = &brw_vue_prog_data(ice->shaders.last_vue_shader->prog_data)->vue_map; if ((wm_prog_data->inputs & VARYING_BIT_PRIMITIVE_ID) && - last_vue_map->varying_to_slot[VARYING_SLOT_PRIMITIVE_ID] == -1) { + last_vue_map->varying_to_slot[VARYING_SLOT_PRIMITIVE_ID] == -1 && + intel_needs_workaround(batch->screen->devinfo, 14015055625)) { program_needs_wa_14015055625 = true; } +#endif for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) { if (!(stage_dirty & (IRIS_STAGE_DIRTY_VS << stage))) @@ -6828,8 +6831,10 @@ iris_upload_dirty_render_state(struct iris_context *ice, uint32_t scratch_addr = pin_scratch_space(ice, batch, prog_data, stage); +#if INTEL_WA_14015055625_GFX_VER shader_program_needs_wa_14015055625(ice, batch, prog_data, stage, &program_needs_wa_14015055625); +#endif if (stage == MESA_SHADER_FRAGMENT) { UNUSED struct iris_rasterizer_state *cso = ice->state.cso_rast; @@ -7864,6 +7869,11 @@ iris_upload_render_state(struct iris_context *ice, #endif } + if (indirect) { + struct mi_builder b; + uint32_t mocs; + mi_builder_init(&b, batch->screen->devinfo, batch); + #define _3DPRIM_END_OFFSET 0x2420 #define _3DPRIM_START_VERTEX 0x2430 #define _3DPRIM_VERTEX_COUNT 0x2434 @@ -7871,103 +7881,100 @@ iris_upload_render_state(struct iris_context *ice, #define _3DPRIM_START_INSTANCE 0x243C #define _3DPRIM_BASE_VERTEX 0x2440 - struct mi_builder b; - uint32_t mocs; - mi_builder_init(&b, batch->screen->devinfo, batch); + if (!indirect->count_from_stream_output) { + if (indirect->indirect_draw_count) { + use_predicate = true; + + struct iris_bo *draw_count_bo = + iris_resource_bo(indirect->indirect_draw_count); + unsigned draw_count_offset = + indirect->indirect_draw_count_offset; + mocs = iris_mocs(draw_count_bo, &batch->screen->isl_dev, 0); + mi_builder_set_mocs(&b, mocs); + + if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT) { + /* comparison = draw id < draw count */ + struct mi_value comparison = + mi_ult(&b, mi_imm(drawid_offset), + mi_mem32(ro_bo(draw_count_bo, draw_count_offset))); + + /* predicate = comparison & conditional rendering predicate */ + mi_store(&b, mi_reg32(MI_PREDICATE_RESULT), + mi_iand(&b, comparison, mi_reg32(CS_GPR(15)))); + } else { + uint32_t mi_predicate; - if (indirect && !indirect->count_from_stream_output) { - if (indirect->indirect_draw_count) { - use_predicate = true; + /* Upload the id of the current primitive to MI_PREDICATE_SRC1. */ + mi_store(&b, mi_reg64(MI_PREDICATE_SRC1), mi_imm(drawid_offset)); + /* Upload the current draw count from the draw parameters buffer + * to MI_PREDICATE_SRC0. Zero the top 32-bits of + * MI_PREDICATE_SRC0. + */ + mi_store(&b, mi_reg64(MI_PREDICATE_SRC0), + mi_mem32(ro_bo(draw_count_bo, draw_count_offset))); + + if (drawid_offset == 0) { + mi_predicate = MI_PREDICATE | MI_PREDICATE_LOADOP_LOADINV | + MI_PREDICATE_COMBINEOP_SET | + MI_PREDICATE_COMPAREOP_SRCS_EQUAL; + } else { + /* While draw_index < draw_count the predicate's result will be + * (draw_index == draw_count) ^ TRUE = TRUE + * When draw_index == draw_count the result is + * (TRUE) ^ TRUE = FALSE + * After this all results will be: + * (FALSE) ^ FALSE = FALSE + */ + mi_predicate = MI_PREDICATE | MI_PREDICATE_LOADOP_LOAD | + MI_PREDICATE_COMBINEOP_XOR | + MI_PREDICATE_COMPAREOP_SRCS_EQUAL; + } + iris_batch_emit(batch, &mi_predicate, sizeof(uint32_t)); + } + } + struct iris_bo *bo = iris_resource_bo(indirect->buffer); + assert(bo); - struct iris_bo *draw_count_bo = - iris_resource_bo(indirect->indirect_draw_count); - unsigned draw_count_offset = - indirect->indirect_draw_count_offset; - mocs = iris_mocs(draw_count_bo, &batch->screen->isl_dev, 0); + mocs = iris_mocs(bo, &batch->screen->isl_dev, 0); mi_builder_set_mocs(&b, mocs); - if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT) { - /* comparison = draw id < draw count */ - struct mi_value comparison = - mi_ult(&b, mi_imm(drawid_offset), - mi_mem32(ro_bo(draw_count_bo, draw_count_offset))); - - /* predicate = comparison & conditional rendering predicate */ - mi_store(&b, mi_reg32(MI_PREDICATE_RESULT), - mi_iand(&b, comparison, mi_reg32(CS_GPR(15)))); + mi_store(&b, mi_reg32(_3DPRIM_VERTEX_COUNT), + mi_mem32(ro_bo(bo, indirect->offset + 0))); + mi_store(&b, mi_reg32(_3DPRIM_INSTANCE_COUNT), + mi_mem32(ro_bo(bo, indirect->offset + 4))); + mi_store(&b, mi_reg32(_3DPRIM_START_VERTEX), + mi_mem32(ro_bo(bo, indirect->offset + 8))); + if (draw->index_size) { + mi_store(&b, mi_reg32(_3DPRIM_BASE_VERTEX), + mi_mem32(ro_bo(bo, indirect->offset + 12))); + mi_store(&b, mi_reg32(_3DPRIM_START_INSTANCE), + mi_mem32(ro_bo(bo, indirect->offset + 16))); } else { - uint32_t mi_predicate; + mi_store(&b, mi_reg32(_3DPRIM_START_INSTANCE), + mi_mem32(ro_bo(bo, indirect->offset + 12))); + mi_store(&b, mi_reg32(_3DPRIM_BASE_VERTEX), mi_imm(0)); + } + } else if (indirect->count_from_stream_output) { + struct iris_stream_output_target *so = + (void *) indirect->count_from_stream_output; + struct iris_bo *so_bo = iris_resource_bo(so->offset.res); - /* Upload the id of the current primitive to MI_PREDICATE_SRC1. */ - mi_store(&b, mi_reg64(MI_PREDICATE_SRC1), mi_imm(drawid_offset)); - /* Upload the current draw count from the draw parameters buffer - * to MI_PREDICATE_SRC0. Zero the top 32-bits of - * MI_PREDICATE_SRC0. - */ - mi_store(&b, mi_reg64(MI_PREDICATE_SRC0), - mi_mem32(ro_bo(draw_count_bo, draw_count_offset))); + mocs = iris_mocs(so_bo, &batch->screen->isl_dev, 0); + mi_builder_set_mocs(&b, mocs); - if (drawid_offset == 0) { - mi_predicate = MI_PREDICATE | MI_PREDICATE_LOADOP_LOADINV | - MI_PREDICATE_COMBINEOP_SET | - MI_PREDICATE_COMPAREOP_SRCS_EQUAL; - } else { - /* While draw_index < draw_count the predicate's result will be - * (draw_index == draw_count) ^ TRUE = TRUE - * When draw_index == draw_count the result is - * (TRUE) ^ TRUE = FALSE - * After this all results will be: - * (FALSE) ^ FALSE = FALSE - */ - mi_predicate = MI_PREDICATE | MI_PREDICATE_LOADOP_LOAD | - MI_PREDICATE_COMBINEOP_XOR | - MI_PREDICATE_COMPAREOP_SRCS_EQUAL; - } - iris_batch_emit(batch, &mi_predicate, sizeof(uint32_t)); - } - } - struct iris_bo *bo = iris_resource_bo(indirect->buffer); - assert(bo); - - mocs = iris_mocs(bo, &batch->screen->isl_dev, 0); - mi_builder_set_mocs(&b, mocs); - - mi_store(&b, mi_reg32(_3DPRIM_VERTEX_COUNT), - mi_mem32(ro_bo(bo, indirect->offset + 0))); - mi_store(&b, mi_reg32(_3DPRIM_INSTANCE_COUNT), - mi_mem32(ro_bo(bo, indirect->offset + 4))); - mi_store(&b, mi_reg32(_3DPRIM_START_VERTEX), - mi_mem32(ro_bo(bo, indirect->offset + 8))); - if (draw->index_size) { - mi_store(&b, mi_reg32(_3DPRIM_BASE_VERTEX), - mi_mem32(ro_bo(bo, indirect->offset + 12))); - mi_store(&b, mi_reg32(_3DPRIM_START_INSTANCE), - mi_mem32(ro_bo(bo, indirect->offset + 16))); - } else { - mi_store(&b, mi_reg32(_3DPRIM_START_INSTANCE), - mi_mem32(ro_bo(bo, indirect->offset + 12))); + iris_emit_buffer_barrier_for(batch, so_bo, IRIS_DOMAIN_OTHER_READ); + + struct iris_address addr = ro_bo(so_bo, so->offset.offset); + struct mi_value offset = + mi_iadd_imm(&b, mi_mem32(addr), -so->base.buffer_offset); + mi_store(&b, mi_reg32(_3DPRIM_VERTEX_COUNT), + mi_udiv32_imm(&b, offset, so->stride)); + mi_store(&b, mi_reg32(_3DPRIM_START_VERTEX), mi_imm(0)); mi_store(&b, mi_reg32(_3DPRIM_BASE_VERTEX), mi_imm(0)); + mi_store(&b, mi_reg32(_3DPRIM_START_INSTANCE), mi_imm(0)); + mi_store(&b, mi_reg32(_3DPRIM_INSTANCE_COUNT), + mi_imm(draw->instance_count)); } - } else if (indirect && indirect->count_from_stream_output) { - struct iris_stream_output_target *so = - (void *) indirect->count_from_stream_output; - struct iris_bo *so_bo = iris_resource_bo(so->offset.res); - - mocs = iris_mocs(so_bo, &batch->screen->isl_dev, 0); - mi_builder_set_mocs(&b, mocs); - - iris_emit_buffer_barrier_for(batch, so_bo, IRIS_DOMAIN_OTHER_READ); - - struct iris_address addr = ro_bo(so_bo, so->offset.offset); - struct mi_value offset = - mi_iadd_imm(&b, mi_mem32(addr), -so->base.buffer_offset); - mi_store(&b, mi_reg32(_3DPRIM_VERTEX_COUNT), - mi_udiv32_imm(&b, offset, so->stride)); - mi_store(&b, mi_reg32(_3DPRIM_START_VERTEX), mi_imm(0)); - mi_store(&b, mi_reg32(_3DPRIM_BASE_VERTEX), mi_imm(0)); - mi_store(&b, mi_reg32(_3DPRIM_START_INSTANCE), mi_imm(0)); - mi_store(&b, mi_reg32(_3DPRIM_INSTANCE_COUNT), - mi_imm(draw->instance_count)); } iris_measure_snapshot(ice, batch, INTEL_SNAPSHOT_DRAW, draw, indirect, sc); diff --git a/src/gallium/drivers/lima/ci/lima-fails.txt b/src/gallium/drivers/lima/ci/lima-fails.txt index 50f91c11400..e9039e214b7 100644 --- a/src/gallium/drivers/lima/ci/lima-fails.txt +++ b/src/gallium/drivers/lima/ci/lima-fails.txt @@ -207,6 +207,7 @@ spec@ext_framebuffer_object@fbo-maxsize,Fail spec@ext_framebuffer_object@fbo-readpixels-depth-formats,Fail spec@ext_framebuffer_object@fbo-readpixels-depth-formats@GL_DEPTH_COMPONENT/GL_FLOAT,Fail spec@ext_framebuffer_object@fbo-readpixels-depth-formats@GL_DEPTH_COMPONENT/GL_UNSIGNED_INT,Fail +spec@ext_framebuffer_object@fbo-scissor-bitmap,Fail spec@ext_framebuffer_object@fbo-stencil-gl_stencil_index16-blit,Fail spec@ext_framebuffer_object@fbo-stencil-gl_stencil_index16-copypixels,Fail spec@ext_framebuffer_object@fbo-stencil-gl_stencil_index16-drawpixels,Fail @@ -546,6 +547,7 @@ spec@khr_texture_compression_astc@basic-gles,Fail spec@khr_texture_compression_astc@miptree-gles srgb,Fail spec@khr_texture_compression_astc@miptree-gles srgb-fp,Fail spec@oes_point_sprite@arb_point_sprite-checkerboard_gles1,Fail +spec@!opengl 1.0@gl-1.0-dlist-bitmap,Fail spec@!opengl 1.0@gl-1.0-dlist-materials,Fail spec@!opengl 1.0@gl-1.0-dlist-shademodel,Fail spec@!opengl 1.0@gl-1.0-drawbuffer-modes,Fail @@ -570,6 +572,7 @@ spec@!opengl 1.0@gl-1.0-logicop@GL_XOR,Fail spec@!opengl 1.0@gl-1.0-no-op-paths,Fail spec@!opengl 1.0@gl-1.0-ortho-pos,Fail spec@!opengl 1.0@gl-1.0-rastercolor,Fail +spec@!opengl 1.0@gl-1.0-scissor-bitmap,Fail spec@!opengl 1.0@gl-1.0-swapbuffers-behavior,Fail spec@!opengl 1.0@gl-1.0-user-clip-all-planes,Fail spec@!opengl 1.1@gl-1.1-xor-copypixels,Fail @@ -640,6 +643,7 @@ spec@!opengl 2.0@vertex-program-two-side enabled front back back2@vs and fs,Fail spec@!opengl 2.0@vertex-program-two-side enabled front front2 back2,Fail spec@!opengl 2.0@vertex-program-two-side enabled front front2 back2@vs and fs,Fail spec@!opengl 2.1@pbo,Fail +spec@!opengl 2.1@pbo@test_bitmap,Fail spec@!opengl 2.1@pbo@test_polygon_stip,Fail spec@!opengl 2.1@polygon-stipple-fs,Fail spec@!opengl es 2.0@glsl-fs-pointcoord,Fail diff --git a/src/gallium/drivers/llvmpipe/ci/traces-llvmpipe.yml b/src/gallium/drivers/llvmpipe/ci/traces-llvmpipe.yml index 0d4277a7c4a..fd85705189a 100644 --- a/src/gallium/drivers/llvmpipe/ci/traces-llvmpipe.yml +++ b/src/gallium/drivers/llvmpipe/ci/traces-llvmpipe.yml @@ -153,9 +153,6 @@ traces: gl-vmware-llvmpipe: label: [skip, broken] text: missing background, error Too many compute shader storage blocks (9/8) - freedoom/freedoom-phase2-gl-high.trace: - gl-vmware-llvmpipe: - label: [unsupported] unvanquished/unvanquished-lowest.trace: gl-vmware-llvmpipe: label: [unsupported] diff --git a/src/gallium/drivers/llvmpipe/lp_texture_handle.c b/src/gallium/drivers/llvmpipe/lp_texture_handle.c index ff69fa024a5..179b429b12d 100644 --- a/src/gallium/drivers/llvmpipe/lp_texture_handle.c +++ b/src/gallium/drivers/llvmpipe/lp_texture_handle.c @@ -202,6 +202,7 @@ llvmpipe_sampler_matrix_destroy(struct llvmpipe_context *ctx) static void * compile_function(struct llvmpipe_context *ctx, struct gallivm_state *gallivm, LLVMValueRef function, + bool needs_caching, uint8_t cache_key[SHA1_DIGEST_LENGTH]) { gallivm_verify_function(gallivm, function); @@ -209,7 +210,7 @@ compile_function(struct llvmpipe_context *ctx, struct gallivm_state *gallivm, LL void *function_ptr = func_to_pointer(gallivm_jit_function(gallivm, function)); - if (!gallivm->cache->data_size) + if (needs_caching) lp_disk_cache_insert_shader(llvmpipe_screen(ctx->pipe.screen), gallivm->cache, cache_key); gallivm_free_ir(gallivm); @@ -251,10 +252,12 @@ compile_image_function(struct llvmpipe_context *ctx, struct lp_static_texture_st _mesa_sha1_update(&hash_ctx, image_function_base_hash, strlen(image_function_base_hash)); _mesa_sha1_update(&hash_ctx, texture, sizeof(*texture)); _mesa_sha1_update(&hash_ctx, &op, sizeof(op)); + _mesa_sha1_update(&hash_ctx, &ms, sizeof(ms)); _mesa_sha1_final(&hash_ctx, cache_key); struct lp_cached_code cached = { 0 }; lp_disk_cache_find_shader(llvmpipe_screen(ctx->pipe.screen), &cached, cache_key); + bool needs_caching = !cached.data_size; struct gallivm_state *gallivm = gallivm_create("sample_function", ctx->context, &cached); @@ -333,7 +336,7 @@ compile_image_function(struct llvmpipe_context *ctx, struct lp_static_texture_st free(image_soa); - return compile_function(ctx, gallivm, function, cache_key); + return compile_function(ctx, gallivm, function, needs_caching, cache_key); } static void * @@ -407,6 +410,7 @@ compile_sample_function(struct llvmpipe_context *ctx, struct lp_static_texture_s struct lp_cached_code cached = { 0 }; lp_disk_cache_find_shader(llvmpipe_screen(ctx->pipe.screen), &cached, cache_key); + bool needs_caching = !cached.data_size; struct gallivm_state *gallivm = gallivm_create("sample_function", ctx->context, &cached); @@ -480,7 +484,7 @@ compile_sample_function(struct llvmpipe_context *ctx, struct lp_static_texture_s free(sampler_soa); - return compile_function(ctx, gallivm, function, cache_key); + return compile_function(ctx, gallivm, function, needs_caching, cache_key); } static void * @@ -496,6 +500,7 @@ compile_size_function(struct llvmpipe_context *ctx, struct lp_static_texture_sta struct lp_cached_code cached = { 0 }; lp_disk_cache_find_shader(llvmpipe_screen(ctx->pipe.screen), &cached, cache_key); + bool needs_caching = !cached.data_size; struct gallivm_state *gallivm = gallivm_create("sample_function", ctx->context, &cached); @@ -560,7 +565,7 @@ compile_size_function(struct llvmpipe_context *ctx, struct lp_static_texture_sta free(sampler_soa); - return compile_function(ctx, gallivm, function, cache_key); + return compile_function(ctx, gallivm, function, needs_caching, cache_key); } static void diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index eb21b09558e..28a616a621f 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c @@ -207,6 +207,9 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_MAX_TEXTURE_MB: return 0; /* TODO: use 1/2 of VRAM for this? */ + case PIPE_CAP_TIMER_RESOLUTION: + return 1000; + case PIPE_CAP_SUPPORTED_PRIM_MODES_WITH_RESTART: case PIPE_CAP_SUPPORTED_PRIM_MODES: return BITFIELD_MASK(MESA_PRIM_COUNT); diff --git a/src/gallium/drivers/panfrost/pan_context.c b/src/gallium/drivers/panfrost/pan_context.c index ae5e2608909..65e06187e25 100644 --- a/src/gallium/drivers/panfrost/pan_context.c +++ b/src/gallium/drivers/panfrost/pan_context.c @@ -254,7 +254,7 @@ panfrost_set_shader_images(struct pipe_context *pctx, const struct pipe_image_view *iviews) { struct panfrost_context *ctx = pan_context(pctx); - ctx->dirty_shader[PIPE_SHADER_FRAGMENT] |= PAN_DIRTY_STAGE_IMAGE; + ctx->dirty_shader[shader] |= PAN_DIRTY_STAGE_IMAGE; /* Unbind start_slot...start_slot+count */ if (!iviews) { diff --git a/src/gallium/drivers/panfrost/pan_resource.c b/src/gallium/drivers/panfrost/pan_resource.c index ad19ad767b7..9abebde2266 100644 --- a/src/gallium/drivers/panfrost/pan_resource.c +++ b/src/gallium/drivers/panfrost/pan_resource.c @@ -41,6 +41,7 @@ #include "util/u_drm.h" #include "util/u_gen_mipmap.h" #include "util/u_memory.h" +#include "util/u_resource.h" #include "util/u_surface.h" #include "util/u_transfer.h" #include "util/u_transfer_helper.h" @@ -219,9 +220,8 @@ panfrost_resource_get_param(struct pipe_screen *pscreen, enum pipe_resource_param param, unsigned usage, uint64_t *value) { - struct panfrost_resource *rsrc = (struct panfrost_resource *)prsc; - struct pipe_resource *cur; - unsigned count; + struct panfrost_resource *rsrc = + (struct panfrost_resource *)util_resource_at_index(prsc, plane); switch (param) { case PIPE_RESOURCE_PARAM_STRIDE: @@ -234,14 +234,7 @@ panfrost_resource_get_param(struct pipe_screen *pscreen, *value = rsrc->image.layout.modifier; return true; case PIPE_RESOURCE_PARAM_NPLANES: - /* Panfrost doesn't directly support multi-planar formats, - * but we should still handle this case for gbm users - * that might want to use resources shared with panfrost - * on video processing hardware that does. - */ - for (count = 0, cur = prsc; cur; cur = cur->next) - count++; - *value = count; + *value = util_resource_num(prsc); return true; default: return false; @@ -1532,9 +1525,8 @@ panfrost_pack_afbc(struct panfrost_context *ctx, if (ratio > screen->max_afbc_packing_ratio) return; - if (dev->debug & PAN_DBG_PERF) { - printf("%i%%: %i KB -> %i KB\n", ratio, old_size / 1024, new_size / 1024); - } + perf_debug(dev, "%i%%: %i KB -> %i KB\n", ratio, old_size / 1024, + new_size / 1024); struct panfrost_bo *dst = panfrost_bo_create(dev, new_size, 0, "AFBC compact texture"); diff --git a/src/gallium/drivers/panfrost/pan_shader.c b/src/gallium/drivers/panfrost/pan_shader.c index 42bb2f72768..546910f8e66 100644 --- a/src/gallium/drivers/panfrost/pan_shader.c +++ b/src/gallium/drivers/panfrost/pan_shader.c @@ -470,6 +470,7 @@ panfrost_create_compute_state(struct pipe_context *pctx, /* The NIR becomes invalid after this. For compute kernels, we never * need to access it again. Don't keep a dangling pointer around. */ + ralloc_free((void *)so->nir); so->nir = NULL; return so; diff --git a/src/gallium/drivers/r600/meson.build b/src/gallium/drivers/r600/meson.build index 6167aaa8346..3555ea2edb0 100644 --- a/src/gallium/drivers/r600/meson.build +++ b/src/gallium/drivers/r600/meson.build @@ -174,7 +174,7 @@ endif libr600 = static_library( 'r600', - [files_r600, egd_tables_h], + [files_r600, egd_tables_h, sha1_h], c_args : [r600_c_args, '-Wstrict-overflow=0'], cpp_args: r600_cpp_args, gnu_symbol_visibility : 'hidden', @@ -182,7 +182,7 @@ libr600 = static_library( inc_src, inc_mapi, inc_mesa, inc_include, inc_gallium, inc_gallium_aux, inc_amd_common, inc_gallium_drivers, ], - + link_with : [ libgalliumvl ], dependencies: [dep_libdrm_radeon, dep_elf, dep_llvm, idep_nir, idep_nir_headers], ) diff --git a/src/gallium/drivers/r600/r600_pipe_common.c b/src/gallium/drivers/r600/r600_pipe_common.c index 1a5b4b89663..8a5f78db95f 100644 --- a/src/gallium/drivers/r600/r600_pipe_common.c +++ b/src/gallium/drivers/r600/r600_pipe_common.c @@ -37,6 +37,8 @@ #include "vl/vl_decoder.h" #include "vl/vl_video_buffer.h" #include "radeon_video.h" +#include "git_sha1.h" + #include #include #include @@ -1207,6 +1209,50 @@ static int r600_get_screen_fd(struct pipe_screen *screen) return ws->get_fd(ws); } +static void r600_get_driver_uuid(UNUSED struct pipe_screen *screen, char *uuid) +{ + const char *driver_id = PACKAGE_VERSION MESA_GIT_SHA1 "r600"; + + /* The driver UUID is used for determining sharability of images and + * memory between two Vulkan instances in separate processes, but also + * to determining memory objects and sharability between Vulkan and + * OpenGL driver. People who want to share memory need to also check + * the device UUID. + */ + struct mesa_sha1 sha1_ctx; + _mesa_sha1_init(&sha1_ctx); + + _mesa_sha1_update(&sha1_ctx, driver_id, strlen(driver_id)); + + uint8_t sha1[SHA1_DIGEST_LENGTH]; + _mesa_sha1_final(&sha1_ctx, sha1); + + assert(SHA1_DIGEST_LENGTH >= PIPE_UUID_SIZE); + memcpy(uuid, sha1, PIPE_UUID_SIZE); +} + +static void r600_get_device_uuid(struct pipe_screen *screen, char *uuid) +{ + uint32_t *uint_uuid = (uint32_t *)uuid; + struct r600_common_screen* rs = (struct r600_common_screen*)screen; + + assert(PIPE_UUID_SIZE >= sizeof(uint32_t) * 4); + + /* Copied from ac_device_info + * Use the device info directly instead of using a sha1. GL/VK UUIDs + * are 16 byte vs 20 byte for sha1, and the truncation that would be + * required would get rid of part of the little entropy we have. + */ + memset(uuid, 0, PIPE_UUID_SIZE); + if (!rs->info.pci.valid) + fprintf(stderr, + "r600 device_uuid output is based on invalid pci bus info.\n"); + uint_uuid[0] = rs->info.pci.domain; + uint_uuid[1] = rs->info.pci.bus; + uint_uuid[2] = rs->info.pci.dev; + uint_uuid[3] = rs->info.pci.func; +} + bool r600_common_screen_init(struct r600_common_screen *rscreen, struct radeon_winsys *ws) { @@ -1247,6 +1293,8 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen, rscreen->b.resource_destroy = r600_resource_destroy; rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory; rscreen->b.query_memory_info = r600_query_memory_info; + rscreen->b.get_device_uuid = r600_get_device_uuid; + rscreen->b.get_driver_uuid = r600_get_driver_uuid; if (rscreen->info.ip[AMD_IP_UVD].num_queues) { rscreen->b.get_video_param = rvid_get_video_param; diff --git a/src/gallium/drivers/r600/sfn/sfn_debug.cpp b/src/gallium/drivers/r600/sfn/sfn_debug.cpp index b41ebece948..4cca3af6704 100644 --- a/src/gallium/drivers/r600/sfn/sfn_debug.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_debug.cpp @@ -125,12 +125,13 @@ SfnTrace::SfnTrace(SfnLog::LogFlag flag, const char *msg): m_flag(flag), m_msg(msg) { - sfn_log << m_flag << std::string(" ", 2 * m_indention++) << "BEGIN: " << m_msg << "\n"; + sfn_log << m_flag << std::string( 2 * m_indention++, ' ') << "BEGIN: " << m_msg << "\n"; } SfnTrace::~SfnTrace() { - sfn_log << m_flag << std::string(" ", 2 * m_indention--) << "END: " << m_msg << "\n"; + assert(m_indention > 0); + sfn_log << m_flag << std::string( 2 * m_indention--, ' ') << "END: " << m_msg << "\n"; } int SfnTrace::m_indention = 0; diff --git a/src/gallium/drivers/r600/sfn/sfn_nir_lower_64bit.cpp b/src/gallium/drivers/r600/sfn/sfn_nir_lower_64bit.cpp index 6c82843ee51..b11c98c500a 100644 --- a/src/gallium/drivers/r600/sfn/sfn_nir_lower_64bit.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_nir_lower_64bit.cpp @@ -1026,7 +1026,8 @@ Lower64BitToVec2::load_64_to_vec2(nir_intrinsic_instr *intr) intr->num_components *= 2; intr->def.bit_size = 32; intr->def.num_components *= 2; - nir_intrinsic_set_component(intr, nir_intrinsic_component(intr) * 2); + if (nir_intrinsic_has_component(intr)) + nir_intrinsic_set_component(intr, nir_intrinsic_component(intr) * 2); return NIR_LOWER_INSTR_PROGRESS; } diff --git a/src/gallium/drivers/r600/sfn/sfn_optimizer.cpp b/src/gallium/drivers/r600/sfn/sfn_optimizer.cpp index c4d0a9fa727..5038b94ab6e 100644 --- a/src/gallium/drivers/r600/sfn/sfn_optimizer.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_optimizer.cpp @@ -375,7 +375,11 @@ CopyPropFwdVisitor::visit(AluInstr *instr) auto mov_block_id = instr->block_id(); - while(ii != ie) { + /** libc++ seems to invalidate the end iterator too if a std::set is + * made empty by an erase operation, + * https://gitlab.freedesktop.org/mesa/mesa/-/issues/7931 + */ + while(ii != ie && !dest->uses().empty()) { auto i = *ii; auto target_block_id = i->block_id(); diff --git a/src/gallium/drivers/r600/sfn/sfn_shader_cs.cpp b/src/gallium/drivers/r600/sfn/sfn_shader_cs.cpp index 4cd2d4c9243..9ae839dcdbe 100644 --- a/src/gallium/drivers/r600/sfn/sfn_shader_cs.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_shader_cs.cpp @@ -52,7 +52,9 @@ ComputeShader::do_allocate_reserved_registers() for (int i = 0; i < 3; ++i) { m_local_invocation_id[i] = vf.allocate_pinned_register(thread_id_sel, i); + m_local_invocation_id[i]->set_flag(Register::pin_end); m_workgroup_id[i] = vf.allocate_pinned_register(wg_id_sel, i); + m_workgroup_id[i]->set_flag(Register::pin_end); } return 2; } diff --git a/src/gallium/drivers/radeonsi/si_buffer.c b/src/gallium/drivers/radeonsi/si_buffer.c index 6196da9325f..7bddea1f488 100644 --- a/src/gallium/drivers/radeonsi/si_buffer.c +++ b/src/gallium/drivers/radeonsi/si_buffer.c @@ -70,6 +70,10 @@ void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res, */ if (!sscreen->info.is_amdgpu) res->domains = RADEON_DOMAIN_GTT; + +#if defined(PIPE_ARCH_AARCH64) + res->domains = RADEON_DOMAIN_GTT; +#endif } /* Tiled textures are unmappable. Always put them in VRAM. */ diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c index 567b8d1f2c8..9478e58035e 100644 --- a/src/gallium/drivers/radeonsi/si_gfx_cs.c +++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c @@ -369,6 +369,8 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs) if (!first_cs) u_trace_fini(&ctx->trace); + u_trace_init(&ctx->trace, &ctx->ds.trace_context); + if (unlikely(radeon_uses_secure_bos(ctx->ws))) { is_secure = ctx->ws->cs_is_secure(&ctx->gfx_cs); @@ -583,7 +585,6 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs) assert(!ctx->gfx_cs.prev_dw); ctx->initial_gfx_cs_size = ctx->gfx_cs.current.cdw; - u_trace_init(&ctx->trace, &ctx->ds.trace_context); /* All buffer references are removed on a flush, so si_check_needs_implicit_sync * cannot determine if si_make_CB_shader_coherent() needs to be called. * ctx->force_cb_shader_coherent will be cleared by the first call to diff --git a/src/gallium/drivers/radeonsi/si_pm4.c b/src/gallium/drivers/radeonsi/si_pm4.c index 58badc48a2d..bed0023eb64 100644 --- a/src/gallium/drivers/radeonsi/si_pm4.c +++ b/src/gallium/drivers/radeonsi/si_pm4.c @@ -135,7 +135,7 @@ void si_pm4_finalize(struct si_pm4_state *state) if (strstr(ac_get_register_name(state->screen->info.gfx_level, state->screen->info.family, reg_offset), "SPI_SHADER_PGM_LO_")) { - state->reg_va_low_idx = get_packed_reg_valueN_idx(state, i); + state->spi_shader_pgm_lo_reg = reg_offset; break; } } @@ -162,7 +162,8 @@ void si_pm4_finalize(struct si_pm4_state *state) if (strstr(ac_get_register_name(state->screen->info.gfx_level, state->screen->info.family, reg_base_offset + i * 4), "SPI_SHADER_PGM_LO_")) { - state->reg_va_low_idx = state->last_pm4 + 2 + i; + state->spi_shader_pgm_lo_reg = reg_base_offset + i * 4; + break; } } diff --git a/src/gallium/drivers/radeonsi/si_pm4.h b/src/gallium/drivers/radeonsi/si_pm4.h index 39f72ed4167..56a6b654d3a 100644 --- a/src/gallium/drivers/radeonsi/si_pm4.h +++ b/src/gallium/drivers/radeonsi/si_pm4.h @@ -45,7 +45,7 @@ struct si_pm4_state { uint16_t max_dw; /* Used by SQTT to override the shader address */ - uint16_t reg_va_low_idx; + uint32_t spi_shader_pgm_lo_reg; /* This must be the last field because the array can continue after the structure. */ uint32_t pm4[64]; diff --git a/src/gallium/drivers/radeonsi/si_shader_info.c b/src/gallium/drivers/radeonsi/si_shader_info.c index 4442d8af128..881458cc4a4 100644 --- a/src/gallium/drivers/radeonsi/si_shader_info.c +++ b/src/gallium/drivers/radeonsi/si_shader_info.c @@ -617,7 +617,7 @@ void si_nir_scan_shader(struct si_screen *sscreen, const struct nir_shader *nir, } /* tess factors are loaded as input instead of system value */ - info->reads_tess_factors = nir->info.patch_inputs_read & + info->reads_tess_factors = nir->info.inputs_read & (BITFIELD64_BIT(VARYING_SLOT_TESS_LEVEL_INNER) | BITFIELD64_BIT(VARYING_SLOT_TESS_LEVEL_OUTER)); diff --git a/src/gallium/drivers/radeonsi/si_sqtt.c b/src/gallium/drivers/radeonsi/si_sqtt.c index 63618e666be..f80d01a401f 100644 --- a/src/gallium/drivers/radeonsi/si_sqtt.c +++ b/src/gallium/drivers/radeonsi/si_sqtt.c @@ -677,12 +677,14 @@ void si_destroy_sqtt(struct si_context *sctx) { list_for_each_entry_safe(struct rgp_pso_correlation_record, record, &pso_correlation->record, list) { list_del(&record->list); + pso_correlation->record_count--; free(record); } list_for_each_entry_safe(struct rgp_loader_events_record, record, &loader_events->record, list) { list_del(&record->list); + loader_events->record_count--; free(record); } @@ -698,6 +700,7 @@ void si_destroy_sqtt(struct si_context *sctx) { } list_del(&record->list); free(record); + code_object->record_count--; } ac_sqtt_finish(sctx->sqtt); @@ -1028,7 +1031,7 @@ si_sqtt_add_code_object(struct si_context* sctx, struct rgp_code_object *code_object = &sctx->sqtt->rgp_code_object; struct rgp_code_object_record *record; - record = malloc(sizeof(struct rgp_code_object_record)); + record = calloc(1, sizeof(struct rgp_code_object_record)); if (!record) return false; diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index d7dfbff4d3d..6329e3218ea 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -1570,8 +1570,7 @@ static void si_emit_db_render_state(struct si_context *sctx, unsigned index) max_allowed_tiles_in_wave = 15; } - db_render_control |= S_028000_OREO_MODE(V_028000_OMODE_O_THEN_B) | - S_028000_MAX_ALLOWED_TILES_IN_WAVE(max_allowed_tiles_in_wave); + db_render_control |= S_028000_MAX_ALLOWED_TILES_IN_WAVE(max_allowed_tiles_in_wave); } /* DB_COUNT_CONTROL (occlusion queries) */ @@ -5442,6 +5441,7 @@ void si_init_state_functions(struct si_context *sctx) sctx->atoms.s.pm4_states[SI_STATE_IDX(rasterizer)].emit = si_pm4_emit_state; sctx->atoms.s.pm4_states[SI_STATE_IDX(dsa)].emit = si_pm4_emit_state; sctx->atoms.s.pm4_states[SI_STATE_IDX(poly_offset)].emit = si_pm4_emit_state; + sctx->atoms.s.pm4_states[SI_STATE_IDX(sqtt_pipeline)].emit = si_pm4_emit_state; sctx->atoms.s.pm4_states[SI_STATE_IDX(ls)].emit = si_pm4_emit_shader; sctx->atoms.s.pm4_states[SI_STATE_IDX(hs)].emit = si_pm4_emit_shader; sctx->atoms.s.pm4_states[SI_STATE_IDX(es)].emit = si_pm4_emit_shader; diff --git a/src/gallium/drivers/radeonsi/si_state_draw.cpp b/src/gallium/drivers/radeonsi/si_state_draw.cpp index 9b9858091a2..987765d8e33 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.cpp +++ b/src/gallium/drivers/radeonsi/si_state_draw.cpp @@ -370,9 +370,8 @@ static bool si_update_shaders(struct si_context *sctx) struct si_pm4_state *pm4 = &shader->pm4; - uint32_t va_low = (pipeline->bo->gpu_address + pipeline->offset[i]) >> 8; - assert(PKT3_IT_OPCODE_G(pm4->pm4[pm4->reg_va_low_idx - 2]) == PKT3_SET_SH_REG); - uint32_t reg = (pm4->pm4[pm4->reg_va_low_idx - 1] << 2) + SI_SH_REG_OFFSET; + uint64_t va_low = (pipeline->bo->gpu_address + pipeline->offset[i]) >> 8; + uint32_t reg = pm4->spi_shader_pgm_lo_reg; si_pm4_set_reg(&pipeline->pm4, reg, va_low); } } diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp index c6d0010e6c2..f71523b974e 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp +++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp @@ -1983,7 +1983,7 @@ static void si_shader_init_pm4_state(struct si_screen *sscreen, struct si_shader assert(0); } - assert(!(sscreen->debug_flags & DBG(SQTT)) || shader->pm4.reg_va_low_idx != 0); + assert(!(sscreen->debug_flags & DBG(SQTT)) || shader->pm4.spi_shader_pgm_lo_reg != 0); } static void si_clear_vs_key_inputs(struct si_context *sctx, union si_shader_key *key, @@ -4274,8 +4274,16 @@ static void si_set_patch_vertices(struct pipe_context *ctx, uint8_t patch_vertic if (sctx->patch_vertices != patch_vertices) { sctx->patch_vertices = patch_vertices; si_update_tess_in_out_patch_vertices(sctx); - if (sctx->shader.tcs.current) - si_update_tess_io_layout_state(sctx); + if (sctx->shader.tcs.current) { + /* Update the io layout now if possible, + * otherwise make sure it's done by si_update_shaders. + */ + if (sctx->tess_rings) + si_update_tess_io_layout_state(sctx); + else + sctx->do_update_shaders = true; + } + } } diff --git a/src/gallium/drivers/radeonsi/si_state_viewport.c b/src/gallium/drivers/radeonsi/si_state_viewport.c index c32584bbcf5..826020491ec 100644 --- a/src/gallium/drivers/radeonsi/si_state_viewport.c +++ b/src/gallium/drivers/radeonsi/si_state_viewport.c @@ -33,8 +33,14 @@ static void si_get_small_prim_cull_info(struct si_context *sctx, struct si_small line_width = roundf(line_width); line_width = MAX2(line_width, 1); - info.clip_half_line_width[0] = line_width * 0.5 / fabs(info.scale[0]); - info.clip_half_line_width[1] = line_width * 0.5 / fabs(info.scale[1]); + float half_line_width = line_width * 0.5; + if (info.scale[0] == 0 || info.scale[1] == 0) { + info.clip_half_line_width[0] = 0; + info.clip_half_line_width[1] = 0; + } else { + info.clip_half_line_width[0] = half_line_width / fabs(info.scale[0]); + info.clip_half_line_width[1] = half_line_width / fabs(info.scale[1]); + } /* If the Y axis is inverted (OpenGL default framebuffer), reverse it. * This is because the viewport transformation inverts the clip space diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index 16948db41a7..6003b71f40f 100644 --- a/src/gallium/drivers/radeonsi/si_texture.c +++ b/src/gallium/drivers/radeonsi/si_texture.c @@ -640,7 +640,9 @@ static bool si_resource_get_param(struct pipe_screen *screen, struct pipe_contex if (resource->target == PIPE_BUFFER) { *value = 0; } else { - uint64_t level_offset = tex->surface.is_linear ? tex->surface.u.gfx9.offset[level] : 0; + uint64_t level_offset = 0; + if (sscreen->info.gfx_level >= GFX9 && tex->surface.is_linear) + level_offset = tex->surface.u.gfx9.offset[level]; *value = ac_surface_get_plane_offset(sscreen->info.gfx_level, &tex->surface, plane, layer) + level_offset; } diff --git a/src/gallium/drivers/v3d/meson.build b/src/gallium/drivers/v3d/meson.build index 289473d2ca1..259c8e36291 100644 --- a/src/gallium/drivers/v3d/meson.build +++ b/src/gallium/drivers/v3d/meson.build @@ -77,11 +77,6 @@ foreach ver : v3d_versions endforeach -v3d_neon_c_args = [] -if host_machine.cpu_family() == 'arm' - v3d_neon_c_args = '-mfpu=neon' -endif - libv3d = static_library( 'v3d', [ diff --git a/src/gallium/drivers/v3d/v3d_resource.c b/src/gallium/drivers/v3d/v3d_resource.c index a0a210ccad5..7eec001c2ed 100644 --- a/src/gallium/drivers/v3d/v3d_resource.c +++ b/src/gallium/drivers/v3d/v3d_resource.c @@ -26,6 +26,7 @@ #include "util/u_memory.h" #include "util/format/u_format.h" #include "util/u_inlines.h" +#include "util/u_resource.h" #include "util/u_surface.h" #include "util/u_transfer_helper.h" #include "util/u_upload_mgr.h" @@ -99,7 +100,17 @@ v3d_resource_bo_alloc(struct v3d_resource *rsc) struct pipe_screen *pscreen = prsc->screen; struct v3d_bo *bo; - bo = v3d_bo_alloc(v3d_screen(pscreen), rsc->size, "resource"); + /* Buffers may be read using ldunifa, which prefetches the next + * 4 bytes after a read. If the buffer's size is exactly a multiple + * of a page size and the shader reads the last 4 bytes with ldunifa + * the prefetching would read out of bounds and cause an MMU error, + * so we allocate extra space to avoid kernel error spamming. + */ + uint32_t size = rsc->size; + if (rsc->base.target == PIPE_BUFFER && (size % 4096 == 0)) + size += 4; + + bo = v3d_bo_alloc(v3d_screen(pscreen), size, "resource"); if (bo) { v3d_bo_unreference(&rsc->bo); rsc->bo = bo; @@ -463,18 +474,22 @@ v3d_resource_get_param(struct pipe_screen *pscreen, enum pipe_resource_param param, unsigned usage, uint64_t *value) { - struct v3d_resource *rsc = v3d_resource(prsc); + struct v3d_resource *rsc = + (struct v3d_resource *)util_resource_at_index(prsc, plane); switch (param) { case PIPE_RESOURCE_PARAM_STRIDE: *value = rsc->slices[level].stride; return true; case PIPE_RESOURCE_PARAM_OFFSET: - *value = 0; + *value = rsc->slices[level].offset; return true; case PIPE_RESOURCE_PARAM_MODIFIER: *value = v3d_resource_modifier(rsc); return true; + case PIPE_RESOURCE_PARAM_NPLANES: + *value = util_resource_num(prsc); + return true; default: return false; } @@ -1007,6 +1022,9 @@ v3d_resource_from_handle(struct pipe_screen *pscreen, slice->stride = whandle->stride; } + /* Prevent implicit clearing of the imported buffer contents. */ + rsc->writes = 1; + return prsc; fail: diff --git a/src/gallium/drivers/v3d/v3dx_format_table.c b/src/gallium/drivers/v3d/v3dx_format_table.c index 78f6d955be3..2e72cb1bc3d 100644 --- a/src/gallium/drivers/v3d/v3dx_format_table.c +++ b/src/gallium/drivers/v3d/v3dx_format_table.c @@ -70,7 +70,9 @@ static const struct v3d_format format_table[] = { FORMAT(R8G8B8A8_SNORM, NO, RGBA8_SNORM, SWIZ_XYZW, 16, 0), FORMAT(R8G8B8X8_SNORM, NO, RGBA8_SNORM, SWIZ_XYZ1, 16, 0), FORMAT(R10G10B10A2_UNORM, RGB10_A2, RGB10_A2, SWIZ_XYZW, 16, 0), + FORMAT(B10G10R10A2_UNORM, RGB10_A2, RGB10_A2, SWIZ_ZYXW, 16, 0), FORMAT(R10G10B10X2_UNORM, RGB10_A2, RGB10_A2, SWIZ_XYZ1, 16, 0), + FORMAT(B10G10R10X2_UNORM, RGB10_A2, RGB10_A2, SWIZ_ZYX1, 16, 0), FORMAT(R10G10B10A2_UINT, RGB10_A2UI, RGB10_A2UI, SWIZ_XYZW, 16, 0), FORMAT(A4B4G4R4_UNORM, ABGR4444, RGBA4, SWIZ_XYZW, 16, 0), diff --git a/src/gallium/drivers/vc4/vc4_resource.c b/src/gallium/drivers/vc4/vc4_resource.c index 0a3a435a46c..e2acc4ad48f 100644 --- a/src/gallium/drivers/vc4/vc4_resource.c +++ b/src/gallium/drivers/vc4/vc4_resource.c @@ -26,6 +26,7 @@ #include "util/u_memory.h" #include "util/format/u_format.h" #include "util/u_inlines.h" +#include "util/u_resource.h" #include "util/u_surface.h" #include "util/u_transfer_helper.h" #include "util/u_upload_mgr.h" @@ -350,18 +351,22 @@ vc4_resource_get_param(struct pipe_screen *pscreen, enum pipe_resource_param param, unsigned usage, uint64_t *value) { - struct vc4_resource *rsc = vc4_resource(prsc); + struct vc4_resource *rsc = + (struct vc4_resource *)util_resource_at_index(prsc, plane); switch (param) { case PIPE_RESOURCE_PARAM_STRIDE: *value = rsc->slices[level].stride; return true; case PIPE_RESOURCE_PARAM_OFFSET: - *value = 0; + *value = rsc->slices[level].offset; return true; case PIPE_RESOURCE_PARAM_MODIFIER: *value = vc4_resource_modifier(rsc); return true; + case PIPE_RESOURCE_PARAM_NPLANES: + *value = util_resource_num(prsc); + return true; default: return false; } diff --git a/src/gallium/drivers/zink/VP_ZINK_requirements.json b/src/gallium/drivers/zink/VP_ZINK_requirements.json index 5dd50f0bd54..a1a09d8fa04 100644 --- a/src/gallium/drivers/zink/VP_ZINK_requirements.json +++ b/src/gallium/drivers/zink/VP_ZINK_requirements.json @@ -1,5 +1,5 @@ { - "$schema": "https://schema.khronos.org/vulkan/profiles-0.8.1-251.json", + "$schema": "https://schema.khronos.org/vulkan/profiles-0.8.2-271.json", "capabilities": { "vulkan10requirements": { "features": { @@ -164,7 +164,7 @@ "VkPhysicalDeviceMaintenance4Features": { "maintenance4": true }, - "VkPhysicalDeviceMaintenance5Features": { + "VkPhysicalDeviceMaintenance5FeaturesKHR": { "maintenance5": true } }, diff --git a/src/gallium/drivers/zink/ci/traces-zink.yml b/src/gallium/drivers/zink/ci/traces-zink.yml index 889020419ed..a94101a6230 100644 --- a/src/gallium/drivers/zink/ci/traces-zink.yml +++ b/src/gallium/drivers/zink/ci/traces-zink.yml @@ -22,11 +22,6 @@ traces: label: [skip, broken, flakes] checksum: 9b5090a236350f04cb2a61c5f0c0fe0f text: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8986 - freedoom/freedoom-phase2-gl-high.trace: - gl-zink-anv-tgl: - label: [skip] - text: "Fails on CI as well as when run locally" - checksum: 288b762ac80ed76e18f848649a618be1 glxgears/glxgears-2-v2.trace: gl-zink-anv-tgl: checksum: f53ac20e17da91c0359c31f2fa3f401e diff --git a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c index b9d0398d1b7..dc964b85024 100644 --- a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c +++ b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c @@ -1853,7 +1853,6 @@ emit_alu(struct ntv_context *ctx, nir_alu_instr *alu) UNOP(nir_op_f2f64, SpvOpFConvert) UNOP(nir_op_bitfield_reverse, SpvOpBitReverse) UNOP(nir_op_bit_count, SpvOpBitCount) - UNOP(nir_op_fisnormal, SpvOpIsNormal) #undef UNOP case nir_op_f2f16_rtz: @@ -3295,6 +3294,7 @@ emit_intrinsic(struct ntv_context *ctx, nir_intrinsic_instr *intr) break; case nir_intrinsic_load_sample_id: + spirv_builder_emit_cap(&ctx->builder, SpvCapabilitySampleRateShading); emit_load_uint_input(ctx, intr, &ctx->sample_id_var, "gl_SampleId", SpvBuiltInSampleId); break; @@ -4663,7 +4663,7 @@ nir_to_spirv(struct nir_shader *s, const struct zink_shader_info *sinfo, uint32_ spirv_builder_emit_cap(&ctx.builder, SpvCapabilitySubgroupBallotKHR); spirv_builder_emit_extension(&ctx.builder, "SPV_KHR_shader_ballot"); } - if (s->info.has_transform_feedback_varyings) { + if (s->info.has_transform_feedback_varyings && s->info.stage != MESA_SHADER_FRAGMENT) { spirv_builder_emit_cap(&ctx.builder, SpvCapabilityTransformFeedback); spirv_builder_emit_exec_mode(&ctx.builder, entry_point, SpvExecutionModeXfb); diff --git a/src/gallium/drivers/zink/zink_batch.c b/src/gallium/drivers/zink/zink_batch.c index 7e3b268fc0c..533d3e0abc4 100644 --- a/src/gallium/drivers/zink/zink_batch.c +++ b/src/gallium/drivers/zink/zink_batch.c @@ -414,6 +414,18 @@ get_batch_state(struct zink_context *ctx, struct zink_batch *batch) if (bs == ctx->last_free_batch_state) ctx->last_free_batch_state = NULL; } + /* try from the ones that are given back to the screen next */ + if (!bs) { + simple_mtx_lock(&screen->free_batch_states_lock); + if (screen->free_batch_states) { + bs = screen->free_batch_states; + bs->ctx = ctx; + screen->free_batch_states = bs->next; + if (bs == screen->last_free_batch_state) + screen->last_free_batch_state = NULL; + } + simple_mtx_unlock(&screen->free_batch_states_lock); + } if (!bs && ctx->batch_states) { /* states are stored sequentially, so if the first one doesn't work, none of them will */ if (zink_screen_check_last_finished(screen, ctx->batch_states->fence.batch_id) || diff --git a/src/gallium/drivers/zink/zink_blit.c b/src/gallium/drivers/zink/zink_blit.c index 1fe9a27459f..7b711905814 100644 --- a/src/gallium/drivers/zink/zink_blit.c +++ b/src/gallium/drivers/zink/zink_blit.c @@ -122,6 +122,18 @@ blit_resolve(struct zink_context *ctx, const struct pipe_blit_info *info, bool * region.extent.width = info->dst.box.width; region.extent.height = info->dst.box.height; region.extent.depth = info->dst.box.depth; + if (region.srcOffset.x + region.extent.width >= u_minify(src->base.b.width0, region.srcSubresource.mipLevel)) + region.extent.width = u_minify(src->base.b.width0, region.srcSubresource.mipLevel) - region.srcOffset.x; + if (region.dstOffset.x + region.extent.width >= u_minify(dst->base.b.width0, region.dstSubresource.mipLevel)) + region.extent.width = u_minify(dst->base.b.width0, region.dstSubresource.mipLevel) - region.dstOffset.x; + if (region.srcOffset.y + region.extent.height >= u_minify(src->base.b.height0, region.srcSubresource.mipLevel)) + region.extent.height = u_minify(src->base.b.height0, region.srcSubresource.mipLevel) - region.srcOffset.y; + if (region.dstOffset.y + region.extent.height >= u_minify(dst->base.b.height0, region.dstSubresource.mipLevel)) + region.extent.height = u_minify(dst->base.b.height0, region.dstSubresource.mipLevel) - region.dstOffset.y; + if (region.srcOffset.z + region.extent.depth >= u_minify(src->base.b.depth0, region.srcSubresource.mipLevel)) + region.extent.depth = u_minify(src->base.b.depth0, region.srcSubresource.mipLevel) - region.srcOffset.z; + if (region.dstOffset.z + region.extent.depth >= u_minify(dst->base.b.depth0, region.dstSubresource.mipLevel)) + region.extent.depth = u_minify(dst->base.b.depth0, region.dstSubresource.mipLevel) - region.dstOffset.z; VKCTX(CmdResolveImage)(cmdbuf, use_src->obj->image, src->layout, dst->obj->image, dst->layout, 1, ®ion); diff --git a/src/gallium/drivers/zink/zink_bo.c b/src/gallium/drivers/zink/zink_bo.c index 14aaca63759..ddd428897ee 100644 --- a/src/gallium/drivers/zink/zink_bo.c +++ b/src/gallium/drivers/zink/zink_bo.c @@ -256,10 +256,6 @@ bo_create_internal(struct zink_screen *screen, struct zink_bo *bo = NULL; bool init_pb_cache; - /* too big for vk alloc */ - if (size > UINT32_MAX) - return NULL; - alignment = get_optimal_alignment(screen, size, alignment); VkMemoryAllocateFlagsInfo ai; @@ -963,7 +959,7 @@ zink_bo_commit(struct zink_screen *screen, struct zink_resource *res, unsigned l simple_mtx_lock(&screen->queue_lock); simple_mtx_lock(&bo->lock); if (res->base.b.target == PIPE_BUFFER) { - ok = buffer_bo_commit(screen, res, box->x, box->width, commit, sem); + ok = buffer_bo_commit(screen, res, box->x, box->width, commit, &cur_sem); goto out; } @@ -1132,8 +1128,8 @@ zink_bo_commit(struct zink_screen *screen, struct zink_resource *res, unsigned l fprintf(stderr, "zink: leaking sparse backing memory\n"); } } + ok = false; } - ok = false; } out: diff --git a/src/gallium/drivers/zink/zink_compiler.c b/src/gallium/drivers/zink/zink_compiler.c index 014b6cccdd7..4400d686a0c 100644 --- a/src/gallium/drivers/zink/zink_compiler.c +++ b/src/gallium/drivers/zink/zink_compiler.c @@ -1212,6 +1212,7 @@ zink_screen_init_compiler(struct zink_screen *screen) .lower_fsat = true, .lower_hadd = true, .lower_iadd_sat = true, + .lower_fisnormal = true, .lower_extract_byte = true, .lower_extract_word = true, .lower_insert_byte = true, @@ -2776,6 +2777,11 @@ zink_compiler_assign_io(struct zink_screen *screen, nir_shader *producer, nir_sh optimize_nir(producer, NULL, true); } } + if (consumer->info.stage != MESA_SHADER_FRAGMENT) { + producer->info.has_transform_feedback_varyings = false; + nir_foreach_shader_out_variable(var, producer) + var->data.explicit_xfb_buffer = false; + } if (producer->info.stage == MESA_SHADER_TESS_CTRL) { /* never assign from tcs -> tes, always invert */ nir_foreach_variable_with_modes(var, consumer, nir_var_shader_in) diff --git a/src/gallium/drivers/zink/zink_context.c b/src/gallium/drivers/zink/zink_context.c index f8e742fc9cf..f4716527883 100644 --- a/src/gallium/drivers/zink/zink_context.c +++ b/src/gallium/drivers/zink/zink_context.c @@ -124,7 +124,9 @@ zink_context_destroy(struct pipe_context *pctx) if (util_queue_is_initialized(&screen->flush_queue)) util_queue_finish(&screen->flush_queue); if (ctx->batch.state && !screen->device_lost) { + simple_mtx_lock(&screen->queue_lock); VkResult result = VKSCR(QueueWaitIdle)(screen->queue); + simple_mtx_unlock(&screen->queue_lock); if (result != VK_SUCCESS) mesa_loge("ZINK: vkQueueWaitIdle failed (%s)", vk_Result_to_str(result)); @@ -159,16 +161,41 @@ zink_context_destroy(struct pipe_context *pctx) while (bs) { struct zink_batch_state *bs_next = bs->next; zink_clear_batch_state(ctx, bs); - zink_batch_state_destroy(screen, bs); + /* restore link as we insert them into the screens free_batch_states + * list below + */ + bs->next = bs_next; bs = bs_next; } bs = ctx->free_batch_states; while (bs) { struct zink_batch_state *bs_next = bs->next; zink_clear_batch_state(ctx, bs); - zink_batch_state_destroy(screen, bs); + /* restore link as we insert them into the screens free_batch_states + * list below + */ + bs->next = bs_next; bs = bs_next; } + simple_mtx_lock(&screen->free_batch_states_lock); + if (ctx->batch_states) { + if (screen->free_batch_states) + screen->last_free_batch_state->next = ctx->batch_states; + else { + screen->free_batch_states = ctx->batch_states; + screen->last_free_batch_state = screen->free_batch_states; + } + while (screen->last_free_batch_state->next) + screen->last_free_batch_state = screen->last_free_batch_state->next; + } + if (ctx->free_batch_states) { + if (screen->free_batch_states) + screen->last_free_batch_state->next = ctx->free_batch_states; + else + screen->free_batch_states = ctx->free_batch_states; + screen->last_free_batch_state = ctx->last_free_batch_state; + } + simple_mtx_unlock(&screen->free_batch_states_lock); if (ctx->batch.state) { zink_clear_batch_state(ctx, ctx->batch.state); zink_batch_state_destroy(screen, ctx->batch.state); @@ -231,6 +258,11 @@ zink_context_destroy(struct pipe_context *pctx) if (!(ctx->flags & ZINK_CONTEXT_COPY_ONLY)) p_atomic_dec(&screen->base.num_contexts); + util_dynarray_foreach(&ctx->di.global_bindings, struct pipe_resource *, res) { + pipe_resource_reference(res, NULL); + } + util_dynarray_fini(&ctx->di.global_bindings); + ralloc_free(ctx); } @@ -702,7 +734,7 @@ update_descriptor_state_sampler(struct zink_context *ctx, gl_shader_stage shader if (res->obj->is_buffer) { if (zink_descriptor_mode == ZINK_DESCRIPTOR_MODE_DB) { ctx->di.db.tbos[shader][slot].address = res->obj->bda + ctx->sampler_views[shader][slot]->u.buf.offset; - ctx->di.db.tbos[shader][slot].range = ctx->sampler_views[shader][slot]->u.buf.size; + ctx->di.db.tbos[shader][slot].range = zink_sampler_view(ctx->sampler_views[shader][slot])->tbo_size; ctx->di.db.tbos[shader][slot].format = zink_get_format(screen, ctx->sampler_views[shader][slot]->format); } else { struct zink_buffer_view *bv = get_bufferview_for_binding(ctx, shader, type, slot); @@ -1192,8 +1224,12 @@ zink_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *pres, } err = !sampler_view->image_view; } else { - if (zink_descriptor_mode == ZINK_DESCRIPTOR_MODE_DB) + if (zink_descriptor_mode == ZINK_DESCRIPTOR_MODE_DB) { + /* always enforce limit clamping */ + unsigned blocksize = util_format_get_blocksize(state->format); + sampler_view->tbo_size = MIN2(state->u.buf.size / blocksize, screen->info.props.limits.maxTexelBufferElements) * blocksize; return &sampler_view->base; + } VkBufferViewCreateInfo bvci = create_bvci(ctx, res, state->format, state->u.buf.offset, state->u.buf.size); sampler_view->buffer_view = get_buffer_view(ctx, res, &bvci); err = !sampler_view->buffer_view; @@ -1231,9 +1267,10 @@ zink_sampler_view_destroy(struct pipe_context *pctx, struct pipe_sampler_view *pview) { struct zink_sampler_view *view = zink_sampler_view(pview); - if (pview->texture->target == PIPE_BUFFER) - zink_buffer_view_reference(zink_screen(pctx->screen), &view->buffer_view, NULL); - else { + if (pview->texture->target == PIPE_BUFFER) { + if (zink_descriptor_mode != ZINK_DESCRIPTOR_MODE_DB) + zink_buffer_view_reference(zink_screen(pctx->screen), &view->buffer_view, NULL); + } else { zink_surface_reference(zink_screen(pctx->screen), &view->image_view, NULL); zink_surface_reference(zink_screen(pctx->screen), &view->cube_array, NULL); zink_surface_reference(zink_screen(pctx->screen), &view->zs_view, NULL); @@ -1914,6 +1951,11 @@ zink_set_shader_images(struct pipe_context *pctx, zink_resource_access_is_write(access), false); } memcpy(&a->base, images + i, sizeof(struct pipe_image_view)); + if (b->resource->target == PIPE_BUFFER) { + /* always enforce limit clamping */ + unsigned blocksize = util_format_get_blocksize(a->base.format); + a->base.u.buf.size = MIN2(a->base.u.buf.size / blocksize, screen->info.props.limits.maxTexelBufferElements) * blocksize; + } update = true; res->image_binds[shader_type] |= BITFIELD_BIT(start_slot + i); } else if (a->base.resource) { @@ -4841,7 +4883,7 @@ zink_rebind_all_images(struct zink_context *ctx) for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) { for (unsigned j = 0; j < ctx->di.num_sampler_views[i]; j++) { struct zink_sampler_view *sv = zink_sampler_view(ctx->sampler_views[i][j]); - if (!sv || sv->image_view->base.texture->target == PIPE_BUFFER || !sv->image_view) + if (!sv || !sv->image_view || sv->image_view->base.texture->target == PIPE_BUFFER) continue; struct zink_resource *res = zink_resource(sv->image_view->base.texture); if (res->obj != sv->image_view->obj) { diff --git a/src/gallium/drivers/zink/zink_draw.cpp b/src/gallium/drivers/zink/zink_draw.cpp index 11e7295fe82..0eee77f1d72 100644 --- a/src/gallium/drivers/zink/zink_draw.cpp +++ b/src/gallium/drivers/zink/zink_draw.cpp @@ -819,7 +819,8 @@ zink_draw(struct pipe_context *pctx, if ((BATCH_CHANGED || ctx->blend_state_changed)) { if (ctx->gfx_pipeline_state.blend_state) { if (ctx->ds3_states & BITFIELD_BIT(ZINK_DS3_BLEND_A2C)) - VKCTX(CmdSetAlphaToCoverageEnableEXT)(batch->state->cmdbuf, ctx->gfx_pipeline_state.blend_state->alpha_to_coverage); + VKCTX(CmdSetAlphaToCoverageEnableEXT)(batch->state->cmdbuf, ctx->gfx_pipeline_state.blend_state->alpha_to_coverage && + ctx->gfx_stages[MESA_SHADER_FRAGMENT]->info.outputs_written & BITFIELD_BIT(FRAG_RESULT_DATA0)); if (ctx->ds3_states & BITFIELD_BIT(ZINK_DS3_BLEND_A21)) VKCTX(CmdSetAlphaToOneEnableEXT)(batch->state->cmdbuf, ctx->gfx_pipeline_state.blend_state->alpha_to_one); if (ctx->fb_state.nr_cbufs) { diff --git a/src/gallium/drivers/zink/zink_kopper.c b/src/gallium/drivers/zink/zink_kopper.c index d1e9a57b20f..bda4c206877 100644 --- a/src/gallium/drivers/zink/zink_kopper.c +++ b/src/gallium/drivers/zink/zink_kopper.c @@ -318,7 +318,9 @@ kopper_CreateSwapchain(struct zink_screen *screen, struct kopper_displaytarget * if (error == VK_ERROR_NATIVE_WINDOW_IN_USE_KHR) { if (util_queue_is_initialized(&screen->flush_queue)) util_queue_finish(&screen->flush_queue); + simple_mtx_lock(&screen->queue_lock); VkResult result = VKSCR(QueueWaitIdle)(screen->queue); + simple_mtx_unlock(&screen->queue_lock); if (result != VK_SUCCESS) mesa_loge("ZINK: vkQueueWaitIdle failed (%s)", vk_Result_to_str(result)); error = VKSCR(CreateSwapchainKHR)(screen->dev, &cswap->scci, NULL, diff --git a/src/gallium/drivers/zink/zink_program.c b/src/gallium/drivers/zink/zink_program.c index 796cc258a4f..e50ad9c9c91 100644 --- a/src/gallium/drivers/zink/zink_program.c +++ b/src/gallium/drivers/zink/zink_program.c @@ -1367,6 +1367,7 @@ create_compute_program(struct zink_context *ctx, nir_shader *nir) struct zink_compute_program *comp = create_program(ctx, true); if (!comp) return NULL; + simple_mtx_init(&comp->cache_lock, mtx_plain); comp->scratch_size = nir->scratch_size; comp->nir = nir; comp->num_inlinable_uniforms = nir->info.num_inlinable_uniforms; @@ -1595,6 +1596,7 @@ zink_get_compute_pipeline(struct zink_screen *screen, struct zink_compute_pipeline_state *state) { struct hash_entry *entry = NULL; + struct compute_pipeline_cache_entry *cache_entry; if (!state->dirty && !state->module_changed) return state->pipeline; @@ -1617,30 +1619,42 @@ zink_get_compute_pipeline(struct zink_screen *screen, entry = _mesa_hash_table_search_pre_hashed(&comp->pipelines, state->final_hash, state); if (!entry) { + simple_mtx_lock(&comp->cache_lock); + entry = _mesa_hash_table_search_pre_hashed(&comp->pipelines, state->final_hash, state); + if (entry) { + simple_mtx_unlock(&comp->cache_lock); + goto out; + } VkPipeline pipeline = zink_create_compute_pipeline(screen, comp, state); - if (pipeline == VK_NULL_HANDLE) + if (pipeline == VK_NULL_HANDLE) { + simple_mtx_unlock(&comp->cache_lock); return VK_NULL_HANDLE; + } zink_screen_update_pipeline_cache(screen, &comp->base, false); if (compute_can_shortcut(comp)) { + simple_mtx_unlock(&comp->cache_lock); /* don't add base pipeline to cache */ state->pipeline = comp->base_pipeline = pipeline; return state->pipeline; } struct compute_pipeline_cache_entry *pc_entry = CALLOC_STRUCT(compute_pipeline_cache_entry); - if (!pc_entry) + if (!pc_entry) { + simple_mtx_unlock(&comp->cache_lock); return VK_NULL_HANDLE; + } memcpy(&pc_entry->state, state, sizeof(*state)); pc_entry->pipeline = pipeline; entry = _mesa_hash_table_insert_pre_hashed(&comp->pipelines, state->final_hash, pc_entry, pc_entry); assert(entry); + simple_mtx_unlock(&comp->cache_lock); } - - struct compute_pipeline_cache_entry *cache_entry = entry->data; +out: + cache_entry = entry->data; state->pipeline = cache_entry->pipeline; return state->pipeline; } @@ -1850,11 +1864,18 @@ zink_bind_fs_state(struct pipe_context *pctx, zink_set_null_fs(ctx); return; } + bool writes_cbuf0 = ctx->gfx_stages[MESA_SHADER_FRAGMENT] ? (ctx->gfx_stages[MESA_SHADER_FRAGMENT]->info.outputs_written & BITFIELD_BIT(FRAG_RESULT_DATA0)) > 0 : true; unsigned shadow_mask = ctx->gfx_stages[MESA_SHADER_FRAGMENT] ? ctx->gfx_stages[MESA_SHADER_FRAGMENT]->fs.legacy_shadow_mask : 0; bind_gfx_stage(ctx, MESA_SHADER_FRAGMENT, cso); ctx->fbfetch_outputs = 0; if (cso) { shader_info *info = &ctx->gfx_stages[MESA_SHADER_FRAGMENT]->info; + bool new_writes_cbuf0 = (info->outputs_written & BITFIELD_BIT(FRAG_RESULT_DATA0)) > 0; + if (ctx->gfx_pipeline_state.blend_state && ctx->gfx_pipeline_state.blend_state->alpha_to_coverage && + writes_cbuf0 != new_writes_cbuf0 && zink_screen(pctx->screen)->info.have_EXT_extended_dynamic_state3) { + ctx->blend_state_changed = true; + ctx->ds3_states |= BITFIELD_BIT(ZINK_DS3_BLEND_A2C); + } if (info->fs.uses_fbfetch_output) { if (info->outputs_read & (BITFIELD_BIT(FRAG_RESULT_DEPTH) | BITFIELD_BIT(FRAG_RESULT_STENCIL))) ctx->fbfetch_outputs |= BITFIELD_BIT(PIPE_MAX_COLOR_BUFS); diff --git a/src/gallium/drivers/zink/zink_resource.c b/src/gallium/drivers/zink/zink_resource.c index b1442eabfa7..121663a72ef 100644 --- a/src/gallium/drivers/zink/zink_resource.c +++ b/src/gallium/drivers/zink/zink_resource.c @@ -359,6 +359,7 @@ check_ici(struct zink_screen *screen, VkImageCreateInfo *ici, uint64_t modifier) mod_info.drmFormatModifier = modifier; mod_info.sharingMode = VK_SHARING_MODE_EXCLUSIVE; mod_info.queueFamilyIndexCount = 0; + mod_info.pQueueFamilyIndices = NULL; info.pNext = &mod_info; } @@ -697,6 +698,7 @@ init_ici(struct zink_screen *screen, VkImageCreateInfo *ici, const struct pipe_r ici->flags |= VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT; ici->usage = 0; ici->queueFamilyIndexCount = 0; + ici->pQueueFamilyIndices = NULL; /* assume we're going to be doing some CompressedTexSubImage */ if (util_format_is_compressed(templ->format) && (ici->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) && @@ -776,6 +778,7 @@ resource_object_create(struct zink_screen *screen, const struct pipe_resource *t return NULL; simple_mtx_init(&obj->view_lock, mtx_plain); util_dynarray_init(&obj->views, NULL); + u_rwlock_init(&obj->copy_lock); obj->unordered_read = true; obj->unordered_write = true; obj->last_dt_idx = obj->dt_idx = UINT32_MAX; //TODO: unionize @@ -846,6 +849,14 @@ resource_object_create(struct zink_screen *screen, const struct pipe_resource *t return obj; } else if (templ->target == PIPE_BUFFER) { VkBufferCreateInfo bci = create_bci(screen, templ, templ->bind); + VkExternalMemoryBufferCreateInfo embci; + + if (user_mem) { + embci.sType = VK_STRUCTURE_TYPE_EXTERNAL_MEMORY_BUFFER_CREATE_INFO; + embci.pNext = bci.pNext; + embci.handleTypes = VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT; + bci.pNext = &embci; + } if (VKSCR(CreateBuffer)(screen->dev, &bci, NULL, &obj->buffer) != VK_SUCCESS) { mesa_loge("ZINK: vkCreateBuffer failed"); @@ -982,6 +993,11 @@ resource_object_create(struct zink_screen *screen, const struct pipe_resource *t } else if (ici.tiling == VK_IMAGE_TILING_OPTIMAL) { shared = false; } + } else if (user_mem) { + emici.sType = VK_STRUCTURE_TYPE_EXTERNAL_MEMORY_IMAGE_CREATE_INFO; + emici.pNext = ici.pNext; + emici.handleTypes = VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT; + ici.pNext = &emici; } if (linear) @@ -2560,6 +2576,7 @@ zink_resource_copy_box_intersects(struct zink_resource *res, unsigned level, con /* untracked huge miplevel */ if (level >= ARRAY_SIZE(res->obj->copies)) return true; + u_rwlock_rdlock(&res->obj->copy_lock); struct pipe_box *b = res->obj->copies[level].data; unsigned num_boxes = util_dynarray_num_elements(&res->obj->copies[level], struct pipe_box); bool (*intersect)(const struct pipe_box *, const struct pipe_box *); @@ -2580,18 +2597,23 @@ zink_resource_copy_box_intersects(struct zink_resource *res, unsigned level, con break; } /* if any of the tracked boxes intersect with this one, a barrier is needed */ + bool ret = false; for (unsigned i = 0; i < num_boxes; i++) { - if (intersect(box, b + i)) - return true; + if (intersect(box, b + i)) { + ret = true; + break; + } } + u_rwlock_rdunlock(&res->obj->copy_lock); /* no intersection = no barrier */ - return false; + return ret; } /* track a new region for TRANSFER_DST barrier emission */ void zink_resource_copy_box_add(struct zink_context *ctx, struct zink_resource *res, unsigned level, const struct pipe_box *box) { + u_rwlock_wrlock(&res->obj->copy_lock); if (res->obj->copies_valid) { struct pipe_box *b = res->obj->copies[level].data; unsigned num_boxes = util_dynarray_num_elements(&res->obj->copies[level], struct pipe_box); @@ -2601,23 +2623,23 @@ zink_resource_copy_box_add(struct zink_context *ctx, struct zink_resource *res, case PIPE_TEXTURE_1D: /* no-op included region */ if (b[i].x <= box->x && b[i].x + b[i].width >= box->x + box->width) - return; + goto out; /* try to merge adjacent regions */ if (b[i].x == box->x + box->width) { b[i].x -= box->width; b[i].width += box->width; - return; + goto out; } if (b[i].x + b[i].width == box->x) { b[i].width += box->width; - return; + goto out; } /* try to merge into region */ if (box->x <= b[i].x && box->x + box->width >= b[i].x + b[i].width) { *b = *box; - return; + goto out; } break; @@ -2626,28 +2648,28 @@ zink_resource_copy_box_add(struct zink_context *ctx, struct zink_resource *res, /* no-op included region */ if (b[i].x <= box->x && b[i].x + b[i].width >= box->x + box->width && b[i].y <= box->y && b[i].y + b[i].height >= box->y + box->height) - return; + goto out; /* try to merge adjacent regions */ if (b[i].y == box->y && b[i].height == box->height) { if (b[i].x == box->x + box->width) { b[i].x -= box->width; b[i].width += box->width; - return; + goto out; } if (b[i].x + b[i].width == box->x) { b[i].width += box->width; - return; + goto out; } } else if (b[i].x == box->x && b[i].width == box->width) { if (b[i].y == box->y + box->height) { b[i].y -= box->height; b[i].height += box->height; - return; + goto out; } if (b[i].y + b[i].height == box->y) { b[i].height += box->height; - return; + goto out; } } @@ -2655,7 +2677,7 @@ zink_resource_copy_box_add(struct zink_context *ctx, struct zink_resource *res, if (box->x <= b[i].x && box->x + box->width >= b[i].x + b[i].width && box->y <= b[i].y && box->y + box->height >= b[i].y + b[i].height) { *b = *box; - return; + goto out; } break; @@ -2664,7 +2686,7 @@ zink_resource_copy_box_add(struct zink_context *ctx, struct zink_resource *res, if (b[i].x <= box->x && b[i].x + b[i].width >= box->x + box->width && b[i].y <= box->y && b[i].y + b[i].height >= box->y + box->height && b[i].z <= box->z && b[i].z + b[i].depth >= box->z + box->depth) - return; + goto out; /* try to merge adjacent regions */ if (b[i].z == box->z && b[i].depth == box->depth) { @@ -2672,21 +2694,21 @@ zink_resource_copy_box_add(struct zink_context *ctx, struct zink_resource *res, if (b[i].x == box->x + box->width) { b[i].x -= box->width; b[i].width += box->width; - return; + goto out; } if (b[i].x + b[i].width == box->x) { b[i].width += box->width; - return; + goto out; } } else if (b[i].x == box->x && b[i].width == box->width) { if (b[i].y == box->y + box->height) { b[i].y -= box->height; b[i].height += box->height; - return; + goto out; } if (b[i].y + b[i].height == box->y) { b[i].height += box->height; - return; + goto out; } } } else if (b[i].x == box->x && b[i].width == box->width) { @@ -2694,21 +2716,21 @@ zink_resource_copy_box_add(struct zink_context *ctx, struct zink_resource *res, if (b[i].z == box->z + box->depth) { b[i].z -= box->depth; b[i].depth += box->depth; - return; + goto out; } if (b[i].z + b[i].depth == box->z) { b[i].depth += box->depth; - return; + goto out; } } else if (b[i].z == box->z && b[i].depth == box->depth) { if (b[i].y == box->y + box->height) { b[i].y -= box->height; b[i].height += box->height; - return; + goto out; } if (b[i].y + b[i].height == box->y) { b[i].height += box->height; - return; + goto out; } } } else if (b[i].y == box->y && b[i].height == box->height) { @@ -2716,21 +2738,21 @@ zink_resource_copy_box_add(struct zink_context *ctx, struct zink_resource *res, if (b[i].x == box->x + box->width) { b[i].x -= box->width; b[i].width += box->width; - return; + goto out; } if (b[i].x + b[i].width == box->x) { b[i].width += box->width; - return; + goto out; } } else if (b[i].x == box->x && b[i].width == box->width) { if (b[i].z == box->z + box->depth) { b[i].z -= box->depth; b[i].depth += box->depth; - return; + goto out; } if (b[i].z + b[i].depth == box->z) { b[i].depth += box->depth; - return; + goto out; } } } @@ -2739,7 +2761,7 @@ zink_resource_copy_box_add(struct zink_context *ctx, struct zink_resource *res, if (box->x <= b[i].x && box->x + box->width >= b[i].x + b[i].width && box->y <= b[i].y && box->y + box->height >= b[i].y + b[i].height && box->z <= b[i].z && box->z + box->depth >= b[i].z + b[i].depth) - return; + goto out; break; } @@ -2752,6 +2774,8 @@ zink_resource_copy_box_add(struct zink_context *ctx, struct zink_resource *res, res->copies_warned = true; } res->obj->copies_valid = true; +out: + u_rwlock_wrunlock(&res->obj->copy_lock); } void @@ -2759,6 +2783,7 @@ zink_resource_copies_reset(struct zink_resource *res) { if (!res->obj->copies_valid) return; + u_rwlock_wrlock(&res->obj->copy_lock); unsigned max_level = res->base.b.target == PIPE_BUFFER ? 1 : (res->base.b.last_level + 1); if (res->base.b.target == PIPE_BUFFER) { /* flush transfer regions back to valid range on reset */ @@ -2771,6 +2796,7 @@ zink_resource_copies_reset(struct zink_resource *res) util_dynarray_clear(&res->obj->copies[i]); res->obj->copies_valid = false; res->obj->copies_need_reset = false; + u_rwlock_wrunlock(&res->obj->copy_lock); } static void diff --git a/src/gallium/drivers/zink/zink_screen.c b/src/gallium/drivers/zink/zink_screen.c index 74b575ed658..cccc901df8f 100644 --- a/src/gallium/drivers/zink/zink_screen.c +++ b/src/gallium/drivers/zink/zink_screen.c @@ -55,8 +55,13 @@ #include #include #include +#ifdef MAJOR_IN_MKDEV +#include +#endif +#ifdef MAJOR_IN_SYSMACROS #include #endif +#endif static int num_screens = 0; bool zink_tracing = false; @@ -1456,6 +1461,12 @@ static void zink_destroy_screen(struct pipe_screen *pscreen) { struct zink_screen *screen = zink_screen(pscreen); + struct zink_batch_state *bs = screen->free_batch_states; + while (bs) { + struct zink_batch_state *bs_next = bs->next; + zink_batch_state_destroy(screen, bs); + bs = bs_next; + } #ifdef HAVE_RENDERDOC_APP_H if (screen->renderdoc_capture_all && p_atomic_dec_zero(&num_screens)) @@ -1520,10 +1531,14 @@ zink_destroy_screen(struct pipe_screen *pscreen) if (screen->dev) VKSCR(DestroyDevice)(screen->dev, NULL); - VKSCR(DestroyInstance)(screen->instance, NULL); + if (screen->instance) + VKSCR(DestroyInstance)(screen->instance, NULL); + util_idalloc_mt_fini(&screen->buffer_ids); - util_dl_close(screen->loader_lib); + if (screen->loader_lib) + util_dl_close(screen->loader_lib); + if (screen->drm_fd != -1) close(screen->drm_fd); @@ -1628,6 +1643,12 @@ choose_pdev(struct zink_screen *screen, int64_t dev_major, int64_t dev_minor) } VKSCR(GetPhysicalDeviceProperties)(screen->pdev, &screen->info.props); + /* allow software rendering only if forced by the user */ + if (!cpu && screen->info.props.deviceType == VK_PHYSICAL_DEVICE_TYPE_CPU) { + screen->pdev = VK_NULL_HANDLE; + return; + } + screen->info.device_version = screen->info.props.apiVersion; /* runtime version is the lesser of the instance version and device version */ @@ -2434,8 +2455,12 @@ zink_query_dmabuf_modifiers(struct pipe_screen *pscreen, enum pipe_format format { struct zink_screen *screen = zink_screen(pscreen); *count = screen->modifier_props[format].drmFormatModifierCount; - for (int i = 0; i < MIN2(max, *count); i++) + for (int i = 0; i < MIN2(max, *count); i++) { + if (external_only) + external_only[i] = 0; + modifiers[i] = screen->modifier_props[format].pDrmFormatModifierProperties[i].drmFormatModifier; + } } static bool @@ -2875,6 +2900,7 @@ init_driver_workarounds(struct zink_screen *screen) /* these drivers can successfully do INVALID <-> LINEAR dri3 modifier swap */ switch (screen->info.driver_props.driverID) { case VK_DRIVER_ID_MESA_TURNIP: + case VK_DRIVER_ID_MESA_VENUS: screen->driver_workarounds.can_do_invalid_linear_modifier = true; break; default: @@ -3115,6 +3141,8 @@ zink_internal_create_screen(const struct pipe_screen_config *config, int64_t dev return NULL; } + screen->drm_fd = -1; + glsl_type_singleton_init_or_ref(); zink_debug = debug_get_option_zink_debug(); if (zink_descriptor_mode == ZINK_DESCRIPTOR_MODE_AUTO) @@ -3478,6 +3506,7 @@ zink_internal_create_screen(const struct pipe_screen_config *config, int64_t dev screen->base_descriptor_size = MAX4(screen->db_size[0], screen->db_size[1], screen->db_size[2], screen->db_size[3]); } + simple_mtx_init(&screen->free_batch_states_lock, mtx_plain); simple_mtx_init(&screen->dt_lock, mtx_plain); util_idalloc_mt_init_tc(&screen->buffer_ids); diff --git a/src/gallium/drivers/zink/zink_types.h b/src/gallium/drivers/zink/zink_types.h index 05d3633869e..b6477e3244a 100644 --- a/src/gallium/drivers/zink/zink_types.h +++ b/src/gallium/drivers/zink/zink_types.h @@ -1148,6 +1148,8 @@ struct zink_compute_program { struct zink_shader *shader; struct hash_table pipelines; + simple_mtx_t cache_lock; //extra lock because threads are insane and sand was not meant to think + VkPipeline base_pipeline; }; @@ -1231,6 +1233,7 @@ struct zink_resource_object { bool copies_valid; bool copies_need_reset; //for use with batch state resets + struct u_rwlock copy_lock; struct util_dynarray copies[16]; //regions being copied to; for barrier omission VkBuffer storage_buffer; @@ -1398,6 +1401,10 @@ struct zink_screen { simple_mtx_t copy_context_lock; struct zink_context *copy_context; + struct zink_batch_state *free_batch_states; //unused batch states + struct zink_batch_state *last_free_batch_state; //for appending + simple_mtx_t free_batch_states_lock; + simple_mtx_t semaphores_lock; struct util_dynarray semaphores; struct util_dynarray fd_semaphores; @@ -1661,6 +1668,7 @@ struct zink_sampler_view { union { struct zink_surface *image_view; struct zink_buffer_view *buffer_view; + unsigned tbo_size; }; struct zink_surface *cube_array; /* Optional sampler view returning red (depth) in all channels, for shader rewrites. */ diff --git a/src/gallium/frontends/dri/dri_util.c b/src/gallium/frontends/dri/dri_util.c index 2476121634a..201fc7f63d4 100644 --- a/src/gallium/frontends/dri/dri_util.c +++ b/src/gallium/frontends/dri/dri_util.c @@ -326,7 +326,7 @@ driGetConfigAttribIndex(const __DRIconfig *config, * for the X server's sake, and EGL will expect us to handle it because * it iterates all __DRI_ATTRIBs. */ - *value = __DRI_ATTRIB_SWAP_EXCHANGE; + *value = __DRI_ATTRIB_SWAP_UNDEFINED; break; case __DRI_ATTRIB_MAX_SWAP_INTERVAL: *value = INT_MAX; diff --git a/src/gallium/frontends/rusticl/api/queue.rs b/src/gallium/frontends/rusticl/api/queue.rs index 01e8e115639..ff1e09a00d7 100644 --- a/src/gallium/frontends/rusticl/api/queue.rs +++ b/src/gallium/frontends/rusticl/api/queue.rs @@ -212,13 +212,7 @@ fn flush(command_queue: cl_command_queue) -> CLResult<()> { #[cl_entrypoint] fn finish(command_queue: cl_command_queue) -> CLResult<()> { // CL_INVALID_COMMAND_QUEUE if command_queue is not a valid host command-queue. - let q = command_queue.get_ref()?; - - for q in q.dependencies_for_pending_events() { - q.flush(false)?; - } - - q.flush(true) + command_queue.get_ref()?.flush(true) } #[cl_entrypoint] diff --git a/src/gallium/frontends/rusticl/core/device.rs b/src/gallium/frontends/rusticl/core/device.rs index 2565598edac..0a5e07ffb5a 100644 --- a/src/gallium/frontends/rusticl/core/device.rs +++ b/src/gallium/frontends/rusticl/core/device.rs @@ -750,8 +750,12 @@ impl Device { } pub fn image_buffer_size(&self) -> usize { - self.screen - .param(pipe_cap::PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT) as usize + min( + // the CTS requires it to not exceed `CL_MAX_MEM_ALLOC_SIZE` + self.max_mem_alloc(), + self.screen + .param(pipe_cap::PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT) as cl_ulong, + ) as usize } pub fn image_read_count(&self) -> cl_uint { @@ -852,7 +856,7 @@ impl Device { pub fn param_max_size(&self) -> usize { min( self.shader_param(pipe_shader_cap::PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE) as u32, - 32 * 1024, + 4 * 1024, ) as usize } diff --git a/src/gallium/frontends/rusticl/core/kernel.rs b/src/gallium/frontends/rusticl/core/kernel.rs index 09ab0bd4b29..7a268670bec 100644 --- a/src/gallium/frontends/rusticl/core/kernel.rs +++ b/src/gallium/frontends/rusticl/core/kernel.rs @@ -734,6 +734,10 @@ pub(super) fn convert_spirv_to_nir( */ nir.preserve_fp16_denorms(); + // Set to rtne for now until drivers are able to report their prefered rounding mode, that + // also matches what we report via the API. + nir.set_fp_rounding_mode_rtne(); + let (args, internal_args) = lower_and_optimize_nir(dev, &mut nir, args, &dev.lib_clc); if let Some(cache) = cache { @@ -919,10 +923,20 @@ impl Kernel { } else { let format = mem.pipe_format; let (formats, orders) = if arg.kind == KernelArgType::Image { - iviews.push(res.pipe_image_view(format, false, app_img_info.as_ref())); + iviews.push(res.pipe_image_view( + format, + false, + mem.pipe_image_host_access(), + app_img_info.as_ref(), + )); (&mut img_formats, &mut img_orders) } else if arg.kind == KernelArgType::RWImage { - iviews.push(res.pipe_image_view(format, true, app_img_info.as_ref())); + iviews.push(res.pipe_image_view( + format, + true, + mem.pipe_image_host_access(), + app_img_info.as_ref(), + )); (&mut img_formats, &mut img_orders) } else { sviews.push((res.clone(), format, app_img_info)); diff --git a/src/gallium/frontends/rusticl/core/memory.rs b/src/gallium/frontends/rusticl/core/memory.rs index c7f3c3b888f..55cf3747f4a 100644 --- a/src/gallium/frontends/rusticl/core/memory.rs +++ b/src/gallium/frontends/rusticl/core/memory.rs @@ -1231,6 +1231,19 @@ impl Mem { Ok(()) } + + pub fn pipe_image_host_access(&self) -> u16 { + // those flags are all mutually exclusive + (if bit_check(self.flags, CL_MEM_HOST_READ_ONLY) { + PIPE_IMAGE_ACCESS_READ + } else if bit_check(self.flags, CL_MEM_HOST_WRITE_ONLY) { + PIPE_IMAGE_ACCESS_WRITE + } else if bit_check(self.flags, CL_MEM_HOST_NO_ACCESS) { + 0 + } else { + PIPE_IMAGE_ACCESS_READ_WRITE + }) as u16 + } } impl Drop for Mem { diff --git a/src/gallium/frontends/rusticl/core/platform.rs b/src/gallium/frontends/rusticl/core/platform.rs index 24f60f2af9d..d9605092ca5 100644 --- a/src/gallium/frontends/rusticl/core/platform.rs +++ b/src/gallium/frontends/rusticl/core/platform.rs @@ -79,6 +79,7 @@ fn load_env() { "clc" => debug.clc = true, "program" => debug.program = true, "sync" => debug.sync_every_event = true, + "" => (), _ => eprintln!("Unknown RUSTICL_DEBUG flag found: {}", flag), } } @@ -90,6 +91,7 @@ fn load_env() { match flag { "fp16" => features.fp16 = true, "fp64" => features.fp64 = true, + "" => (), _ => eprintln!("Unknown RUSTICL_FEATURES flag found: {}", flag), } } diff --git a/src/gallium/frontends/rusticl/core/queue.rs b/src/gallium/frontends/rusticl/core/queue.rs index 364b4272487..bd58247b7d9 100644 --- a/src/gallium/frontends/rusticl/core/queue.rs +++ b/src/gallium/frontends/rusticl/core/queue.rs @@ -9,16 +9,17 @@ use mesa_rust::pipe::context::PipeContext; use mesa_rust_util::properties::*; use rusticl_opencl_gen::*; -use std::collections::HashSet; +use std::mem; use std::sync::mpsc; use std::sync::Arc; use std::sync::Mutex; +use std::sync::Weak; use std::thread; use std::thread::JoinHandle; struct QueueState { pending: Vec>, - last: Option>, + last: Weak, // `Sync` on `Sender` was stabilized in 1.72, until then, put it into our Mutex. // see https://github.com/rust-lang/rust/commit/5f56956b3c7edb9801585850d1f41b0aeb1888ff chan_in: mpsc::Sender>>, @@ -62,7 +63,7 @@ impl Queue { props_v2: props_v2, state: Mutex::new(QueueState { pending: Vec::new(), - last: None, + last: Weak::new(), chan_in: tx_q, }), _thrd: thread::Builder::new() @@ -130,33 +131,41 @@ impl Queue { pub fn flush(&self, wait: bool) -> CLResult<()> { let mut state = self.state.lock().unwrap(); + let events = mem::take(&mut state.pending); + let mut queues = Event::deep_unflushed_queues(&events); // Update last if and only if we get new events, this prevents breaking application code // doing things like `clFlush(q); clFinish(q);` - if let Some(last) = state.pending.last() { - state.last = Some(last.clone()); + if let Some(last) = events.last() { + state.last = Arc::downgrade(last); + + // This should never ever error, but if it does return an error + state + .chan_in + .send(events) + .map_err(|_| CL_OUT_OF_HOST_MEMORY)?; } - let events = state.pending.drain(0..).collect(); - // This should never ever error, but if it does return an error - state - .chan_in - .send(events) - .map_err(|_| CL_OUT_OF_HOST_MEMORY)?; - if wait { - // Waiting on the last event is good enough here as the queue will process it in order, - // also take the value so we can release the event once we are done - state.last.take().map(|e| e.wait()); - } - Ok(()) - } + let last = wait.then(|| state.last.clone()); - pub fn dependencies_for_pending_events(&self) -> HashSet> { - let state = self.state.lock().unwrap(); + // We have to unlock before actually flushing otherwise we'll run into dead locks when a + // queue gets flushed concurrently. + drop(state); - let mut queues = Event::deep_unflushed_queues(&state.pending); + // We need to flush out other queues implicitly and this _has_ to happen after taking the + // pending events, otherwise we'll risk dead locks when waiting on events. queues.remove(self); - queues + for q in queues { + q.flush(false)?; + } + + if let Some(last) = last { + // Waiting on the last event is good enough here as the queue will process it in order + // It's not a problem if the weak ref is invalid as that means the work is already done + // and waiting isn't necessary anymore. + last.upgrade().map(|e| e.wait()); + } + Ok(()) } pub fn is_profiling_enabled(&self) -> bool { diff --git a/src/gallium/frontends/rusticl/mesa/compiler/nir.rs b/src/gallium/frontends/rusticl/mesa/compiler/nir.rs index bb5fafdc261..b61ec9254a9 100644 --- a/src/gallium/frontends/rusticl/mesa/compiler/nir.rs +++ b/src/gallium/frontends/rusticl/mesa/compiler/nir.rs @@ -446,6 +446,15 @@ impl NirShader { } } + pub fn set_fp_rounding_mode_rtne(&mut self) { + unsafe { + self.nir.as_mut().info.float_controls_execution_mode |= + float_controls::FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 as u32 + | float_controls::FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32 as u32 + | float_controls::FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64 as u32; + } + } + pub fn reads_sysval(&self, sysval: gl_system_value) -> bool { let nir = unsafe { self.nir.as_ref() }; bitset::test_bit(&nir.info.system_values_read, sysval as u32) diff --git a/src/gallium/frontends/rusticl/mesa/pipe/resource.rs b/src/gallium/frontends/rusticl/mesa/pipe/resource.rs index 521b8c5f908..3b8075610ca 100644 --- a/src/gallium/frontends/rusticl/mesa/pipe/resource.rs +++ b/src/gallium/frontends/rusticl/mesa/pipe/resource.rs @@ -82,6 +82,7 @@ impl PipeResource { &self, format: pipe_format, read_write: bool, + host_access: u16, app_img_info: Option<&AppImgInfo>, ) -> pipe_image_view { let u = if let Some(app_img_info) = app_img_info { @@ -130,7 +131,7 @@ impl PipeResource { pipe_image_view { resource: self.pipe(), format: format, - access: access, + access: access | host_access, shader_access: shader_access, u: u, } diff --git a/src/gallium/frontends/rusticl/mesa/pipe/screen.rs b/src/gallium/frontends/rusticl/mesa/pipe/screen.rs index 9428bc0b98d..c3272f4c321 100644 --- a/src/gallium/frontends/rusticl/mesa/pipe/screen.rs +++ b/src/gallium/frontends/rusticl/mesa/pipe/screen.rs @@ -216,7 +216,7 @@ impl PipeScreen { tmpl.height0 = height; tmpl.depth0 = depth; tmpl.array_size = array_size; - tmpl.bind = PIPE_BIND_SAMPLER_VIEW; + tmpl.bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_LINEAR; if support_image { tmpl.bind |= PIPE_BIND_SHADER_IMAGE; @@ -234,9 +234,13 @@ impl PipeScreen { } fn compute_param_wrapped(&self, cap: pipe_compute_cap, ptr: *mut c_void) -> i32 { - let s = &mut unsafe { *self.screen }; unsafe { - s.get_compute_param.unwrap()(self.screen, pipe_shader_ir::PIPE_SHADER_IR_NIR, cap, ptr) + (*self.screen).get_compute_param.unwrap()( + self.screen, + pipe_shader_ir::PIPE_SHADER_IR_NIR, + cap, + ptr, + ) } } @@ -245,10 +249,7 @@ impl PipeScreen { } pub fn name(&self) -> String { - unsafe { - let s = *self.screen; - c_string_to_string(s.get_name.unwrap()(self.screen)) - } + unsafe { c_string_to_string((*self.screen).get_name.unwrap()(self.screen)) } } pub fn device_node_mask(&self) -> Option { @@ -274,10 +275,7 @@ impl PipeScreen { } pub fn device_vendor(&self) -> String { - unsafe { - let s = *self.screen; - c_string_to_string(s.get_device_vendor.unwrap()(self.screen)) - } + unsafe { c_string_to_string((*self.screen).get_device_vendor.unwrap()(self.screen)) } } pub fn device_type(&self) -> pipe_loader_device_type { @@ -296,9 +294,7 @@ impl PipeScreen { pub fn cl_cts_version(&self) -> &CStr { unsafe { - let s = *self.screen; - - let ptr = s + let ptr = (*self.screen) .get_cl_cts_version .map_or(ptr::null(), |get_cl_cts_version| { get_cl_cts_version(self.screen) @@ -318,8 +314,9 @@ impl PipeScreen { target: pipe_texture_target, bindings: u32, ) -> bool { - let s = &mut unsafe { *self.screen }; - unsafe { s.is_format_supported.unwrap()(self.screen, format, target, 0, 0, bindings) } + unsafe { + (*self.screen).is_format_supported.unwrap()(self.screen, format, target, 0, 0, bindings) + } } pub fn get_timestamp(&self) -> u64 { @@ -346,9 +343,7 @@ impl PipeScreen { } pub fn shader_cache(&self) -> Option { - let s = &mut unsafe { *self.screen }; - - let ptr = if let Some(func) = s.get_disk_shader_cache { + let ptr = if let Some(func) = unsafe { *self.screen }.get_disk_shader_cache { unsafe { func(self.screen) } } else { ptr::null_mut() @@ -358,8 +353,7 @@ impl PipeScreen { } pub fn finalize_nir(&self, nir: &NirShader) { - let s = &mut unsafe { *self.screen }; - if let Some(func) = s.finalize_nir { + if let Some(func) = unsafe { *self.screen }.finalize_nir { unsafe { func(self.screen, nir.get_nir().cast()); } @@ -368,15 +362,18 @@ impl PipeScreen { pub(super) fn unref_fence(&self, mut fence: *mut pipe_fence_handle) { unsafe { - let s = &mut *self.screen; - s.fence_reference.unwrap()(s, &mut fence, ptr::null_mut()); + (*self.screen).fence_reference.unwrap()(self.screen, &mut fence, ptr::null_mut()); } } pub(super) fn fence_finish(&self, fence: *mut pipe_fence_handle) { unsafe { - let s = &mut *self.screen; - s.fence_finish.unwrap()(s, ptr::null_mut(), fence, OS_TIMEOUT_INFINITE as u64); + (*self.screen).fence_finish.unwrap()( + self.screen, + ptr::null_mut(), + fence, + OS_TIMEOUT_INFINITE as u64, + ); } } } diff --git a/src/gallium/frontends/rusticl/meson.build b/src/gallium/frontends/rusticl/meson.build index d7aee75240c..32a8bb85d4e 100644 --- a/src/gallium/frontends/rusticl/meson.build +++ b/src/gallium/frontends/rusticl/meson.build @@ -91,6 +91,13 @@ rusticl_args = [ '-Aclippy::type_complexity', ] +if rustc.version().version_compare('>=1.72') + rusticl_args += [ + # Needs to be fixed + '-Aclippy::arc-with-non-send-sync' + ] +endif + rusticl_gen_args = [ # can't do anything about it anyway '-Aclippy::all', @@ -114,7 +121,17 @@ rusticl_bindgen_args = [ '--anon-fields-prefix', 'anon_', ] -if find_program('bindgen').version().version_compare('< 0.65') +bindgen_version = find_program('bindgen').version() + +if bindgen_version == 'unknown' + error('Failed to detect bindgen version. If you are using bindgen 0.69.0, please either update to 0.69.1 or downgrade to 0.68.1. You can install the latest version for your user with `cargo install bindgen-cli`.') +endif + +if bindgen_version.version_compare('< 0.62') + error('rusticl requires bindgen 0.62 or newer. If your distribution does not ship a recent enough version, you can install the latest version for your user with `cargo install bindgen-cli`.') +endif + +if bindgen_version.version_compare('< 0.65') rusticl_bindgen_args += [ '--size_t-is-usize', ] diff --git a/src/gallium/frontends/va/buffer.c b/src/gallium/frontends/va/buffer.c index dd160439aa6..c1f4d9d882d 100644 --- a/src/gallium/frontends/va/buffer.c +++ b/src/gallium/frontends/va/buffer.c @@ -173,6 +173,11 @@ VAStatus vlVaMapBuffer2(VADriverContextP ctx, VABufferID buf_id, usage = PIPE_MAP_READ; else usage = PIPE_MAP_WRITE; + + /* Map decoder and postproc surfaces also for reading. */ + if (buf->derived_surface.entrypoint == PIPE_VIDEO_ENTRYPOINT_BITSTREAM || + buf->derived_surface.entrypoint == PIPE_VIDEO_ENTRYPOINT_PROCESSING) + usage |= PIPE_MAP_READ; } if (flags & VA_MAPBUFFER_FLAG_READ) diff --git a/src/gallium/frontends/va/context.c b/src/gallium/frontends/va/context.c index 4f4f0ff5656..310a47d3f50 100644 --- a/src/gallium/frontends/va/context.c +++ b/src/gallium/frontends/va/context.c @@ -139,9 +139,6 @@ VA_DRIVER_INIT_FUNC(VADriverContextP ctx) break; } #else - case VA_DISPLAY_ANDROID: - FREE(drv); - return VA_STATUS_ERROR_UNIMPLEMENTED; case VA_DISPLAY_GLX: case VA_DISPLAY_X11: drv->vscreen = vl_dri3_screen_create(ctx->native_dpy, ctx->x11_screen); @@ -152,7 +149,8 @@ VA_DRIVER_INIT_FUNC(VADriverContextP ctx) break; case VA_DISPLAY_WAYLAND: case VA_DISPLAY_DRM: - case VA_DISPLAY_DRM_RENDERNODES: { + case VA_DISPLAY_DRM_RENDERNODES: + case VA_DISPLAY_ANDROID: { const struct drm_state *drm_info = (struct drm_state *) ctx->drm_state; if (!drm_info || drm_info->fd < 0) { diff --git a/src/gallium/frontends/va/image.c b/src/gallium/frontends/va/image.c index d109646d3ff..98d423f2a4d 100644 --- a/src/gallium/frontends/va/image.c +++ b/src/gallium/frontends/va/image.c @@ -435,6 +435,9 @@ vlVaDeriveImage(VADriverContextP ctx, VASurfaceID surface, VAImage *image) pipe_resource_reference(&img_buf->derived_surface.resource, surfaces[0]->texture); img_buf->derived_image_buffer = new_buffer; + if (surf->ctx) + img_buf->derived_surface.entrypoint = surf->ctx->templat.entrypoint; + img->buf = handle_table_add(VL_VA_DRIVER(ctx)->htab, img_buf); mtx_unlock(&drv->mutex); diff --git a/src/gallium/frontends/va/picture.c b/src/gallium/frontends/va/picture.c index 4c9339ff481..ffedf77d0c8 100644 --- a/src/gallium/frontends/va/picture.c +++ b/src/gallium/frontends/va/picture.c @@ -1148,7 +1148,7 @@ vlVaEndPicture(VADriverContextP ctx, VAContextID context_id) context->desc.h264enc.frame_num_cnt++; /* keep other path the same way */ - if (!screen->get_video_param(screen, ProfileToPipe(context->templat.profile), + if (!screen->get_video_param(screen, context->templat.profile, context->decoder->entrypoint, PIPE_VIDEO_CAP_ENC_QUALITY_LEVEL)) { diff --git a/src/gallium/frontends/va/va_private.h b/src/gallium/frontends/va/va_private.h index 5df1bdb6d70..df80a60623c 100644 --- a/src/gallium/frontends/va/va_private.h +++ b/src/gallium/frontends/va/va_private.h @@ -316,6 +316,7 @@ typedef struct { struct { struct pipe_resource *resource; struct pipe_transfer *transfer; + enum pipe_video_entrypoint entrypoint; } derived_surface; unsigned int export_refcount; VABufferInfo export_state; diff --git a/src/gbm/backends/dri/gbm_dri.c b/src/gbm/backends/dri/gbm_dri.c index 91fcc1fd29f..bbfa70ec1ce 100644 --- a/src/gbm/backends/dri/gbm_dri.c +++ b/src/gbm/backends/dri/gbm_dri.c @@ -472,6 +472,82 @@ static const struct gbm_dri_visual gbm_dri_visuals_table[] = { { 16, 16, 16, 16 }, true, }, + { + GBM_FORMAT_YUYV, __DRI_IMAGE_FORMAT_NONE, + .is_yuv = true, + }, + { + GBM_FORMAT_YVYU, __DRI_IMAGE_FORMAT_NONE, + .is_yuv = true, + }, + { + GBM_FORMAT_UYVY, __DRI_IMAGE_FORMAT_NONE, + .is_yuv = true, + }, + { + GBM_FORMAT_VYUY, __DRI_IMAGE_FORMAT_NONE, + .is_yuv = true, + }, + { + GBM_FORMAT_AYUV, __DRI_IMAGE_FORMAT_NONE, + .is_yuv = true, + }, + { + GBM_FORMAT_NV12, __DRI_IMAGE_FORMAT_NONE, + .is_yuv = true, + }, + { + GBM_FORMAT_NV21, __DRI_IMAGE_FORMAT_NONE, + .is_yuv = true, + }, + { + GBM_FORMAT_NV16, __DRI_IMAGE_FORMAT_NONE, + .is_yuv = true, + }, + { + GBM_FORMAT_NV61, __DRI_IMAGE_FORMAT_NONE, + .is_yuv = true, + }, + { + GBM_FORMAT_YUV410, __DRI_IMAGE_FORMAT_NONE, + .is_yuv = true, + }, + { + GBM_FORMAT_YVU410, __DRI_IMAGE_FORMAT_NONE, + .is_yuv = true, + }, + { + GBM_FORMAT_YUV411, __DRI_IMAGE_FORMAT_NONE, + .is_yuv = true, + }, + { + GBM_FORMAT_YVU411, __DRI_IMAGE_FORMAT_NONE, + .is_yuv = true, + }, + { + GBM_FORMAT_YUV420, __DRI_IMAGE_FORMAT_NONE, + .is_yuv = true, + }, + { + GBM_FORMAT_YVU420, __DRI_IMAGE_FORMAT_NONE, + .is_yuv = true, + }, + { + GBM_FORMAT_YUV422, __DRI_IMAGE_FORMAT_NONE, + .is_yuv = true, + }, + { + GBM_FORMAT_YVU422, __DRI_IMAGE_FORMAT_NONE, + .is_yuv = true, + }, + { + GBM_FORMAT_YUV444, __DRI_IMAGE_FORMAT_NONE, + .is_yuv = true, + }, + { + GBM_FORMAT_YVU444, __DRI_IMAGE_FORMAT_NONE, + .is_yuv = true, + }, }; static int diff --git a/src/gbm/backends/dri/gbm_driint.h b/src/gbm/backends/dri/gbm_driint.h index 76f6194aa8a..e055b73feff 100644 --- a/src/gbm/backends/dri/gbm_driint.h +++ b/src/gbm/backends/dri/gbm_driint.h @@ -58,6 +58,7 @@ struct gbm_dri_visual { unsigned int alpha; } rgba_sizes; bool is_float; + bool is_yuv; }; struct gbm_dri_device { diff --git a/src/glx/glxext.c b/src/glx/glxext.c index 7712e54c1d6..39d5f08bdcf 100644 --- a/src/glx/glxext.c +++ b/src/glx/glxext.c @@ -563,12 +563,11 @@ __glXInitializeVisualConfigFromTags(struct glx_config * config, int count, case GLX_SAMPLES_SGIS: config->samples = *bp++; break; -#ifdef GLX_USE_APPLEGL case IGNORE_GLX_SWAP_METHOD_OML: /* We ignore this tag. See the comment above this function. */ ++bp; break; -#else +#ifndef GLX_USE_APPLEGL case GLX_BIND_TO_TEXTURE_RGB_EXT: config->bindToTextureRgb = *bp++; break; diff --git a/src/imagination/vulkan/pvr_device.c b/src/imagination/vulkan/pvr_device.c index e533b7ca549..de995688680 100644 --- a/src/imagination/vulkan/pvr_device.c +++ b/src/imagination/vulkan/pvr_device.c @@ -591,6 +591,12 @@ static bool pvr_physical_device_get_properties( /* Vulkan 1.2 / VK_KHR_timeline_semaphore */ .maxTimelineSemaphoreValueDifference = UINT64_MAX, + + /* Vulkan 1.3 / VK_EXT_texel_buffer_alignment */ + .storageTexelBufferOffsetAlignmentBytes = 16, + .storageTexelBufferOffsetSingleTexelAlignment = true, + .uniformTexelBufferOffsetAlignmentBytes = 16, + .uniformTexelBufferOffsetSingleTexelAlignment = false, }; snprintf(properties->deviceName, diff --git a/src/intel/ci/gitlab-ci-inc.yml b/src/intel/ci/gitlab-ci-inc.yml index 928740a15ab..8e70bba5327 100644 --- a/src/intel/ci/gitlab-ci-inc.yml +++ b/src/intel/ci/gitlab-ci-inc.yml @@ -118,7 +118,7 @@ - !reference [.vulkan-manual-rules, rules] - changes: - src/intel/**/* - when: on_success + when: manual # ruleset to trigger on changes affecting either anv or iris, for jobs using both (piglit, skqp) .intel-rules: diff --git a/src/intel/ci/traces-iris.yml b/src/intel/ci/traces-iris.yml index 59cb3403cc5..7bc335c1738 100644 --- a/src/intel/ci/traces-iris.yml +++ b/src/intel/ci/traces-iris.yml @@ -514,19 +514,6 @@ traces: checksum: f11aa01f5ef3a563567e2a85998c418e gl-intel-cml: checksum: f11aa01f5ef3a563567e2a85998c418e - freedoom/freedoom-phase2-gl-high.trace: - gl-intel-apl: - checksum: b9951727c5c869d5ca510d83a557711b - gl-intel-glx: - checksum: b9951727c5c869d5ca510d83a557711b - gl-intel-amly: - checksum: b9951727c5c869d5ca510d83a557711b - gl-intel-kbl: - checksum: b9951727c5c869d5ca510d83a557711b - gl-intel-whl: - checksum: b9951727c5c869d5ca510d83a557711b - gl-intel-cml: - checksum: b9951727c5c869d5ca510d83a557711b unvanquished/unvanquished-lowest.trace: gl-intel-apl: checksum: 884096b6dd40e2f500d0837501287fac diff --git a/src/intel/common/i915/intel_engine.c b/src/intel/common/i915/intel_engine.c index cc5d9bc6b7a..6d99df53da7 100644 --- a/src/intel/common/i915/intel_engine.c +++ b/src/intel/common/i915/intel_engine.c @@ -25,7 +25,7 @@ #include -#include "intel_gem.h" +#include "i915/intel_gem.h" static enum intel_engine_class i915_engine_class_to_intel(enum drm_i915_gem_engine_class i915) diff --git a/src/intel/common/intel_aux_map.c b/src/intel/common/intel_aux_map.c index 5fddd995502..f66b664ed3b 100644 --- a/src/intel/common/intel_aux_map.c +++ b/src/intel/common/intel_aux_map.c @@ -183,14 +183,33 @@ struct aux_map_buffer { struct intel_buffer *buffer; }; +struct intel_aux_level { + /* GPU address of the current level */ + uint64_t address; + + /* Pointer to the GPU entries of this level */ + uint64_t *entries; + + union { + /* Host tracking of a parent level to its children (only use on L3/L2 + * levels which have 4096 entries) + */ + struct intel_aux_level *children[4096]; + + /* Refcount of AUX pages at the L1 level (MTL has only 16 entries in L1, + * which Gfx12 has 256 entries) + */ + uint32_t ref_counts[256]; + }; +}; + struct intel_aux_map_context { void *driver_ctx; pthread_mutex_t mutex; + struct intel_aux_level *l3_level; struct intel_mapped_pinned_buffer_alloc *buffer_alloc; uint32_t num_buffers; struct list_head buffers; - uint64_t level3_base_addr; - uint64_t *level3_map; uint32_t tail_offset, tail_remaining; uint32_t state_num; const struct aux_format_info *format; @@ -250,7 +269,7 @@ select_format(const struct intel_device_info *devinfo) static bool add_buffer(struct intel_aux_map_context *ctx) { - struct aux_map_buffer *buf = ralloc(ctx, struct aux_map_buffer); + struct aux_map_buffer *buf = rzalloc(ctx, struct aux_map_buffer); if (!buf) return false; @@ -312,20 +331,31 @@ get_current_pos(struct intel_aux_map_context *ctx, uint64_t *gpu, uint64_t **map *map = (uint64_t*)((uint8_t*)tail->buffer->map + ctx->tail_offset); } -static bool -add_sub_table(struct intel_aux_map_context *ctx, uint32_t size, - uint32_t align, uint64_t *gpu, uint64_t **map) +static struct intel_aux_level * +add_sub_table(struct intel_aux_map_context *ctx, + struct intel_aux_level *parent, + uint32_t parent_index, + uint32_t size, uint32_t align) { if (!align_and_verify_space(ctx, size, align)) { if (!add_buffer(ctx)) - return false; + return NULL; UNUSED bool aligned = align_and_verify_space(ctx, size, align); assert(aligned); } - get_current_pos(ctx, gpu, map); - memset(*map, 0, size); + + struct intel_aux_level *level = rzalloc(ctx, struct intel_aux_level); + + get_current_pos(ctx, &level->address, &level->entries); + memset(level->entries, 0, size); advance_current_pos(ctx, size); - return true; + + if (parent != NULL) { + assert(parent->children[parent_index] == NULL); + parent->children[parent_index] = level; + } + + return level; } uint32_t @@ -361,11 +391,12 @@ intel_aux_map_init(void *driver_ctx, ctx->tail_remaining = 0; ctx->state_num = 0; - if (add_sub_table(ctx, L3_L2_SUB_TABLE_LEN, L3_L2_SUB_TABLE_LEN, - &ctx->level3_base_addr, &ctx->level3_map)) { + ctx->l3_level = add_sub_table(ctx, NULL, 0, + L3_L2_SUB_TABLE_LEN, L3_L2_SUB_TABLE_LEN); + if (ctx->l3_level != NULL) { if (aux_map_debug) fprintf(stderr, "AUX-MAP L3: 0x%"PRIx64", map=%p\n", - ctx->level3_base_addr, ctx->level3_map); + ctx->l3_level->address, ctx->l3_level->entries); p_atomic_inc(&ctx->state_num); return ctx; } else { @@ -404,27 +435,7 @@ intel_aux_map_get_base(struct intel_aux_map_context *ctx) * This get initialized in intel_aux_map_init, and never changes, so there is * no need to lock the mutex. */ - return ctx->level3_base_addr; -} - -static struct aux_map_buffer * -find_buffer(struct intel_aux_map_context *ctx, uint64_t addr) -{ - list_for_each_entry(struct aux_map_buffer, buf, &ctx->buffers, link) { - if (buf->buffer->gpu <= addr && buf->buffer->gpu_end > addr) { - return buf; - } - } - return NULL; -} - -static uint64_t * -get_u64_entry_ptr(struct intel_aux_map_context *ctx, uint64_t addr) -{ - struct aux_map_buffer *buf = find_buffer(ctx, addr); - assert(buf); - uintptr_t map_offset = addr - buf->buffer->gpu; - return (uint64_t*)((uint8_t*)buf->buffer->map + map_offset); + return ctx->l3_level->address; } static uint8_t @@ -511,52 +522,57 @@ get_l1_addr_mask(struct intel_aux_map_context *ctx) static void get_aux_entry(struct intel_aux_map_context *ctx, uint64_t main_address, uint32_t *l1_index_out, uint64_t *l1_entry_addr_out, - uint64_t **l1_entry_map_out) + uint64_t **l1_entry_map_out, + struct intel_aux_level **l1_aux_level_out) { + struct intel_aux_level *l3_level = ctx->l3_level; + struct intel_aux_level *l2_level; + struct intel_aux_level *l1_level; + uint32_t l3_index = (main_address >> 36) & 0xfff; - uint64_t *l3_entry = &ctx->level3_map[l3_index]; - uint64_t *l2_map; - if ((*l3_entry & INTEL_AUX_MAP_ENTRY_VALID_BIT) == 0) { - uint64_t l2_addr; - if (add_sub_table(ctx, L3_L2_SUB_TABLE_LEN, L3_L2_SUB_TABLE_LEN, - &l2_addr, &l2_map)) { + if (l3_level->children[l3_index] == NULL) { + l2_level = + add_sub_table(ctx, ctx->l3_level, l3_index, + L3_L2_SUB_TABLE_LEN, L3_L2_SUB_TABLE_LEN); + if (l2_level != NULL) { if (aux_map_debug) fprintf(stderr, "AUX-MAP L3[0x%x]: 0x%"PRIx64", map=%p\n", - l3_index, l2_addr, l2_map); + l3_index, l2_level->address, l2_level->entries); } else { unreachable("Failed to add L2 Aux-Map Page Table!"); } - *l3_entry = (l2_addr & L3_ENTRY_L2_ADDR_MASK) | INTEL_AUX_MAP_ENTRY_VALID_BIT; + l3_level->entries[l3_index] = (l2_level->address & L3_ENTRY_L2_ADDR_MASK) | + INTEL_AUX_MAP_ENTRY_VALID_BIT; } else { - uint64_t l2_addr = intel_canonical_address(*l3_entry & L3_ENTRY_L2_ADDR_MASK); - l2_map = get_u64_entry_ptr(ctx, l2_addr); + l2_level = l3_level->children[l3_index]; } uint32_t l2_index = (main_address >> 24) & 0xfff; - uint64_t *l2_entry = &l2_map[l2_index]; uint64_t l1_page_size = ctx->format->l1_page_size; - uint64_t l1_addr, *l1_map; - if ((*l2_entry & INTEL_AUX_MAP_ENTRY_VALID_BIT) == 0) { - if (add_sub_table(ctx, l1_page_size, l1_page_size, &l1_addr, &l1_map)) { + if (l2_level->children[l2_index] == NULL) { + l1_level = add_sub_table(ctx, l2_level, l2_index, l1_page_size, l1_page_size); + if (l1_level != NULL) { if (aux_map_debug) fprintf(stderr, "AUX-MAP L2[0x%x]: 0x%"PRIx64", map=%p\n", - l2_index, l1_addr, l1_map); + l2_index, l1_level->address, l1_level->entries); } else { unreachable("Failed to add L1 Aux-Map Page Table!"); } - *l2_entry = (l1_addr & get_l1_addr_mask(ctx)) | INTEL_AUX_MAP_ENTRY_VALID_BIT; + l2_level->entries[l2_index] = (l1_level->address & get_l1_addr_mask(ctx)) | + INTEL_AUX_MAP_ENTRY_VALID_BIT; } else { - l1_addr = intel_canonical_address(*l2_entry & get_l1_addr_mask(ctx)); - l1_map = get_u64_entry_ptr(ctx, l1_addr); + l1_level = l2_level->children[l2_index]; } uint32_t l1_index = get_index(main_address, ctx->format->l1_index_mask, - ctx->format->l1_index_offset); + ctx->format->l1_index_offset); if (l1_index_out) *l1_index_out = l1_index; if (l1_entry_addr_out) - *l1_entry_addr_out = intel_canonical_address(l1_addr + l1_index * sizeof(*l1_map)); + *l1_entry_addr_out = intel_canonical_address(l1_level->address + l1_index * sizeof(uint64_t)); if (l1_entry_map_out) - *l1_entry_map_out = &l1_map[l1_index]; + *l1_entry_map_out = &l1_level->entries[l1_index]; + if (l1_aux_level_out) + *l1_aux_level_out = l1_level; } static bool @@ -570,7 +586,8 @@ add_mapping(struct intel_aux_map_context *ctx, uint64_t main_address, uint32_t l1_index; uint64_t *l1_entry; - get_aux_entry(ctx, main_address, &l1_index, NULL, &l1_entry); + struct intel_aux_level *l1_aux_level; + get_aux_entry(ctx, main_address, &l1_index, NULL, &l1_entry, &l1_aux_level); const uint64_t l1_data = (aux_address & intel_aux_get_meta_address_mask(ctx)) | @@ -579,6 +596,7 @@ add_mapping(struct intel_aux_map_context *ctx, uint64_t main_address, const uint64_t current_l1_data = *l1_entry; if ((current_l1_data & INTEL_AUX_MAP_ENTRY_VALID_BIT) == 0) { + assert(l1_aux_level->ref_counts[l1_index] == 0); assert((aux_address & 0xffULL) == 0); if (aux_map_debug) fprintf(stderr, "AUX-MAP L1[0x%x] 0x%"PRIx64" -> 0x%"PRIx64"\n", @@ -608,6 +626,8 @@ add_mapping(struct intel_aux_map_context *ctx, uint64_t main_address, } } + l1_aux_level->ref_counts[l1_index]++; + return true; } @@ -618,12 +638,71 @@ intel_aux_map_get_entry(struct intel_aux_map_context *ctx, { pthread_mutex_lock(&ctx->mutex); uint64_t *l1_entry_map; - get_aux_entry(ctx, main_address, NULL, aux_entry_address, &l1_entry_map); + get_aux_entry(ctx, main_address, NULL, aux_entry_address, &l1_entry_map, NULL); pthread_mutex_unlock(&ctx->mutex); return l1_entry_map; } +/** + * We mark the leaf entry as invalid, but we don't attempt to cleanup the + * other levels of translation mappings. Since we attempt to re-use VMA + * ranges, hopefully this will not lead to unbounded growth of the translation + * tables. + */ +static void +remove_l1_mapping_locked(struct intel_aux_map_context *ctx, uint64_t main_address, + bool reset_refcount, bool *state_changed) +{ + uint32_t l1_index; + uint64_t *l1_entry; + struct intel_aux_level *l1_aux_level; + get_aux_entry(ctx, main_address, &l1_index, NULL, &l1_entry, &l1_aux_level); + + const uint64_t current_l1_data = *l1_entry; + const uint64_t l1_data = current_l1_data & ~INTEL_AUX_MAP_ENTRY_VALID_BIT; + + if ((current_l1_data & INTEL_AUX_MAP_ENTRY_VALID_BIT) == 0) { + assert(l1_aux_level->ref_counts[l1_index] == 0); + return; + } else if (reset_refcount) { + l1_aux_level->ref_counts[l1_index] = 0; + if (unlikely(l1_data == 0)) + *state_changed = true; + *l1_entry = l1_data; + } else { + assert(l1_aux_level->ref_counts[l1_index] > 0); + if (--l1_aux_level->ref_counts[l1_index] == 0) { + /** + * We use non-zero bits in 63:1 to indicate the entry had been filled + * previously. In the unlikely event that these are all zero, we + * force a flush of the aux-map tables. + */ + if (unlikely(l1_data == 0)) + *state_changed = true; + *l1_entry = l1_data; + } + } +} + +static void +remove_mapping_locked(struct intel_aux_map_context *ctx, uint64_t main_address, + uint64_t size, bool reset_refcount, bool *state_changed) +{ + if (aux_map_debug) + fprintf(stderr, "AUX-MAP remove 0x%"PRIx64"-0x%"PRIx64"\n", main_address, + main_address + size); + + uint64_t main_inc_addr = main_address; + uint64_t main_page_size = ctx->format->main_page_size; + assert((main_address & get_page_mask(main_page_size)) == 0); + while (main_inc_addr - main_address < size) { + remove_l1_mapping_locked(ctx, main_inc_addr, reset_refcount, + state_changed); + main_inc_addr += main_page_size; + } +} + bool intel_aux_map_add_mapping(struct intel_aux_map_context *ctx, uint64_t main_address, uint64_t aux_address, uint64_t main_size_B, @@ -645,41 +724,32 @@ intel_aux_map_add_mapping(struct intel_aux_map_context *ctx, uint64_t main_addre main_inc_addr = main_inc_addr + main_page_size; aux_inc_addr = aux_inc_addr + aux_page_size; } + bool success = main_inc_addr - main_address >= main_size_B; + if (!success && (main_inc_addr - main_address) > 0) { + /* If the mapping failed, remove the mapped portion. */ + remove_mapping_locked(ctx, main_address, + main_size_B - (main_inc_addr - main_address), + false /* reset_refcount */, &state_changed); + } pthread_mutex_unlock(&ctx->mutex); if (state_changed) p_atomic_inc(&ctx->state_num); - return main_inc_addr - main_address >= main_size_B; + + return success; } -/** - * We mark the leaf entry as invalid, but we don't attempt to cleanup the - * other levels of translation mappings. Since we attempt to re-use VMA - * ranges, hopefully this will not lead to unbounded growth of the translation - * tables. - */ -static void -remove_mapping(struct intel_aux_map_context *ctx, uint64_t main_address, - bool *state_changed) +void +intel_aux_map_del_mapping(struct intel_aux_map_context *ctx, uint64_t main_address, + uint64_t size) { - uint64_t *l1_entry; - get_aux_entry(ctx, main_address, NULL, NULL, &l1_entry); - - const uint64_t current_l1_data = *l1_entry; - const uint64_t l1_data = current_l1_data & ~INTEL_AUX_MAP_ENTRY_VALID_BIT; - - if ((current_l1_data & INTEL_AUX_MAP_ENTRY_VALID_BIT) == 0) { - return; - } else { - /** - * We use non-zero bits in 63:1 to indicate the entry had been filled - * previously. In the unlikely event that these are all zero, we force a - * flush of the aux-map tables. - */ - if (unlikely(l1_data == 0)) - *state_changed = true; - *l1_entry = l1_data; - } + bool state_changed = false; + pthread_mutex_lock(&ctx->mutex); + remove_mapping_locked(ctx, main_address, size, false /* reset_refcount */, + &state_changed); + pthread_mutex_unlock(&ctx->mutex); + if (state_changed) + p_atomic_inc(&ctx->state_num); } void @@ -688,17 +758,8 @@ intel_aux_map_unmap_range(struct intel_aux_map_context *ctx, uint64_t main_addre { bool state_changed = false; pthread_mutex_lock(&ctx->mutex); - if (aux_map_debug) - fprintf(stderr, "AUX-MAP remove 0x%"PRIx64"-0x%"PRIx64"\n", main_address, - main_address + size); - - uint64_t main_inc_addr = main_address; - uint64_t main_page_size = ctx->format->main_page_size; - assert((main_address & get_page_mask(main_page_size)) == 0); - while (main_inc_addr - main_address < size) { - remove_mapping(ctx, main_inc_addr, &state_changed); - main_inc_addr += main_page_size; - } + remove_mapping_locked(ctx, main_address, size, true /* reset_refcount */, + &state_changed); pthread_mutex_unlock(&ctx->mutex); if (state_changed) p_atomic_inc(&ctx->state_num); diff --git a/src/intel/common/intel_aux_map.h b/src/intel/common/intel_aux_map.h index 7593cdd4705..d1a996199a2 100644 --- a/src/intel/common/intel_aux_map.h +++ b/src/intel/common/intel_aux_map.h @@ -110,12 +110,23 @@ intel_aux_map_get_entry(struct intel_aux_map_context *ctx, uint64_t *aux_entry_address); /* Fails if a mapping is attempted that would conflict with an existing one. + * This increase the refcount of the mapped region if already mapped, sets it + * to 1 otherwise. */ bool intel_aux_map_add_mapping(struct intel_aux_map_context *ctx, uint64_t main_address, uint64_t aux_address, uint64_t main_size_B, uint64_t format_bits); +/* Decrease the refcount of a mapped region. When the refcount reaches 0, the + * region is unmapped. + */ +void +intel_aux_map_del_mapping(struct intel_aux_map_context *ctx, uint64_t main_address, + uint64_t size); + +/* Unmaps a region, refcount is reset to 0. + */ void intel_aux_map_unmap_range(struct intel_aux_map_context *ctx, uint64_t main_address, uint64_t size); diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h index b01c221af76..0d4b93ed968 100644 --- a/src/intel/compiler/brw_eu_defines.h +++ b/src/intel/compiler/brw_eu_defines.h @@ -986,6 +986,17 @@ enum urb_logical_srcs { URB_LOGICAL_NUM_SRCS }; +enum interpolator_logical_srcs { + /** Interpolation offset */ + INTERP_SRC_OFFSET, + /** Message data */ + INTERP_SRC_MSG_DESC, + /** Flag register for dynamic mode */ + INTERP_SRC_DYNAMIC_MODE, + + INTERP_NUM_SRCS +}; + #ifdef __cplusplus /** diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index db67b332576..e6a603a9048 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -2788,6 +2788,29 @@ fs_visitor::opt_algebraic() if (brw_reg_type_is_floating_point(inst->src[1].type)) break; + /* From the BDW PRM, Vol 2a, "mul - Multiply": + * + * "When multiplying integer datatypes, if src0 is DW and src1 + * is W, irrespective of the destination datatype, the + * accumulator maintains full 48-bit precision." + * ... + * "When multiplying integer data types, if one of the sources + * is a DW, the resulting full precision data is stored in + * the accumulator." + * + * There are also similar notes in earlier PRMs. + * + * The MOV instruction can copy the bits of the source, but it + * does not clear the higher bits of the accumulator. So, because + * we might use the full accumulator in the MUL/MACH macro, we + * shouldn't replace such MULs with MOVs. + */ + if ((brw_reg_type_to_size(inst->src[0].type) == 4 || + brw_reg_type_to_size(inst->src[1].type) == 4) && + (inst->dst.is_accumulator() || + inst->writes_accumulator_implicitly(devinfo))) + break; + /* a * 1.0 = a */ if (inst->src[1].is_one()) { inst->opcode = BRW_OPCODE_MOV; @@ -6811,7 +6834,7 @@ save_instruction_order(const struct cfg_t *cfg) static void restore_instruction_order(struct cfg_t *cfg, fs_inst **inst_arr) { - int num_insts = cfg->last_block()->end_ip + 1; + ASSERTED int num_insts = cfg->last_block()->end_ip + 1; int ip = 0; foreach_block (block, cfg) { @@ -7576,7 +7599,17 @@ computed_depth_mode(const nir_shader *shader) case FRAG_DEPTH_LAYOUT_LESS: return BRW_PSCDEPTH_ON_LE; case FRAG_DEPTH_LAYOUT_UNCHANGED: - return BRW_PSCDEPTH_OFF; + /* We initially set this to OFF, but having the shader write the + * depth means we allocate register space in the SEND message. The + * difference between the SEND register count and the OFF state + * programming makes the HW hang. + * + * Removing the depth writes also leads to test failures. So use + * LesserThanOrEqual, which fits writing the same value + * (unchanged/equal). + * + */ + return BRW_PSCDEPTH_ON_LE; } } return BRW_PSCDEPTH_OFF; diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 34df9a8f436..9bb62ec7401 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -361,6 +361,17 @@ fs_visitor::nir_emit_if(nir_if *if_stmt) invert = true; cond_reg = get_nir_src(cond->src[0].src); cond_reg = offset(cond_reg, bld, cond->src[0].swizzle[0]); + + if (devinfo->ver <= 5 && + (cond->instr.pass_flags & BRW_NIR_BOOLEAN_MASK) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE) { + /* redo boolean resolve on gen5 */ + fs_reg masked = bld.vgrf(BRW_REGISTER_TYPE_D); + bld.AND(masked, cond_reg, brw_imm_d(1)); + masked.negate = true; + fs_reg tmp = bld.vgrf(cond_reg.type); + bld.MOV(retype(tmp, BRW_REGISTER_TYPE_D), masked); + cond_reg = tmp; + } } else { invert = false; cond_reg = get_nir_src(if_stmt->condition); @@ -2092,12 +2103,18 @@ emit_pixel_interpolater_send(const fs_builder &bld, const fs_reg &dst, const fs_reg &src, const fs_reg &desc, + const fs_reg &flag_reg, glsl_interp_mode interpolation) { struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(bld.shader->stage_prog_data); - fs_inst *inst = bld.emit(opcode, dst, src, desc); + fs_reg srcs[INTERP_NUM_SRCS]; + srcs[INTERP_SRC_OFFSET] = src; + srcs[INTERP_SRC_MSG_DESC] = desc; + srcs[INTERP_SRC_DYNAMIC_MODE] = flag_reg; + + fs_inst *inst = bld.emit(opcode, dst, srcs, INTERP_NUM_SRCS); /* 2 floats per slot returned */ inst->size_written = 2 * dst.component_size(inst->exec_size); if (interpolation == INTERP_MODE_NOPERSPECTIVE) { @@ -3578,11 +3595,23 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder &bld, bld.exec_all().group(1, 0).SHL(msg_data, sample_id, brw_imm_ud(4u)); } + fs_reg flag_reg; + struct brw_wm_prog_key *wm_prog_key = (struct brw_wm_prog_key *) key; + if (wm_prog_key->multisample_fbo == BRW_SOMETIMES) { + struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(prog_data); + + check_dynamic_msaa_flag(bld.exec_all().group(8, 0), + wm_prog_data, + BRW_WM_MSAA_FLAG_MULTISAMPLE_FBO); + flag_reg = brw_flag_reg(0, 0); + } + emit_pixel_interpolater_send(bld, FS_OPCODE_INTERPOLATE_AT_SAMPLE, dest, fs_reg(), /* src */ msg_data, + flag_reg, interpolation); break; } @@ -3603,6 +3632,7 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder &bld, dest, fs_reg(), /* src */ brw_imm_ud(off_x | (off_y << 4)), + fs_reg(), /* flag_reg */ interpolation); } else { fs_reg src = retype(get_nir_src(instr->src[0]), BRW_REGISTER_TYPE_D); @@ -3612,6 +3642,7 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder &bld, dest, src, brw_imm_ud(0u), + fs_reg(), /* flag_reg */ interpolation); } break; @@ -6380,16 +6411,17 @@ fs_visitor::nir_emit_global_atomic(const fs_builder &bld, nir_intrinsic_instr *instr) { int op = lsc_aop_for_nir_intrinsic(instr); + int num_data = lsc_op_num_data_values(op); fs_reg dest = get_nir_def(instr->def); fs_reg addr = get_nir_src(instr->src[0]); fs_reg data; - if (op != LSC_OP_ATOMIC_INC && op != LSC_OP_ATOMIC_DEC) + if (num_data >= 1) data = expand_to_32bit(bld, get_nir_src(instr->src[1])); - if (op == LSC_OP_ATOMIC_CMPXCHG) { + if (num_data >= 2) { fs_reg tmp = bld.vgrf(data.type, 2); fs_reg sources[2] = { data, diff --git a/src/intel/compiler/brw_lower_logical_sends.cpp b/src/intel/compiler/brw_lower_logical_sends.cpp index c055da7e8bc..40daed39da2 100644 --- a/src/intel/compiler/brw_lower_logical_sends.cpp +++ b/src/intel/compiler/brw_lower_logical_sends.cpp @@ -2715,6 +2715,7 @@ lower_math_logical_send(const fs_builder &bld, fs_inst *inst) static void lower_interpolator_logical_send(const fs_builder &bld, fs_inst *inst, + const struct brw_wm_prog_key *wm_prog_key, const struct brw_wm_prog_data *wm_prog_data) { const intel_device_info *devinfo = bld.shader->devinfo; @@ -2726,17 +2727,17 @@ lower_interpolator_logical_send(const fs_builder &bld, fs_inst *inst, unsigned mode; switch (inst->opcode) { case FS_OPCODE_INTERPOLATE_AT_SAMPLE: - assert(inst->src[0].file == BAD_FILE); + assert(inst->src[INTERP_SRC_OFFSET].file == BAD_FILE); mode = GFX7_PIXEL_INTERPOLATOR_LOC_SAMPLE; break; case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: - assert(inst->src[0].file == BAD_FILE); + assert(inst->src[INTERP_SRC_OFFSET].file == BAD_FILE); mode = GFX7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET; break; case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: - payload = inst->src[0]; + payload = inst->src[INTERP_SRC_OFFSET]; mlen = 2 * inst->exec_size / 8; mode = GFX7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET; break; @@ -2746,10 +2747,9 @@ lower_interpolator_logical_send(const fs_builder &bld, fs_inst *inst, } const bool dynamic_mode = - inst->opcode == FS_OPCODE_INTERPOLATE_AT_SAMPLE && - wm_prog_data->persample_dispatch == BRW_SOMETIMES; + inst->src[INTERP_SRC_DYNAMIC_MODE].file != BAD_FILE; - fs_reg desc = inst->src[1]; + fs_reg desc = inst->src[INTERP_SRC_MSG_DESC]; uint32_t desc_imm = brw_pixel_interp_desc(devinfo, /* Leave the mode at 0 if persample_dispatch is @@ -2798,8 +2798,10 @@ lower_interpolator_logical_send(const fs_builder &bld, fs_inst *inst, const fs_builder &ubld = bld.exec_all().group(8, 0); desc = ubld.vgrf(BRW_REGISTER_TYPE_UD); - check_dynamic_msaa_flag(ubld, wm_prog_data, - BRW_WM_MSAA_FLAG_PERSAMPLE_DISPATCH); + /* The predicate should have been built in brw_fs_nir.cpp when emitting + * NIR code. This guarantees that we do not have incorrect interactions + * with the flag register holding the predication result. + */ if (orig_desc.file == IMM) { /* Not using SEL here because we would generate an instruction with 2 * immediate sources which is not supported by HW. @@ -3185,6 +3187,7 @@ fs_visitor::lower_logical_sends() case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: lower_interpolator_logical_send(ibld, inst, + (const brw_wm_prog_key *)key, brw_wm_prog_data(prog_data)); break; diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 3ef61403616..c36269fd015 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -1734,6 +1734,13 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler, nir_validate_ssa_dominance(nir, "before nir_convert_from_ssa"); + /* Rerun the divergence analysis before convert_from_ssa as this pass has + * some assert on consistent divergence flags. + */ + NIR_PASS(_, nir, nir_convert_to_lcssa, true, true); + NIR_PASS_V(nir, nir_divergence_analysis); + OPT(nir_opt_remove_phis); + OPT(nir_convert_from_ssa, true); if (!is_scalar) { @@ -1746,14 +1753,6 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler, if (OPT(nir_opt_rematerialize_compares)) OPT(nir_opt_dce); - /* This is the last pass we run before we start emitting stuff. It - * determines when we need to insert boolean resolves on Gen <= 5. We - * run it last because it stashes data in instr->pass_flags and we don't - * want that to be squashed by other NIR passes. - */ - if (devinfo->ver <= 5) - brw_nir_analyze_boolean_resolves(nir); - OPT(nir_opt_dce); /* The mesh stages require this pass to be called at the last minute, @@ -1766,6 +1765,15 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler, brw_nir_adjust_payload(nir, compiler); nir_trivialize_registers(nir); + + /* This is the last pass we run before we start emitting stuff. It + * determines when we need to insert boolean resolves on Gen <= 5. We + * run it last because it stashes data in instr->pass_flags and we don't + * want that to be squashed by other NIR passes. + */ + if (devinfo->ver <= 5) + brw_nir_analyze_boolean_resolves(nir); + nir_sweep(nir); if (unlikely(debug_enabled)) { diff --git a/src/intel/compiler/brw_nir_lower_intersection_shader.c b/src/intel/compiler/brw_nir_lower_intersection_shader.c index 90e2f03684a..b26339bdac1 100644 --- a/src/intel/compiler/brw_nir_lower_intersection_shader.c +++ b/src/intel/compiler/brw_nir_lower_intersection_shader.c @@ -196,7 +196,14 @@ brw_nir_lower_intersection_shader(nir_shader *intersection, nir_def *hit_t = intrin->src[0].ssa; nir_def *hit_kind = intrin->src[1].ssa; nir_def *min_t = nir_load_ray_t_min(b); - nir_def *max_t = nir_load_global(b, t_addr, 4, 1, 32); + + struct brw_nir_rt_mem_ray_defs ray_def; + brw_nir_rt_load_mem_ray(b, &ray_def, BRW_RT_BVH_LEVEL_WORLD); + + struct brw_nir_rt_mem_hit_defs hit_in = {}; + brw_nir_rt_load_mem_hit(b, &hit_in, false); + + nir_def *max_t = ray_def.t_far; /* bool commit_tmp = false; */ nir_variable *commit_tmp = @@ -227,8 +234,13 @@ brw_nir_lower_intersection_shader(nir_shader *intersection, nir_push_if(b, nir_load_var(b, commit_tmp)); { nir_store_var(b, commit, nir_imm_true(b), 0x1); + + nir_def *ray_addr = + brw_nir_rt_mem_ray_addr(b, brw_nir_rt_stack_addr(b), BRW_RT_BVH_LEVEL_WORLD); + + nir_store_global(b, nir_iadd_imm(b, ray_addr, 16 + 12), 4, hit_t, 0x1); nir_store_global(b, t_addr, 4, - nir_vec2(b, hit_t, hit_kind), + nir_vec2(b, nir_fmin(b, hit_t, hit_in.t), hit_kind), 0x3); } nir_pop_if(b, NULL); diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index d96879c6f00..cddf55229b5 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -2548,19 +2548,42 @@ isl_calc_base_alignment(const struct isl_device *dev, if (tile_info->tiling == ISL_TILING_GFX12_CCS) base_alignment_B = MAX(base_alignment_B, 4096); - /* Platforms using an aux map require that images be granularity-aligned - * if they're going to used with CCS. This is because the Aux - * translation table maps main surface addresses to aux addresses at a - * granularity in the main surface. Because we don't know for sure in - * ISL if a surface will use CCS, we have to guess based on the - * DISABLE_AUX usage bit. The one thing we do know is that we haven't - * enable CCS on linear images yet so we can avoid the extra alignment - * there. - */ if (dev->info->has_aux_map && !(info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)) { + /* Wa_22015614752: + * + * Due to L3 cache being tagged with (engineID, vaID) and the CCS + * block/cacheline being 256 bytes, 2 engines accessing a 64Kb range + * with compression will generate 2 different CCS cacheline entries + * in L3, this will lead to corruptions. To avoid this, we need to + * ensure 2 images do not share a 256 bytes CCS cacheline. With a + * ratio of compression of 1/256, this is 64Kb alignment (even for + * Tile4...) + * + * ATS-M PRMS, Vol 2a: Command Reference: Instructions, + * XY_CTRL_SURF_COPY_BLT, "Size of Control Surface Copy" field, the + * CCS blocks are 256 bytes : + * + * "This field indicates size of the Control Surface or CCS copy. + * It is expressed in terms of number of 256B block of CCS, where + * each 256B block of CCS corresponds to 64KB of main surface." + */ + if (intel_needs_workaround(dev->info, 22015614752)) { + base_alignment_B = MAX(base_alignment_B, + 256 /* cacheline */ * 256 /* AUX ratio */); + } + + /* Platforms using an aux map require that images be + * granularity-aligned if they're going to used with CCS. This is + * because the Aux translation table maps main surface addresses to + * aux addresses at a granularity in the main surface. Because we + * don't know for sure in ISL if a surface will use CCS, we have to + * guess based on the DISABLE_AUX usage bit. The one thing we do know + * is that we haven't enable CCS on linear images yet so we can avoid + * the extra alignment there. + */ base_alignment_B = MAX(base_alignment_B, dev->info->verx10 >= 125 ? - 1024 * 1024 : 64 * 1024); + 1024 * 1024 : 64 * 1024); } } @@ -2774,6 +2797,13 @@ isl_surf_get_mcs_surf(const struct isl_device *dev, if (intel_device_info_is_dg2(dev->info)) return false; + /* On Gfx12+ this format is not listed in TGL PRMs, Volume 2b: Command + * Reference: Enumerations, RenderCompressionFormat + */ + if (ISL_GFX_VER(dev) >= 12 && + surf->format == ISL_FORMAT_R9G9B9E5_SHAREDEXP) + return false; + /* The following are true of all multisampled surfaces */ assert(surf->samples > 1); assert(surf->dim == ISL_SURF_DIM_2D); diff --git a/src/intel/perf/gen_perf.py b/src/intel/perf/gen_perf.py index 4a8b78f4373..1210cde214b 100644 --- a/src/intel/perf/gen_perf.py +++ b/src/intel/perf/gen_perf.py @@ -251,10 +251,10 @@ def splice_equal(args): def resolve_variable(name, set, allow_counters): if name in hw_vars: return hw_vars[name] - m = re.search('\$GtSlice([0-9]+)$', name) + m = re.search(r'\$GtSlice([0-9]+)$', name) if m: return 'intel_device_info_slice_available(&perf->devinfo, {0})'.format(m.group(1)) - m = re.search('\$GtSlice([0-9]+)XeCore([0-9]+)$', name) + m = re.search(r'\$GtSlice([0-9]+)XeCore([0-9]+)$', name) if m: return 'intel_device_info_subslice_available(&perf->devinfo, {0}, {1})'.format(m.group(1), m.group(2)) if allow_counters and name in set.counter_vars: diff --git a/src/intel/perf/intel_perf.c b/src/intel/perf/intel_perf.c index 52f4d989e7a..a047525b375 100644 --- a/src/intel/perf/intel_perf.c +++ b/src/intel/perf/intel_perf.c @@ -280,18 +280,19 @@ i915_query_perf_config_data(struct intel_perf_config *perf, { char data[sizeof(struct drm_i915_query_perf_config) + sizeof(struct drm_i915_perf_oa_config)] = {}; - struct drm_i915_query_perf_config *query = (void *)data; + struct drm_i915_query_perf_config *i915_query = (void *)data; + struct drm_i915_perf_oa_config *i915_config = (void *)data + sizeof(*i915_query); - memcpy(query->uuid, guid, sizeof(query->uuid)); - memcpy(query->data, config, sizeof(*config)); + memcpy(i915_query->uuid, guid, sizeof(i915_query->uuid)); + memcpy(i915_config, config, sizeof(*config)); int32_t item_length = sizeof(data); if (intel_i915_query_flags(fd, DRM_I915_QUERY_PERF_CONFIG, DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID, - query, &item_length)) + i915_query, &item_length)) return false; - memcpy(config, query->data, sizeof(*config)); + memcpy(config, i915_config, sizeof(*config)); return true; } diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c index 56073b42899..f527aa8d036 100644 --- a/src/intel/vulkan/anv_allocator.c +++ b/src/intel/vulkan/anv_allocator.c @@ -1646,6 +1646,7 @@ anv_device_import_bo(struct anv_device *device, assert(!(alloc_flags & (ANV_BO_ALLOC_MAPPED | ANV_BO_ALLOC_SNOOPED | ANV_BO_ALLOC_FIXED_ADDRESS))); + assert(alloc_flags & ANV_BO_ALLOC_EXTERNAL); struct anv_bo_cache *cache = &device->bo_cache; diff --git a/src/intel/vulkan/anv_android.c b/src/intel/vulkan/anv_android.c index 9dd3114f621..2cea3fc9f36 100644 --- a/src/intel/vulkan/anv_android.c +++ b/src/intel/vulkan/anv_android.c @@ -348,6 +348,7 @@ anv_image_init_from_gralloc(struct anv_device *device, * */ result = anv_device_import_bo(device, dma_buf, + ANV_BO_ALLOC_EXTERNAL | ANV_BO_ALLOC_IMPLICIT_SYNC | ANV_BO_ALLOC_IMPLICIT_WRITE, 0 /* client_address */, @@ -431,6 +432,7 @@ anv_image_bind_from_gralloc(struct anv_device *device, */ struct anv_bo *bo = NULL; VkResult result = anv_device_import_bo(device, dma_buf, + ANV_BO_ALLOC_EXTERNAL | ANV_BO_ALLOC_IMPLICIT_SYNC | ANV_BO_ALLOC_IMPLICIT_WRITE, 0 /* client_address */, diff --git a/src/intel/vulkan/anv_batch_chain.c b/src/intel/vulkan/anv_batch_chain.c index eb39ae6e85b..433cf00e5ef 100644 --- a/src/intel/vulkan/anv_batch_chain.c +++ b/src/intel/vulkan/anv_batch_chain.c @@ -1016,27 +1016,9 @@ anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer) const uint32_t length = cmd_buffer->batch.next - cmd_buffer->batch.start; if (cmd_buffer->device->physical->use_call_secondary) { cmd_buffer->exec_mode = ANV_CMD_BUFFER_EXEC_MODE_CALL_AND_RETURN; - /* If the secondary command buffer begins & ends in the same BO and - * its length is less than the length of CS prefetch, add some NOOPs - * instructions so the last MI_BATCH_BUFFER_START is outside the CS - * prefetch. - */ - if (cmd_buffer->batch_bos.next == cmd_buffer->batch_bos.prev) { - const enum intel_engine_class engine_class = cmd_buffer->queue_family->engine_class; - /* Careful to have everything in signed integer. */ - int32_t prefetch_len = devinfo->engine_class_prefetch[engine_class]; - int32_t batch_len = cmd_buffer->batch.next - cmd_buffer->batch.start; - - for (int32_t i = 0; i < (prefetch_len - batch_len); i += 4) - anv_batch_emit(&cmd_buffer->batch, GFX9_MI_NOOP, noop); - } void *jump_addr = - anv_batch_emitn(&cmd_buffer->batch, - GFX9_MI_BATCH_BUFFER_START_length, - GFX9_MI_BATCH_BUFFER_START, - .AddressSpaceIndicator = ASI_PPGTT, - .SecondLevelBatchBuffer = Firstlevelbatch) + + anv_genX(devinfo, batch_emit_return)(&cmd_buffer->batch) + (GFX9_MI_BATCH_BUFFER_START_BatchBufferStartAddress_start / 8); cmd_buffer->return_addr = anv_batch_address(&cmd_buffer->batch, jump_addr); @@ -1156,18 +1138,10 @@ anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary, struct anv_batch_bo *first_bbo = list_first_entry(&secondary->batch_bos, struct anv_batch_bo, link); - uint64_t *write_return_addr = - anv_batch_emitn(&primary->batch, - GFX9_MI_STORE_DATA_IMM_length + 1 /* QWord write */, - GFX9_MI_STORE_DATA_IMM, - .Address = secondary->return_addr) - + (GFX9_MI_STORE_DATA_IMM_ImmediateData_start / 8); - - emit_batch_buffer_start(&primary->batch, first_bbo->bo, 0); - - *write_return_addr = - anv_address_physical(anv_batch_address(&primary->batch, - primary->batch.next)); + anv_genX(primary->device->info, batch_emit_secondary_call)( + &primary->batch, + (struct anv_address) { .bo = first_bbo->bo }, + secondary->return_addr); anv_cmd_buffer_add_seen_bbos(primary, &secondary->batch_bos); break; diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c index 796eb8c484d..f3bea7cdcb4 100644 --- a/src/intel/vulkan/anv_blorp.c +++ b/src/intel/vulkan/anv_blorp.c @@ -1788,11 +1788,18 @@ anv_fast_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer, * * Set CS stall bit to guarantee that the fast clear starts the execution * after the tile cache flush completed. + * + * There is no Bspec requirement to flush the data cache but the + * experiment shows that flusing the data cache helps to resolve the + * corruption. */ + unsigned wa_flush = intel_device_info_is_dg2(cmd_buffer->device->info) ? + ANV_PIPE_DATA_CACHE_FLUSH_BIT : 0; anv_add_pending_pipe_bits(cmd_buffer, ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT | - ANV_PIPE_TILE_CACHE_FLUSH_BIT, + ANV_PIPE_TILE_CACHE_FLUSH_BIT | + wa_flush, "before clear hiz_ccs_wt"); } diff --git a/src/intel/vulkan/anv_descriptor_set.c b/src/intel/vulkan/anv_descriptor_set.c index 0d335b806f3..123894dfa43 100644 --- a/src/intel/vulkan/anv_descriptor_set.c +++ b/src/intel/vulkan/anv_descriptor_set.c @@ -280,7 +280,9 @@ anv_descriptor_size_for_mutable_type(const struct anv_physical_device *device, { unsigned size = 0; - if (!mutable_info || mutable_info->mutableDescriptorTypeListCount == 0) { + if (!mutable_info || + mutable_info->mutableDescriptorTypeListCount == 0 || + binding >= mutable_info->mutableDescriptorTypeListCount) { for(VkDescriptorType i = 0; i <= VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT; i++) { if (i == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC || diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 055f9a79fbb..4ca87819276 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -77,7 +77,8 @@ static const driOptionDescription anv_dri_options[] = { DRI_CONF_VK_X11_STRICT_IMAGE_COUNT(false) DRI_CONF_VK_KHR_PRESENT_WAIT(false) DRI_CONF_VK_XWAYLAND_WAIT_READY(true) - DRI_CONF_ANV_ASSUME_FULL_SUBGROUPS(false) + DRI_CONF_ANV_ASSUME_FULL_SUBGROUPS(0) + DRI_CONF_ANV_DISABLE_FCV(false) DRI_CONF_ANV_SAMPLE_MASK_OUT_OPENGL_BEHAVIOUR(false) DRI_CONF_ANV_FP64_WORKAROUND_ENABLED(false) DRI_CONF_ANV_GENERATED_INDIRECT_THRESHOLD(4) @@ -879,11 +880,6 @@ anv_compute_sys_heap_size(struct anv_physical_device *device, else available_ram = total_ram * 3 / 4; - /* We also want to leave some padding for things we allocate in the driver, - * so don't go over 3/4 of the GTT either. - */ - available_ram = MIN2(available_ram, device->gtt_size * 3 / 4); - return available_ram; } @@ -1220,7 +1216,7 @@ anv_physical_device_init_queue_families(struct anv_physical_device *pdevice) /* Increase count below when other families are added as a reminder to * increase the ANV_MAX_QUEUE_FAMILIES value. */ - STATIC_ASSERT(ANV_MAX_QUEUE_FAMILIES >= 4); + STATIC_ASSERT(ANV_MAX_QUEUE_FAMILIES >= 5); } else { /* Default to a single render queue */ pdevice->queue.families[family_count++] = (struct anv_queue_family) { @@ -1366,6 +1362,8 @@ anv_physical_device_try_create(struct vk_instance *vk_instance, device->flush_astc_ldr_void_extent_denorms = device->has_astc_ldr && !device->emu_astc_ldr; } + device->disable_fcv = intel_device_info_is_mtl(&device->info) || + instance->disable_fcv; result = anv_physical_device_init_heaps(device, fd); if (result != VK_SUCCESS) @@ -1582,7 +1580,7 @@ anv_init_dri_options(struct anv_instance *instance) instance->vk.app_info.engine_version); instance->assume_full_subgroups = - driQueryOptionb(&instance->dri_options, "anv_assume_full_subgroups"); + driQueryOptioni(&instance->dri_options, "anv_assume_full_subgroups"); instance->limit_trig_input_range = driQueryOptionb(&instance->dri_options, "limit_trig_input_range"); instance->sample_mask_out_opengl_behaviour = @@ -1609,6 +1607,8 @@ anv_init_dri_options(struct anv_instance *instance) driQueryOptioni(&instance->dri_options, "force_vk_vendor"); instance->has_fake_sparse = driQueryOptionb(&instance->dri_options, "fake_sparse"); + instance->disable_fcv = + driQueryOptionb(&instance->dri_options, "anv_disable_fcv"); } VkResult anv_CreateInstance( @@ -2760,7 +2760,7 @@ anv_get_memory_budget(VkPhysicalDevice physicalDevice, } } else { total_heaps_size = total_sys_heaps_size; - mem_available = device->sys.available; + mem_available = MIN2(device->sys.available, total_heaps_size); } double heap_proportion = (double) heap_size / total_heaps_size; diff --git a/src/intel/vulkan/anv_genX.h b/src/intel/vulkan/anv_genX.h index 7799f1780eb..f59c98472f8 100644 --- a/src/intel/vulkan/anv_genX.h +++ b/src/intel/vulkan/anv_genX.h @@ -173,6 +173,12 @@ void genX(cmd_buffer_dispatch_kernel)(struct anv_cmd_buffer *cmd_buffer, void genX(blorp_exec)(struct blorp_batch *batch, const struct blorp_params *params); +void genX(batch_emit_secondary_call)(struct anv_batch *batch, + struct anv_address secondary_addr, + struct anv_address secondary_return_addr); + +void *genX(batch_emit_return)(struct anv_batch *batch); + void genX(cmd_emit_timestamp)(struct anv_batch *batch, struct anv_device *device, struct anv_address addr, diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c index 6ffe7cbd5c0..aecb2975ebe 100644 --- a/src/intel/vulkan/anv_image.c +++ b/src/intel/vulkan/anv_image.c @@ -830,7 +830,8 @@ add_aux_surface_if_supported(struct anv_device *device, if (intel_needs_workaround(device->info, 1607794140)) { /* FCV is permanently enabled on this HW. */ image->planes[plane].aux_usage = ISL_AUX_USAGE_FCV_CCS_E; - } else if (intel_device_info_is_dg2(device->info)) { + } else if (device->info->verx10 >= 125 && + !device->physical->disable_fcv) { /* FCV is enabled via 3DSTATE_3D_MODE. We'd expect plain CCS_E to * perform better because it allows for non-zero fast clear colors, * but we've run into regressions in several benchmarks (F1 22 and @@ -1703,6 +1704,25 @@ anv_image_finish(struct anv_image *image) if (anv_image_is_sparse(image)) anv_image_finish_sparse_bindings(image); + /* Unmap a CCS so that if the bound region of the image is rebound to + * another image, the AUX tables will be cleared to allow for a new + * mapping. + */ + for (int p = 0; p < image->n_planes; ++p) { + if (!image->planes[p].aux_ccs_mapped) + continue; + + const struct anv_address main_addr = + anv_image_address(image, + &image->planes[p].primary_surface.memory_range); + const struct isl_surf *surf = + &image->planes[p].primary_surface.isl; + + intel_aux_map_del_mapping(device->aux_map_ctx, + anv_address_physical(main_addr), + surf->size_B); + } + if (image->from_gralloc) { assert(!image->disjoint); assert(image->n_planes == 1); @@ -1899,32 +1919,17 @@ anv_image_get_memory_requirements(struct anv_device *device, switch (ext->sType) { case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: { VkMemoryDedicatedRequirements *requirements = (void *)ext; - if (image->vk.wsi_legacy_scanout || image->from_ahb) { - /* If we need to set the tiling for external consumers, we need a - * dedicated allocation. + if (image->vk.wsi_legacy_scanout || + image->from_ahb || + (isl_drm_modifier_has_aux(image->vk.drm_format_mod) && + anv_image_uses_aux_map(device, image))) { + /* If we need to set the tiling for external consumers or the + * modifier involves AUX tables, we need a dedicated allocation. * * See also anv_AllocateMemory. */ requirements->prefersDedicatedAllocation = true; requirements->requiresDedicatedAllocation = true; - } else if (anv_image_uses_aux_map(device, image)) { - /* We request a dedicated allocation to guarantee that the BO will - * be aux-map compatible (see anv_bo_vma_alloc_or_close and - * anv_bo_allows_aux_map). - * - * TODO: This is an untested heuristic. It's not known if this - * guarantee is worth losing suballocation. - * - * If we don't have an aux-map compatible BO at the time we bind - * this image to device memory, we'll change the aux usage. - * - * It may be possible to handle an image using a modifier in the - * same way. However, we choose to keep things simple and require - * a dedicated allocation for that case. - */ - requirements->prefersDedicatedAllocation = true; - requirements->requiresDedicatedAllocation = - isl_drm_modifier_has_aux(image->vk.drm_format_mod); } else { requirements->prefersDedicatedAllocation = false; requirements->requiresDedicatedAllocation = false; @@ -2296,15 +2301,20 @@ VkResult anv_BindImageMemory2( if (!bo || !isl_aux_usage_has_ccs(image->planes[p].aux_usage)) continue; - /* Do nothing if flat CCS requirements are satisfied. */ - if (device->info->has_flat_ccs && bo->vram_only) + /* Do nothing if flat CCS requirements are satisfied. + * + * Also, assume that imported BOs with a modifier including + * CCS live only in local memory. Otherwise the exporter should + * have failed the creation of the BO. + */ + if (device->info->has_flat_ccs && + (bo->vram_only || bo->is_external)) continue; /* Add the plane to the aux map when applicable. */ - if (anv_bo_allows_aux_map(device, bo)) { - const struct anv_address main_addr = - anv_image_address(image, - &image->planes[p].primary_surface.memory_range); + const struct anv_address main_addr = anv_image_address( + image, &image->planes[p].primary_surface.memory_range); + if (anv_address_allows_aux_map(device, main_addr)) { const struct anv_address aux_addr = anv_image_address(image, &image->planes[p].compr_ctrl_memory_range); @@ -2312,12 +2322,12 @@ VkResult anv_BindImageMemory2( &image->planes[p].primary_surface.isl; const uint64_t format_bits = intel_aux_map_format_bits_for_isl_surf(surf); - const bool mapped = + image->planes[p].aux_ccs_mapped = intel_aux_map_add_mapping(device->aux_map_ctx, anv_address_physical(main_addr), anv_address_physical(aux_addr), surf->size_B, format_bits); - if (mapped) + if (image->planes[p].aux_ccs_mapped) continue; } diff --git a/src/intel/vulkan/anv_internal_kernels.c b/src/intel/vulkan/anv_internal_kernels.c index 184d757fb36..077d7ebe177 100644 --- a/src/intel/vulkan/anv_internal_kernels.c +++ b/src/intel/vulkan/anv_internal_kernels.c @@ -245,6 +245,8 @@ compile_upload_spirv(struct anv_device *device, brw_nir_analyze_ubo_ranges(compiler, nir, NULL, prog_data.base.ubo_ranges); + void *temp_ctx = ralloc_context(NULL); + const unsigned *program; if (stage == MESA_SHADER_FRAGMENT) { struct brw_compile_stats stats[3]; @@ -254,6 +256,7 @@ compile_upload_spirv(struct anv_device *device, .log_data = device, .debug_flag = DEBUG_WM, .stats = stats, + .mem_ctx = temp_ctx, }, .key = &key.wm, .prog_data = &prog_data.wm, @@ -287,6 +290,7 @@ compile_upload_spirv(struct anv_device *device, .stats = &stats, .log_data = device, .debug_flag = DEBUG_CS, + .mem_ctx = temp_ctx, }, .key = &key.cs, .prog_data = &prog_data.cs, @@ -314,6 +318,7 @@ compile_upload_spirv(struct anv_device *device, &push_desc_info, 0 /* dynamic_push_values */); + ralloc_free(temp_ctx); ralloc_free(nir); return kernel; diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 52f97aec312..e7f0d873e9b 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -771,7 +771,7 @@ anv_pipeline_hash_graphics(struct anv_graphics_base_pipeline *pipeline, } if (stages[MESA_SHADER_MESH].info || stages[MESA_SHADER_TASK].info) { - const bool afs = device->physical->instance->assume_full_subgroups; + const uint8_t afs = device->physical->instance->assume_full_subgroups; _mesa_sha1_update(&ctx, &afs, sizeof(afs)); } @@ -789,7 +789,7 @@ anv_pipeline_hash_compute(struct anv_compute_pipeline *pipeline, anv_pipeline_hash_common(&ctx, &pipeline->base); - const bool afs = device->physical->instance->assume_full_subgroups; + const uint8_t afs = device->physical->instance->assume_full_subgroups; _mesa_sha1_update(&ctx, &afs, sizeof(afs)); _mesa_sha1_update(&ctx, stage->shader_sha1, @@ -1991,7 +1991,9 @@ anv_fixup_subgroup_size(struct anv_device *device, struct shader_info *info) * a size. */ if (info->subgroup_size == SUBGROUP_SIZE_FULL_SUBGROUPS) - info->subgroup_size = BRW_SUBGROUP_SIZE; + info->subgroup_size = + device->physical->instance->assume_full_subgroups != 0 ? + device->physical->instance->assume_full_subgroups : BRW_SUBGROUP_SIZE; } static void diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 15a746126ab..fe5544addd5 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -805,7 +805,7 @@ struct anv_queue_family { enum intel_engine_class engine_class; }; -#define ANV_MAX_QUEUE_FAMILIES 4 +#define ANV_MAX_QUEUE_FAMILIES 5 struct anv_memory_type { /* Standard bits passed on to the client */ @@ -895,7 +895,8 @@ struct anv_physical_device { bool flush_astc_ldr_void_extent_denorms; /** True if ASTC LDR is supported via emulation */ bool emu_astc_ldr; - + /* true if FCV optimization should be disabled. */ + bool disable_fcv; /**/ bool uses_ex_bso; @@ -1021,7 +1022,7 @@ struct anv_instance { /** * Workarounds for game bugs. */ - bool assume_full_subgroups; + uint8_t assume_full_subgroups; bool limit_trig_input_range; bool sample_mask_out_opengl_behaviour; bool fp64_workaround_enabled; @@ -1032,6 +1033,7 @@ struct anv_instance { unsigned query_copy_with_shader_threshold; unsigned force_vk_vendor; bool has_fake_sparse; + bool disable_fcv; /* HW workarounds */ bool no_16bit; @@ -4684,6 +4686,8 @@ struct anv_image { * boolean will prevent the usage of CC_ONE. */ bool can_non_zero_fast_clear; + + bool aux_ccs_mapped; } planes[3]; struct anv_image_memory_range vid_dmv_top_surface; @@ -4940,6 +4944,24 @@ anv_bo_allows_aux_map(const struct anv_device *device, return true; } +static inline bool +anv_address_allows_aux_map(const struct anv_device *device, + struct anv_address addr) +{ + if (device->aux_map_ctx == NULL) + return false; + + /* Technically, we really only care about what offset the image is bound + * into on the BO, but we don't have that information here. As a heuristic, + * rely on the BO offset instead. + */ + if (((addr.bo ? addr.bo->offset : 0) + addr.offset) % + intel_aux_map_get_alignment(device->aux_map_ctx) != 0) + return false; + + return true; +} + void anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer *cmd_buffer, const struct anv_image *image, diff --git a/src/intel/vulkan/genX_blorp_exec.c b/src/intel/vulkan/genX_blorp_exec.c index a98319736ea..a8ee4f7219f 100644 --- a/src/intel/vulkan/genX_blorp_exec.c +++ b/src/intel/vulkan/genX_blorp_exec.c @@ -358,6 +358,7 @@ blorp_exec_on_render(struct blorp_batch *batch, #if GFX_VER >= 12 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PRIMITIVE_REPLICATION); #endif + BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VIEWPORT_CC); BITSET_SET(hw_state->dirty, ANV_GFX_STATE_STREAMOUT); BITSET_SET(hw_state->dirty, ANV_GFX_STATE_RASTER); BITSET_SET(hw_state->dirty, ANV_GFX_STATE_CLIP); @@ -386,8 +387,7 @@ blorp_exec_on_render(struct blorp_batch *batch, BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PS_BLEND); } - anv_cmd_dirty_mask_t dirty = ~(ANV_CMD_DIRTY_PIPELINE | - ANV_CMD_DIRTY_INDEX_BUFFER | + anv_cmd_dirty_mask_t dirty = ~(ANV_CMD_DIRTY_INDEX_BUFFER | ANV_CMD_DIRTY_XFB_ENABLE); cmd_buffer->state.gfx.vb_dirty = ~0; diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 424e917ee6a..9142d066365 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -915,7 +915,7 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer, dst_queue_family != VK_QUEUE_FAMILY_IGNORED && src_queue_family != dst_queue_family) { enum intel_engine_class src_engine = - cmd_buffer->queue_family[src_queue_family].engine_class; + cmd_buffer->queue_family->engine_class; if (src_engine != INTEL_ENGINE_CLASS_RENDER) return; } @@ -3295,6 +3295,19 @@ genX(BeginCommandBuffer)( if (cmd_buffer->vk.level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) cmd_buffer->usage_flags &= ~VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT; +#if GFX_VER >= 12 + /* Reenable prefetching at the beginning of secondary command buffers. We + * do this so that the return instruction edition is not prefetched before + * completion. + */ + if (cmd_buffer->vk.level == VK_COMMAND_BUFFER_LEVEL_SECONDARY) { + anv_batch_emit(&cmd_buffer->batch, GENX(MI_ARB_CHECK), arb) { + arb.PreParserDisableMask = true; + arb.PreParserDisable = false; + } + } +#endif + trace_intel_begin_cmd_buffer(&cmd_buffer->trace); if (anv_cmd_buffer_is_video_queue(cmd_buffer) || @@ -4545,7 +4558,7 @@ void genX(CmdDrawMultiIndexedEXT)( prim.StartInstanceLocation = firstInstance; prim.BaseVertexLocation = pVertexOffset ? *pVertexOffset : draw->vertexOffset; prim.ExtendedParametersPresent = true; - prim.ExtendedParameter0 = draw->vertexOffset; + prim.ExtendedParameter0 = pVertexOffset ? *pVertexOffset : draw->vertexOffset; prim.ExtendedParameter1 = firstInstance; prim.ExtendedParameter2 = i; } @@ -8073,7 +8086,8 @@ void genX(cmd_emit_timestamp)(struct anv_batch *batch, * ANV_TIMESTAMP_REWRITE_COMPUTE_WALKER capture type are not set for * transfer queue. */ - if (batch->engine_class == INTEL_ENGINE_CLASS_COPY) { + if ((batch->engine_class == INTEL_ENGINE_CLASS_COPY) || + (batch->engine_class == INTEL_ENGINE_CLASS_VIDEO)) { assert(type != ANV_TIMESTAMP_CAPTURE_AT_CS_STALL && type != ANV_TIMESTAMP_REWRITE_COMPUTE_WALKER); } @@ -8087,7 +8101,8 @@ void genX(cmd_emit_timestamp)(struct anv_batch *batch, } case ANV_TIMESTAMP_CAPTURE_END_OF_PIPE: { - if (batch->engine_class == INTEL_ENGINE_CLASS_COPY) { + if ((batch->engine_class == INTEL_ENGINE_CLASS_COPY) || + (batch->engine_class == INTEL_ENGINE_CLASS_VIDEO)) { anv_batch_emit(batch, GENX(MI_FLUSH_DW), fd) { fd.PostSyncOperation = WriteTimestamp; fd.Address = addr; @@ -8128,6 +8143,53 @@ void genX(cmd_emit_timestamp)(struct anv_batch *batch, } } +void genX(batch_emit_secondary_call)(struct anv_batch *batch, + struct anv_address secondary_addr, + struct anv_address secondary_return_addr) +{ + /* Emit a write to change the return address of the secondary */ + uint64_t *write_return_addr = + anv_batch_emitn(batch, + GENX(MI_STORE_DATA_IMM_length) + 1 /* QWord write */, + GENX(MI_STORE_DATA_IMM), +#if GFX_VER >= 12 + .ForceWriteCompletionCheck = true, +#endif + .Address = secondary_return_addr) + + GENX(MI_STORE_DATA_IMM_ImmediateData_start) / 8; + +#if GFX_VER >= 12 + /* Disable prefetcher before jumping into a secondary */ + anv_batch_emit(batch, GENX(MI_ARB_CHECK), arb) { + arb.PreParserDisableMask = true; + arb.PreParserDisable = true; + } +#endif + + /* Jump into the secondary */ + anv_batch_emit(batch, GENX(MI_BATCH_BUFFER_START), bbs) { + bbs.AddressSpaceIndicator = ASI_PPGTT; + bbs.SecondLevelBatchBuffer = Firstlevelbatch; + bbs.BatchBufferStartAddress = secondary_addr; + } + + /* Replace the return address written by the MI_STORE_DATA_IMM above with + * the primary's current batch address (immediately after the jump). + */ + *write_return_addr = + anv_address_physical(anv_batch_current_address(batch)); +} + +void * +genX(batch_emit_return)(struct anv_batch *batch) +{ + return anv_batch_emitn(batch, + GENX(MI_BATCH_BUFFER_START_length), + GENX(MI_BATCH_BUFFER_START), + .AddressSpaceIndicator = ASI_PPGTT, + .SecondLevelBatchBuffer = Firstlevelbatch); +} + void genX(batch_emit_dummy_post_sync_op)(struct anv_batch *batch, struct anv_device *device, diff --git a/src/intel/vulkan/genX_cmd_draw_generated_indirect.h b/src/intel/vulkan/genX_cmd_draw_generated_indirect.h index 7eb19307d56..8f90b016462 100644 --- a/src/intel/vulkan/genX_cmd_draw_generated_indirect.h +++ b/src/intel/vulkan/genX_cmd_draw_generated_indirect.h @@ -114,13 +114,6 @@ genX(cmd_buffer_emit_generate_draws)(struct anv_cmd_buffer *cmd_buffer, static void genX(cmd_buffer_emit_indirect_generated_draws_init)(struct anv_cmd_buffer *cmd_buffer) { -#if GFX_VER >= 12 - anv_batch_emit(&cmd_buffer->batch, GENX(MI_ARB_CHECK), arb) { - arb.PreParserDisableMask = true; - arb.PreParserDisable = true; - } -#endif - anv_batch_emit_ensure_space(&cmd_buffer->generation.batch, 4); trace_intel_begin_generate_draws(&cmd_buffer->trace); @@ -133,6 +126,13 @@ genX(cmd_buffer_emit_indirect_generated_draws_init)(struct anv_cmd_buffer *cmd_b cmd_buffer->generation.return_addr = anv_batch_current_address(&cmd_buffer->batch); +#if GFX_VER >= 12 + anv_batch_emit(&cmd_buffer->batch, GENX(MI_ARB_CHECK), arb) { + arb.PreParserDisableMask = true; + arb.PreParserDisable = false; + } +#endif + trace_intel_end_generate_draws(&cmd_buffer->trace); struct anv_device *device = cmd_buffer->device; @@ -354,6 +354,9 @@ genX(cmd_buffer_emit_indirect_generated_draws_inring)(struct anv_cmd_buffer *cmd if (cmd_buffer->generation.ring_bo == NULL) { const uint32_t bo_size = align( +#if GFX_VER >= 12 + GENX(MI_ARB_CHECK_length) * 4 + +#endif draw_cmd_stride * MAX_RING_BO_ITEMS + #if GFX_VER == 9 4 * MAX_RING_BO_ITEMS + @@ -376,6 +379,8 @@ genX(cmd_buffer_emit_indirect_generated_draws_inring)(struct anv_cmd_buffer *cmd /* The ring bo has the following layout: * * -------------------------------------------------- + * | MI_ARB_CHECK to resume CS prefetch (Gfx12+) | + * |------------------------------------------------| * | ring_count * 3DPRIMITIVE | * |------------------------------------------------| * | jump instruction (either back to generate more | @@ -391,6 +396,22 @@ genX(cmd_buffer_emit_indirect_generated_draws_inring)(struct anv_cmd_buffer *cmd GENX(MI_BATCH_BUFFER_START_length) * 4, }; + struct anv_address draw_cmds_addr = (struct anv_address) { + .bo = cmd_buffer->generation.ring_bo, +#if GFX_VER >= 12 + .offset = GENX(MI_ARB_CHECK_length) * 4, +#endif + }; + +#if GFX_VER >= 12 + struct GENX(MI_ARB_CHECK) resume_prefetch = { + .PreParserDisableMask = true, + .PreParserDisable = false, + }; + GENX(MI_ARB_CHECK_pack)(NULL, cmd_buffer->generation.ring_bo->map, + &resume_prefetch); +#endif + #if GFX_VER == 9 /* Mark the VB-0 as using the entire ring_bo, but only for the draw call * starting the generation batch. All the following ones will use the same @@ -437,16 +458,6 @@ genX(cmd_buffer_emit_indirect_generated_draws_inring)(struct anv_cmd_buffer *cmd */ struct anv_address gen_addr = anv_batch_current_address(&cmd_buffer->batch); -#if GFX_VER >= 12 - /* Prior to Gfx12 we cannot disable the CS prefetch but it doesn't matter - * as the prefetch shouldn't follow the MI_BATCH_BUFFER_START. - */ - anv_batch_emit(&cmd_buffer->batch, GENX(MI_ARB_CHECK), arb) { - arb.PreParserDisableMask = true; - arb.PreParserDisable = true; - } -#endif - struct anv_simple_shader simple_state = (struct anv_simple_shader) { .device = device, .cmd_buffer = cmd_buffer, @@ -463,9 +474,7 @@ genX(cmd_buffer_emit_indirect_generated_draws_inring)(struct anv_cmd_buffer *cmd genX(cmd_buffer_emit_generate_draws)( cmd_buffer, &simple_state, - (struct anv_address) { - .bo = cmd_buffer->generation.ring_bo, - }, + draw_cmds_addr, draw_cmd_stride, indirect_data_addr, indirect_data_stride, @@ -486,13 +495,6 @@ genX(cmd_buffer_emit_indirect_generated_draws_inring)(struct anv_cmd_buffer *cmd ANV_PIPE_CS_STALL_BIT, "after generation flush"); -#if GFX_VER >= 12 - anv_batch_emit(&cmd_buffer->batch, GENX(MI_ARB_CHECK), arb) { - arb.PreParserDisableMask = true; - arb.PreParserDisable = false; - } -#endif - trace_intel_end_generate_draws(&cmd_buffer->trace); if (cmd_buffer->state.conditional_render_enabled) @@ -502,6 +504,16 @@ genX(cmd_buffer_emit_indirect_generated_draws_inring)(struct anv_cmd_buffer *cmd genX(cmd_buffer_flush_gfx_state)(cmd_buffer); if (max_draw_count > 0) { +#if GFX_VER >= 12 + /* Prior to Gfx12 we cannot disable the CS prefetch but it doesn't matter + * as the prefetch shouldn't follow the MI_BATCH_BUFFER_START. + */ + anv_batch_emit(&cmd_buffer->batch, GENX(MI_ARB_CHECK), arb) { + arb.PreParserDisableMask = true; + arb.PreParserDisable = true; + } +#endif + /* Jump into the ring buffer. */ anv_batch_emit(&cmd_buffer->batch, GENX(MI_BATCH_BUFFER_START), bbs) { bbs.AddressSpaceIndicator = ASI_PPGTT; @@ -636,7 +648,7 @@ genX(cmd_buffer_flush_generated_draws)(struct anv_cmd_buffer *cmd_buffer) #if GFX_VER >= 12 anv_batch_emit(batch, GENX(MI_ARB_CHECK), arb) { arb.PreParserDisableMask = true; - arb.PreParserDisable = false; + arb.PreParserDisable = true; } #else /* Prior to Gfx12 we cannot disable the CS prefetch but it doesn't matter diff --git a/src/intel/vulkan/genX_init_state.c b/src/intel/vulkan/genX_init_state.c index c0ca960059c..1bbd215384d 100644 --- a/src/intel/vulkan/genX_init_state.c +++ b/src/intel/vulkan/genX_init_state.c @@ -149,21 +149,22 @@ genX(emit_slice_hashing_state)(struct anv_device *device, ptr.SliceHashTableStatePointer = device->slice_hash.offset; } + /* TODO: Figure out FCV support for other platforms + * Testing indicates that FCV is broken on MTL, but works fine on DG2. + * Let's disable FCV on MTL for now till we figure out what's wrong. + * + * Alternatively, it can be toggled off via drirc option 'anv_disable_fcv'. + * + * Ref: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9987 + */ anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), mode) { mode.SliceHashingTableEnable = true; mode.SliceHashingTableEnableMask = true; mode.CrossSliceHashingMode = (util_bitcount(ppipe_mask) > 1 ? hashing32x32 : NormalMode); mode.CrossSliceHashingModeMask = -1; - /* TODO: Figure out FCV support for other platforms - * Testing indicates that FCV is broken on MTL, but works fine on DG2. - * Let's disable FCV on MTL for now till we figure out what's wrong. - * - * Ref: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9987 - */ - mode.FastClearOptimizationEnable = intel_device_info_is_dg2(device->info); - mode.FastClearOptimizationEnableMask = - intel_device_info_is_dg2(device->info); + mode.FastClearOptimizationEnable = !device->physical->disable_fcv; + mode.FastClearOptimizationEnableMask = !device->physical->disable_fcv; } #endif } diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c index f42298f85ab..1f194427669 100644 --- a/src/intel/vulkan/genX_query.c +++ b/src/intel/vulkan/genX_query.c @@ -695,7 +695,7 @@ emit_query_pc_availability(struct anv_cmd_buffer *cmd_buffer, genx_batch_emit_pipe_control_write (&cmd_buffer->batch, cmd_buffer->device->info, WriteImmediateData, addr, - available, ANV_PIPE_CS_STALL_BIT); + available, 0); } /** @@ -1391,12 +1391,22 @@ void genX(CmdWriteTimestamp2)( bool cs_stall_needed = (GFX_VER == 9 && cmd_buffer->device->info->gt == 4); - genx_batch_emit_pipe_control_write - (&cmd_buffer->batch, cmd_buffer->device->info, WriteTimestamp, - anv_address_add(query_addr, 8), 0, - cs_stall_needed ? ANV_PIPE_CS_STALL_BIT : 0); - emit_query_pc_availability(cmd_buffer, query_addr, true); + if (anv_cmd_buffer_is_blitter_queue(cmd_buffer) || + anv_cmd_buffer_is_video_queue(cmd_buffer)) { + anv_batch_emit(&cmd_buffer->batch, GENX(MI_FLUSH_DW), dw) { + dw.Address = anv_address_add(query_addr, 8); + dw.PostSyncOperation = WriteTimestamp; + } + emit_query_mi_flush_availability(cmd_buffer, query_addr, true); + } else { + genx_batch_emit_pipe_control_write + (&cmd_buffer->batch, cmd_buffer->device->info, WriteTimestamp, + anv_address_add(query_addr, 8), 0, + cs_stall_needed ? ANV_PIPE_CS_STALL_BIT : 0); + emit_query_pc_availability(cmd_buffer, query_addr, true); + } + } diff --git a/src/intel/vulkan/genX_simple_shader.c b/src/intel/vulkan/genX_simple_shader.c index ee87eb6ef48..6ce78b5c0a0 100644 --- a/src/intel/vulkan/genX_simple_shader.c +++ b/src/intel/vulkan/genX_simple_shader.c @@ -310,6 +310,7 @@ genX(emit_simpler_shader_init_fragment)(struct anv_simple_shader *state) BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PRIMITIVE_REPLICATION); #endif BITSET_SET(hw_state->dirty, ANV_GFX_STATE_STREAMOUT); + BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VIEWPORT_CC); BITSET_SET(hw_state->dirty, ANV_GFX_STATE_CLIP); BITSET_SET(hw_state->dirty, ANV_GFX_STATE_RASTER); BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SAMPLE_MASK); diff --git a/src/intel/vulkan/i915/anv_kmd_backend.c b/src/intel/vulkan/i915/anv_kmd_backend.c index d0f99b542bd..7641db181a3 100644 --- a/src/intel/vulkan/i915/anv_kmd_backend.c +++ b/src/intel/vulkan/i915/anv_kmd_backend.c @@ -59,6 +59,23 @@ i915_gem_create(struct anv_device *device, if (intel_ioctl(device->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create)) return 0; + if (alloc_flags & ANV_BO_ALLOC_SNOOPED) { + /* We don't want to change these defaults if it's going to be shared + * with another process. + */ + assert(!(alloc_flags & ANV_BO_ALLOC_EXTERNAL)); + + /* Regular objects are created I915_CACHING_CACHED on LLC platforms and + * I915_CACHING_NONE on non-LLC platforms. For many internal state + * objects, we'd rather take the snooping overhead than risk forgetting + * a CLFLUSH somewhere. Userptr objects are always created as + * I915_CACHING_CACHED, which on non-LLC means snooped so there's no + * need to do this there. + */ + if (device->info->has_caching_uapi && !device->info->has_llc) + i915_gem_set_caching(device, gem_create.handle, I915_CACHING_CACHED); + } + *actual_size = gem_create.size; return gem_create.handle; } diff --git a/src/intel/vulkan/shaders/meson.build b/src/intel/vulkan/shaders/meson.build index 7586babf5f2..12f99c510ac 100644 --- a/src/intel/vulkan/shaders/meson.build +++ b/src/intel/vulkan/shaders/meson.build @@ -48,7 +48,8 @@ foreach item : anv_internal_shaders anv_internal_spvs += custom_target( spv_filename, input : [glsl2spirv, f, files('common_generated_draws.glsl', - 'common_query_copy.glsl')], + 'common_query_copy.glsl', + 'interface.h')], output : spv_filename, command : [ prog_python, '@INPUT0@', '@INPUT1@', '@OUTPUT@', diff --git a/src/intel/vulkan_hasvk/anv_batch_chain.c b/src/intel/vulkan_hasvk/anv_batch_chain.c index 4dd013c485d..ec775611765 100644 --- a/src/intel/vulkan_hasvk/anv_batch_chain.c +++ b/src/intel/vulkan_hasvk/anv_batch_chain.c @@ -1899,6 +1899,7 @@ setup_execbuf_for_cmd_buffers(struct anv_execbuf *execbuf, anv_cmd_buffer_process_relocs(cmd_buffers[0], &cmd_buffers[0]->surface_relocs); } +#ifdef SUPPORT_INTEL_INTEGRATED_GPUS if (device->physical->memory.need_flush) { __builtin_ia32_mfence(); for (uint32_t i = 0; i < num_cmd_buffers; i++) { @@ -1908,6 +1909,7 @@ setup_execbuf_for_cmd_buffers(struct anv_execbuf *execbuf, } __builtin_ia32_mfence(); } +#endif struct anv_batch *batch = &cmd_buffers[0]->batch; execbuf->execbuf = (struct drm_i915_gem_execbuffer2) { @@ -1986,8 +1988,10 @@ setup_utrace_execbuf(struct anv_execbuf *execbuf, struct anv_queue *queue, flush->batch_bo->exec_obj_index = last_idx; } +#ifdef SUPPORT_INTEL_INTEGRATED_GPUS if (device->physical->memory.need_flush) intel_flush_range(flush->batch_bo->map, flush->batch_bo->size); +#endif execbuf->execbuf = (struct drm_i915_gem_execbuffer2) { .buffers_ptr = (uintptr_t) execbuf->objects, @@ -2421,8 +2425,10 @@ anv_queue_submit_simple_batch(struct anv_queue *queue, return result; memcpy(batch_bo->map, batch->start, batch_size); +#ifdef SUPPORT_INTEL_INTEGRATED_GPUS if (device->physical->memory.need_flush) intel_flush_range(batch_bo->map, batch_size); +#endif struct anv_execbuf execbuf = { .alloc = &queue->device->vk.alloc, diff --git a/src/intel/vulkan_hasvk/anv_device.c b/src/intel/vulkan_hasvk/anv_device.c index 6798f607b29..6935232c86b 100644 --- a/src/intel/vulkan_hasvk/anv_device.c +++ b/src/intel/vulkan_hasvk/anv_device.c @@ -67,7 +67,7 @@ static const driOptionDescription anv_dri_options[] = { DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0) DRI_CONF_VK_X11_STRICT_IMAGE_COUNT(false) DRI_CONF_VK_XWAYLAND_WAIT_READY(true) - DRI_CONF_ANV_ASSUME_FULL_SUBGROUPS(false) + DRI_CONF_ANV_ASSUME_FULL_SUBGROUPS(0) DRI_CONF_ANV_SAMPLE_MASK_OUT_OPENGL_BEHAVIOUR(false) DRI_CONF_NO_16BIT(false) DRI_CONF_SECTION_END @@ -1324,7 +1324,7 @@ anv_init_dri_options(struct anv_instance *instance) instance->vk.app_info.engine_version); instance->assume_full_subgroups = - driQueryOptionb(&instance->dri_options, "anv_assume_full_subgroups"); + driQueryOptioni(&instance->dri_options, "anv_assume_full_subgroups"); instance->limit_trig_input_range = driQueryOptionb(&instance->dri_options, "limit_trig_input_range"); instance->sample_mask_out_opengl_behaviour = @@ -2333,8 +2333,10 @@ anv_device_init_trivial_batch(struct anv_device *device) anv_batch_emit(&batch, GFX7_MI_BATCH_BUFFER_END, bbe); anv_batch_emit(&batch, GFX7_MI_NOOP, noop); +#ifdef SUPPORT_INTEL_INTEGRATED_GPUS if (device->physical->memory.need_flush) intel_flush_range(batch.start, batch.next - batch.start); +#endif return VK_SUCCESS; } @@ -3480,8 +3482,10 @@ VkResult anv_FlushMappedMemoryRanges( if (!device->physical->memory.need_flush) return VK_SUCCESS; +#ifdef SUPPORT_INTEL_INTEGRATED_GPUS /* Make sure the writes we're flushing have landed. */ __builtin_ia32_mfence(); +#endif for (uint32_t i = 0; i < memoryRangeCount; i++) { ANV_FROM_HANDLE(anv_device_memory, mem, pMemoryRanges[i].memory); @@ -3492,9 +3496,11 @@ VkResult anv_FlushMappedMemoryRanges( if (map_offset >= mem->map_size) continue; +#ifdef SUPPORT_INTEL_INTEGRATED_GPUS intel_flush_range(mem->map + map_offset, MIN2(pMemoryRanges[i].size, mem->map_size - map_offset)); +#endif } return VK_SUCCESS; @@ -3519,13 +3525,17 @@ VkResult anv_InvalidateMappedMemoryRanges( if (map_offset >= mem->map_size) continue; +#ifdef SUPPORT_INTEL_INTEGRATED_GPUS intel_invalidate_range(mem->map + map_offset, MIN2(pMemoryRanges[i].size, mem->map_size - map_offset)); +#endif } +#ifdef SUPPORT_INTEL_INTEGRATED_GPUS /* Make sure no reads get moved up above the invalidate. */ __builtin_ia32_mfence(); +#endif return VK_SUCCESS; } diff --git a/src/intel/vulkan_hasvk/anv_pipeline.c b/src/intel/vulkan_hasvk/anv_pipeline.c index 6df9c3f79ff..3e0671d992a 100644 --- a/src/intel/vulkan_hasvk/anv_pipeline.c +++ b/src/intel/vulkan_hasvk/anv_pipeline.c @@ -472,7 +472,7 @@ anv_pipeline_hash_compute(struct anv_compute_pipeline *pipeline, const bool rba = device->vk.enabled_features.robustBufferAccess; _mesa_sha1_update(&ctx, &rba, sizeof(rba)); - const bool afs = device->physical->instance->assume_full_subgroups; + const uint8_t afs = device->physical->instance->assume_full_subgroups; _mesa_sha1_update(&ctx, &afs, sizeof(afs)); _mesa_sha1_update(&ctx, stage->shader_sha1, @@ -1581,7 +1581,9 @@ anv_pipeline_compile_cs(struct anv_compute_pipeline *pipeline, * a size. */ if (stage.nir->info.subgroup_size == SUBGROUP_SIZE_FULL_SUBGROUPS) - stage.nir->info.subgroup_size = BRW_SUBGROUP_SIZE; + stage.nir->info.subgroup_size = + device->physical->instance->assume_full_subgroups != 0 ? + device->physical->instance->assume_full_subgroups : BRW_SUBGROUP_SIZE; stage.num_stats = 1; diff --git a/src/intel/vulkan_hasvk/anv_private.h b/src/intel/vulkan_hasvk/anv_private.h index 663f3ccc9a0..6cff8e33a18 100644 --- a/src/intel/vulkan_hasvk/anv_private.h +++ b/src/intel/vulkan_hasvk/anv_private.h @@ -944,7 +944,7 @@ struct anv_instance { /** * Workarounds for game bugs. */ - bool assume_full_subgroups; + uint8_t assume_full_subgroups; bool limit_trig_input_range; bool sample_mask_out_opengl_behaviour; float lower_depth_range_rate; @@ -1416,7 +1416,7 @@ anv_batch_emit_reloc(struct anv_batch *batch, static inline void write_reloc(const struct anv_device *device, void *p, uint64_t v, bool flush) { - unsigned reloc_size = 0; + UNUSED unsigned reloc_size = 0; if (device->info->ver >= 8) { reloc_size = sizeof(uint64_t); *(uint64_t *)p = intel_canonical_address(v); @@ -1425,8 +1425,10 @@ write_reloc(const struct anv_device *device, void *p, uint64_t v, bool flush) *(uint32_t *)p = v; } +#ifdef SUPPORT_INTEL_INTEGRATED_GPUS if (flush && device->physical->memory.need_flush) intel_flush_range(p, reloc_size); +#endif } static inline uint64_t diff --git a/src/intel/vulkan_hasvk/anv_wsi.c b/src/intel/vulkan_hasvk/anv_wsi.c index 0c807371316..93b7539fe23 100644 --- a/src/intel/vulkan_hasvk/anv_wsi.c +++ b/src/intel/vulkan_hasvk/anv_wsi.c @@ -97,10 +97,12 @@ VkResult anv_QueuePresentKHR( if (device->debug_frame_desc) { device->debug_frame_desc->frame_id++; +#ifdef SUPPORT_INTEL_INTEGRATED_GPUS if (device->physical->memory.need_flush) { intel_flush_range(device->debug_frame_desc, sizeof(*device->debug_frame_desc)); } +#endif } result = vk_queue_wait_before_present(&queue->vk, pPresentInfo); diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c index 64ed8024554..0e6e4760658 100644 --- a/src/mesa/main/bufferobj.c +++ b/src/mesa/main/bufferobj.c @@ -3373,14 +3373,14 @@ copy_buffer_sub_data(struct gl_context *ctx, struct gl_buffer_object *src, return; } - if (readOffset + size > src->Size) { + if (size > src->Size || readOffset > src->Size - size) { _mesa_error(ctx, GL_INVALID_VALUE, "%s(readOffset %d + size %d > src_buffer_size %d)", func, (int) readOffset, (int) size, (int) src->Size); return; } - if (writeOffset + size > dst->Size) { + if (size > dst->Size || writeOffset > dst->Size - size) { _mesa_error(ctx, GL_INVALID_VALUE, "%s(writeOffset %d + size %d > dst_buffer_size %d)", func, (int) writeOffset, (int) size, (int) dst->Size); diff --git a/src/mesa/main/get_hash_params.py b/src/mesa/main/get_hash_params.py index 90d09c4a631..267efa5b3be 100644 --- a/src/mesa/main/get_hash_params.py +++ b/src/mesa/main/get_hash_params.py @@ -494,6 +494,10 @@ # GL_EXT_framebuffer_EXT / GLES 3.0 + EXT_sRGB_write_control [ "FRAMEBUFFER_SRGB_EXT", "CONTEXT_BOOL(Color.sRGBEnabled), extra_EXT_framebuffer_sRGB" ], + +# GL_ARB_cull_distance, GL_EXT_clip_cull_distance + [ "MAX_CULL_DISTANCES", "CONTEXT_INT(Const.MaxClipPlanes), extra_ARB_cull_distance" ], + [ "MAX_COMBINED_CLIP_AND_CULL_DISTANCES", "CONTEXT_INT(Const.MaxClipPlanes), extra_ARB_cull_distance" ], ]}, { "apis": ["GLES", "GLES2"], "params": [ @@ -1009,10 +1013,6 @@ [ "GPU_MEMORY_INFO_EVICTION_COUNT_NVX", "LOC_CUSTOM, TYPE_INT, NO_OFFSET, extra_NVX_gpu_memory_info" ], [ "GPU_MEMORY_INFO_EVICTED_MEMORY_NVX", "LOC_CUSTOM, TYPE_INT, NO_OFFSET, extra_NVX_gpu_memory_info" ], -# GL_ARB_cull_distance - [ "MAX_CULL_DISTANCES", "CONTEXT_INT(Const.MaxClipPlanes), extra_ARB_cull_distance" ], - [ "MAX_COMBINED_CLIP_AND_CULL_DISTANCES", "CONTEXT_INT(Const.MaxClipPlanes), extra_ARB_cull_distance" ], - # GL_ARB_compute_variable_group_size [ "MAX_COMPUTE_VARIABLE_GROUP_INVOCATIONS_ARB", "CONTEXT_INT(Const.MaxComputeVariableGroupInvocations), extra_ARB_compute_variable_group_size" ], diff --git a/src/mesa/main/glthread_draw.c b/src/mesa/main/glthread_draw.c index b747493aba7..e1d0611d762 100644 --- a/src/mesa/main/glthread_draw.c +++ b/src/mesa/main/glthread_draw.c @@ -813,7 +813,8 @@ should_convert_to_begin_end(struct gl_context *ctx, unsigned count, * Others prevent syncing, such as disallowing buffer objects because we * can't map them without syncing. */ - return util_is_vbo_upload_ratio_too_large(count, num_upload_vertices) && + return ctx->API == API_OPENGL_COMPAT && + util_is_vbo_upload_ratio_too_large(count, num_upload_vertices) && instance_count == 1 && /* no instancing */ vao->CurrentElementBufferName == 0 && /* only user indices */ !ctx->GLThread._PrimitiveRestart && /* no primitive restart */ diff --git a/src/mesa/main/state.c b/src/mesa/main/state.c index 736b2ae6c2b..784dafd07ff 100644 --- a/src/mesa/main/state.c +++ b/src/mesa/main/state.c @@ -687,6 +687,9 @@ set_vertex_processing_mode(struct gl_context *ctx, gl_vertex_processing_mode m) default: assert(0); } + + _mesa_set_varying_vp_inputs(ctx, ctx->VertexProgram._VPModeInputFilter & + ctx->Array._DrawVAO->_EnabledWithMapMode); } diff --git a/src/mesa/state_tracker/st_cb_texture.c b/src/mesa/state_tracker/st_cb_texture.c index f0d0b576152..3b75d012301 100644 --- a/src/mesa/state_tracker/st_cb_texture.c +++ b/src/mesa/state_tracker/st_cb_texture.c @@ -169,6 +169,11 @@ create_dst_texture(struct gl_context *ctx, struct pipe_screen *screen = st->screen; struct pipe_resource dst_templ; + if (pipe_target == PIPE_TEXTURE_CUBE || pipe_target == PIPE_TEXTURE_CUBE_ARRAY) { + width = MAX2(width, height); + height = MAX2(width, height); + } + /* create the destination texture of size (width X height X depth) */ memset(&dst_templ, 0, sizeof(dst_templ)); dst_templ.target = pipe_target; diff --git a/src/microsoft/vulkan/dzn_device.c b/src/microsoft/vulkan/dzn_device.c index a11a482e1e1..c95742fbde3 100644 --- a/src/microsoft/vulkan/dzn_device.c +++ b/src/microsoft/vulkan/dzn_device.c @@ -2806,7 +2806,7 @@ dzn_device_memory_create(struct dzn_device *device, if (!device->dev13) goto cleanup; - if (FAILED(ID3D12Device13_OpenExistingHeapFromAddress1(device->dev13, host_pointer, heap_desc.SizeInBytes, &IID_ID3D12Heap, &mem->heap))) + if (FAILED(ID3D12Device13_OpenExistingHeapFromAddress1(device->dev13, host_pointer, heap_desc.SizeInBytes, &IID_ID3D12Heap, (void**)&mem->heap))) goto cleanup; D3D12_HEAP_DESC desc = dzn_ID3D12Heap_GetDesc(mem->heap); @@ -3920,7 +3920,7 @@ dzn_GetMemoryHostPointerPropertiesEXT(VkDevice _device, return VK_ERROR_FEATURE_NOT_PRESENT; ID3D12Heap *heap; - if (FAILED(ID3D12Device13_OpenExistingHeapFromAddress1(device->dev13, pHostPointer, 1, &IID_ID3D12Heap, &heap))) + if (FAILED(ID3D12Device13_OpenExistingHeapFromAddress1(device->dev13, pHostPointer, 1, &IID_ID3D12Heap, (void **)&heap))) return VK_ERROR_INVALID_EXTERNAL_HANDLE; struct dzn_physical_device *pdev = container_of(device->vk.physical, struct dzn_physical_device, vk); diff --git a/src/nouveau/vulkan/nvk_cmd_buffer.c b/src/nouveau/vulkan/nvk_cmd_buffer.c index f93e6da6899..8fefcd58560 100644 --- a/src/nouveau/vulkan/nvk_cmd_buffer.c +++ b/src/nouveau/vulkan/nvk_cmd_buffer.c @@ -183,7 +183,7 @@ nvk_cmd_buffer_upload_alloc(struct nvk_cmd_buffer *cmd, assert(size <= NVK_CMD_BO_SIZE); uint32_t offset = cmd->upload_offset; - if (align > 0) + if (alignment > 0) offset = align(offset, alignment); assert(offset <= NVK_CMD_BO_SIZE); @@ -649,7 +649,8 @@ nvk_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, struct nv_push *p = nvk_cmd_buffer_push(cmd, 6); P_IMMD(p, NVC597, SET_MME_DATA_FIFO_CONFIG, FIFO_SIZE_SIZE_4KB); P_1INC(p, NV9097, CALL_MME_MACRO(NVK_MME_XFB_COUNTER_LOAD)); - P_INLINE_DATA(p, cb_idx); + /* The STREAM_OUT_BUFFER_LOAD_WRITE_POINTER registers are 8 dword stride */ + P_INLINE_DATA(p, cb_idx * 8); P_INLINE_DATA(p, cb_addr >> 32); P_INLINE_DATA(p, cb_addr); } else { @@ -658,7 +659,8 @@ nvk_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, __push_immd(p, SUBC_NV9097, NV906F_SET_REFERENCE, 0); P_1INC(p, NV9097, CALL_MME_MACRO(NVK_MME_XFB_COUNTER_LOAD)); - P_INLINE_DATA(p, cb_idx); + /* The STREAM_OUT_BUFFER_LOAD_WRITE_POINTER registers are 8 dword stride */ + P_INLINE_DATA(p, cb_idx * 8); nv_push_update_count(p, 1); nvk_cmd_buffer_push_indirect_buffer(cmd, buffer, offset, 4); } diff --git a/src/nouveau/vulkan/nvk_nir_lower_descriptors.c b/src/nouveau/vulkan/nvk_nir_lower_descriptors.c index d3d98667b4c..c4d4f7bf17c 100644 --- a/src/nouveau/vulkan/nvk_nir_lower_descriptors.c +++ b/src/nouveau/vulkan/nvk_nir_lower_descriptors.c @@ -682,12 +682,15 @@ nvk_nir_lower_descriptors(nir_shader *nir, * are left and lowers them to slightly less efficient but variable- * pointers-correct versions. */ - return nir_shader_instructions_pass(nir, try_lower_descriptors_instr, - nir_metadata_block_index | - nir_metadata_dominance, - (void *)&ctx) | - nir_shader_instructions_pass(nir, lower_ssbo_descriptor_instr, - nir_metadata_block_index | - nir_metadata_dominance, - (void *)&ctx); + bool pass_lower_descriptors = + nir_shader_instructions_pass(nir, try_lower_descriptors_instr, + nir_metadata_block_index | + nir_metadata_dominance, + (void *)&ctx); + bool pass_lower_ssbo = + nir_shader_instructions_pass(nir, lower_ssbo_descriptor_instr, + nir_metadata_block_index | + nir_metadata_dominance, + (void *)&ctx); + return pass_lower_descriptors || pass_lower_ssbo; } diff --git a/src/panfrost/ci/traces-panfrost.yml b/src/panfrost/ci/traces-panfrost.yml index 02125b98cb6..c14f25d6354 100644 --- a/src/panfrost/ci/traces-panfrost.yml +++ b/src/panfrost/ci/traces-panfrost.yml @@ -122,11 +122,6 @@ traces: label: [unsupported] gl-panfrost-t860: label: [unsupported] - freedoom/freedoom-phase2-gl-high.trace: - gl-panfrost-t760: - label: [unsupported] - gl-panfrost-t860: - label: [unsupported] unvanquished/unvanquished-lowest.trace: gl-panfrost-t760: label: [unsupported] diff --git a/src/panfrost/lib/pan_texture.c b/src/panfrost/lib/pan_texture.c index 31240832deb..66e6a4f5e7c 100644 --- a/src/panfrost/lib/pan_texture.c +++ b/src/panfrost/lib/pan_texture.c @@ -540,15 +540,8 @@ panfrost_emit_surface(const struct pan_image_view *iview, unsigned level, unsigned layer, unsigned face, unsigned sample, enum pipe_format format, void **payload) { - const struct pan_image *base_image = pan_image_view_get_plane(iview, 0); ASSERTED const struct util_format_description *desc = util_format_description(format); - mali_ptr base = base_image->data.bo->ptr.gpu + base_image->data.offset; - - if (iview->buf.size) { - assert(iview->dim == MALI_TEXTURE_DIMENSION_1D); - base += iview->buf.offset; - } const struct pan_image_layout *layouts[MAX_IMAGE_PLANES] = {0}; mali_ptr plane_ptrs[MAX_IMAGE_PLANES] = {0}; @@ -556,12 +549,21 @@ panfrost_emit_surface(const struct pan_image_view *iview, unsigned level, int32_t surface_strides[MAX_IMAGE_PLANES] = {0}; for (int i = 0; i < MAX_IMAGE_PLANES; i++) { - if (!pan_image_view_get_plane(iview, i)) { + const struct pan_image *base_image = pan_image_view_get_plane(iview, i); + + if (!base_image) { /* Every texture should have at least one plane. */ assert(i > 0); break; } + mali_ptr base = base_image->data.bo->ptr.gpu + base_image->data.offset; + + if (iview->buf.size) { + assert(iview->dim == MALI_TEXTURE_DIMENSION_1D); + base += iview->buf.offset; + } + layouts[i] = &pan_image_view_get_plane(iview, i)->layout; /* v4 does not support compression */ @@ -742,6 +744,11 @@ GENX(panfrost_new_texture)(const struct panfrost_device *dev, array_size /= 6; } + /* Multiplanar YUV textures require 2 surface descriptors. */ + if (panfrost_is_yuv(desc->layout) && PAN_ARCH >= 9 && + pan_image_view_get_plane(iview, 1) != NULL) + array_size *= 2; + unsigned width; if (iview->buf.size) { diff --git a/src/util/00-mesa-defaults.conf b/src/util/00-mesa-defaults.conf index 6af8e5c4e3f..9e9fbb89913 100644 --- a/src/util/00-mesa-defaults.conf +++ b/src/util/00-mesa-defaults.conf @@ -837,6 +837,13 @@ TODO: document the other workarounds.