@@ -60,22 +60,39 @@ static int valid_pin(const mcu_pin_obj_t *pin, qstr name) {
6060 return result ;
6161}
6262
63- void common_hal_dotclockframebuffer_framebuffer_construct (dotclockframebuffer_framebuffer_obj_t * self ,
64- const mcu_pin_obj_t * de ,
65- const mcu_pin_obj_t * vsync ,
66- const mcu_pin_obj_t * hsync ,
67- const mcu_pin_obj_t * dclk ,
68- const mcu_pin_obj_t * * red , uint8_t num_red ,
69- const mcu_pin_obj_t * * green , uint8_t num_green ,
70- const mcu_pin_obj_t * * blue , uint8_t num_blue ,
71- int frequency , int width , int height ,
72- int hsync_pulse_width , int hsync_back_porch , int hsync_front_porch , bool hsync_idle_low ,
73- int vsync_pulse_width , int vsync_back_porch , int vsync_front_porch , bool vsync_idle_low ,
74- bool de_idle_high , bool pclk_active_high , bool pclk_idle_high , int overscan_left ) {
75-
76- if (num_red != 5 || num_green != 6 || num_blue != 5 ) {
77- mp_raise_ValueError (MP_ERROR_TEXT ("Must provide 5/6/5 RGB pins" ));
63+ static void allocate_gpio_range (
64+ const mcu_pin_obj_t * * pins ,
65+ const int num_pins ,
66+ const int expected_pins ,
67+ esp_lcd_rgb_panel_config_t * cfg ,
68+ int * gpio_num ,
69+ qstr pin_group_name
70+ )
71+ {
72+ for (int i = 0 ; i < expected_pins ; i ++ , (* gpio_num )++ ) {
73+ cfg -> data_gpio_nums [* gpio_num ] = (i < num_pins ? valid_pin (pins [i ], pin_group_name ) : GPIO_NUM_NC );
7874 }
75+ }
76+
77+ void common_hal_dotclockframebuffer_framebuffer_construct (dotclockframebuffer_framebuffer_obj_t * self ,
78+ const mcu_pin_obj_t * de ,
79+ const mcu_pin_obj_t * vsync ,
80+ const mcu_pin_obj_t * hsync ,
81+ const mcu_pin_obj_t * dclk ,
82+ const mcu_pin_obj_t * * red , uint8_t num_red ,
83+ const mcu_pin_obj_t * * green , uint8_t num_green ,
84+ const mcu_pin_obj_t * * blue , uint8_t num_blue ,
85+ int frequency , int width , int height ,
86+ int hsync_pulse_width , int hsync_back_porch , int hsync_front_porch , bool hsync_idle_low ,
87+ int vsync_pulse_width , int vsync_back_porch , int vsync_front_porch , bool vsync_idle_low ,
88+ bool de_idle_high , bool pclk_active_high , bool pclk_idle_high , int overscan_left ) {
89+
90+ const int expected_red = 5 ;
91+ const int expected_green = 6 ;
92+ const int expected_blue = 5 ;
93+ // if (num_red != 5 || num_green != 6 || num_blue != 5) {
94+ // mp_raise_ValueError(MP_ERROR_TEXT("Must provide 5/6/5 RGB pins"));
95+ // }
7996
8097 claim_and_record (de , & self -> used_pins_mask );
8198 claim_and_record (vsync , & self -> used_pins_mask );
@@ -117,24 +134,28 @@ void common_hal_dotclockframebuffer_framebuffer_construct(dotclockframebuffer_fr
117134 cfg -> pclk_gpio_num = valid_pin (dclk , MP_QSTR_dclk );
118135 cfg -> clk_src = LCD_CLK_SRC_DEFAULT ;
119136
120- cfg -> data_gpio_nums [0 ] = valid_pin (blue [0 ], MP_QSTR_blue );
121- cfg -> data_gpio_nums [1 ] = valid_pin (blue [1 ], MP_QSTR_blue );
122- cfg -> data_gpio_nums [2 ] = valid_pin (blue [2 ], MP_QSTR_blue );
123- cfg -> data_gpio_nums [3 ] = valid_pin (blue [3 ], MP_QSTR_blue );
124- cfg -> data_gpio_nums [4 ] = valid_pin (blue [4 ], MP_QSTR_blue );
125-
126- cfg -> data_gpio_nums [5 ] = valid_pin (green [0 ], MP_QSTR_green );
127- cfg -> data_gpio_nums [6 ] = valid_pin (green [1 ], MP_QSTR_green );
128- cfg -> data_gpio_nums [7 ] = valid_pin (green [2 ], MP_QSTR_green );
129- cfg -> data_gpio_nums [8 ] = valid_pin (green [3 ], MP_QSTR_green );
130- cfg -> data_gpio_nums [9 ] = valid_pin (green [4 ], MP_QSTR_green );
131- cfg -> data_gpio_nums [10 ] = valid_pin (green [5 ], MP_QSTR_green );
132-
133- cfg -> data_gpio_nums [11 ] = valid_pin (red [0 ], MP_QSTR_red );
134- cfg -> data_gpio_nums [12 ] = valid_pin (red [1 ], MP_QSTR_red );
135- cfg -> data_gpio_nums [13 ] = valid_pin (red [2 ], MP_QSTR_red );
136- cfg -> data_gpio_nums [14 ] = valid_pin (red [3 ], MP_QSTR_red );
137- cfg -> data_gpio_nums [15 ] = valid_pin (red [4 ], MP_QSTR_red );
137+ int gpio_num = 0 ;
138+ allocate_gpio_range (blue , num_blue , expected_blue , cfg , & gpio_num , MP_QSTR_blue );
139+ // cfg->data_gpio_nums[0] = valid_pin(blue[0], MP_QSTR_blue);
140+ // cfg->data_gpio_nums[1] = valid_pin(blue[1], MP_QSTR_blue);
141+ // cfg->data_gpio_nums[2] = valid_pin(blue[2], MP_QSTR_blue);
142+ // cfg->data_gpio_nums[3] = valid_pin(blue[3], MP_QSTR_blue);
143+ // cfg->data_gpio_nums[4] = valid_pin(blue[4], MP_QSTR_blue);
144+
145+ allocate_gpio_range (green , num_green , expected_green , cfg , & gpio_num , MP_QSTR_green );
146+ // cfg->data_gpio_nums[5] = valid_pin(green[0], MP_QSTR_green);
147+ // cfg->data_gpio_nums[6] = valid_pin(green[1], MP_QSTR_green);
148+ // cfg->data_gpio_nums[7] = valid_pin(green[2], MP_QSTR_green);
149+ // cfg->data_gpio_nums[8] = valid_pin(green[3], MP_QSTR_green);
150+ // cfg->data_gpio_nums[9] = valid_pin(green[4], MP_QSTR_green);
151+ // cfg->data_gpio_nums[10] = valid_pin(green[5], MP_QSTR_green);
152+
153+ allocate_gpio_range (red , num_red , expected_red , cfg , & gpio_num , MP_QSTR_red );
154+ // cfg->data_gpio_nums[11] = valid_pin(red[0], MP_QSTR_red);
155+ // cfg->data_gpio_nums[12] = valid_pin(red[1], MP_QSTR_red);
156+ // cfg->data_gpio_nums[13] = valid_pin(red[2], MP_QSTR_red);
157+ // cfg->data_gpio_nums[14] = valid_pin(red[3], MP_QSTR_red);
158+ // cfg->data_gpio_nums[15] = valid_pin(red[4], MP_QSTR_red);
138159
139160 cfg -> disp_gpio_num = GPIO_NUM_NC ;
140161
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