Skip to content

Commit b3c0a64

Browse files
orangecmsorangecms
committed
draft chapters on SoC and peripherals
Signed-off-by: Daniel Maslowski <[email protected]>
1 parent 67b127d commit b3c0a64

File tree

6 files changed

+100
-10
lines changed

6 files changed

+100
-10
lines changed

‎src/SUMMARY.md‎

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,7 @@
1-
[PSI Spec Introduction](intro.md)
2-
[Mask ROMs and Loaders](mask-roms-loaders.md)
3-
[Platform Initialization](platform-initialization.md)
4-
[Boot Environments](boot-environments.md)
5-
[Platform Security](platform-security.md)
1+
- [PSI Spec Introduction](intro.md)
2+
* [Application Processors](application-processors.md)
3+
* [Peripherals](peripherals.md)
4+
- [Mask ROMs and Loaders](mask-roms-loaders.md)
5+
- [Platform Initialization](platform-initialization.md)
6+
- [Boot Environments](boot-environments.md)
7+
- [Platform Security](platform-security.md)

‎src/application-processors.md‎

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,22 @@
1+
## Application Processors
2+
3+
An _Application Processor_ (AP) is the main processing unit of a system,
4+
commonly designed as a _System on Chip_ (SoC). APs are sometimes also considered
5+
microprocessors, as opposed to microcontrollers. Another regularly used term is
6+
_Central Processing Unit_ (CPU). While design approaches and names have changed
7+
over the years, psi-spec is concerned with the kind of processors that feature a
8+
_Memory Management Unit_ (MMU) and DRAM, allowing for many concurrent tasks and
9+
processing large amounts of data.
10+
11+
### System on Chip
12+
13+
An SoC integrates application processing units with [peripherals](./peripherals)
14+
via internal system buses, all packaged into one chip. Common buses are defined
15+
by the [AMBA](https://developer.arm.com/Architectures/AMBA) standards and the
16+
[WISHBONE Interconnect Architecture](https://opencores.org/howto/wishbone). Some
17+
vendors have their own designs, such as AMD's [Infinity Fabric](
18+
https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/other/56978.pdf).
19+
A bus is generally a set of physical interfaces and corresponding protocols.
20+
Parts of an SoC are called blocks.
21+
22+
![logical view of a simple SoC](images/simple-soc.png)

‎src/images/simple-soc.drawio‎

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,60 @@
1+
<mxfile host="Electron" agent="Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/537.36 (KHTML, like Gecko) draw.io/26.0.4 Chrome/128.0.6613.186 Electron/32.2.5 Safari/537.36" version="26.0.4">
2+
<diagram id="Y_t08EuvB3_94yiSf32u" name="Page-1">
3+
<mxGraphModel dx="1144" dy="686" grid="1" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="1" pageScale="1" pageWidth="600" pageHeight="400" math="0" shadow="0">
4+
<root>
5+
<mxCell id="0" />
6+
<mxCell id="1" parent="0" />
7+
<mxCell id="z8LfdM-xd5_OOajsD7mN-11" value="" style="rounded=0;whiteSpace=wrap;html=1;fontColor=#FFB366;" parent="1" vertex="1">
8+
<mxGeometry x="40" y="150" width="260" height="230" as="geometry" />
9+
</mxCell>
10+
<mxCell id="z8LfdM-xd5_OOajsD7mN-1" value="" style="shape=flexArrow;endArrow=classic;startArrow=classic;html=1;rounded=0;" parent="1" edge="1">
11+
<mxGeometry width="100" height="100" relative="1" as="geometry">
12+
<mxPoint x="290" y="266" as="sourcePoint" />
13+
<mxPoint x="50" y="266" as="targetPoint" />
14+
</mxGeometry>
15+
</mxCell>
16+
<mxCell id="z8LfdM-xd5_OOajsD7mN-10" value="System Bus" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];fontColor=#FFB366;" parent="z8LfdM-xd5_OOajsD7mN-1" vertex="1" connectable="0">
17+
<mxGeometry x="0.0314" y="3" relative="1" as="geometry">
18+
<mxPoint y="-16" as="offset" />
19+
</mxGeometry>
20+
</mxCell>
21+
<mxCell id="z8LfdM-xd5_OOajsD7mN-2" value="AP" style="rounded=0;whiteSpace=wrap;html=1;" parent="1" vertex="1">
22+
<mxGeometry x="73" y="161" width="70" height="60" as="geometry" />
23+
</mxCell>
24+
<mxCell id="z8LfdM-xd5_OOajsD7mN-3" value="SRAM" style="rounded=0;whiteSpace=wrap;html=1;" parent="1" vertex="1">
25+
<mxGeometry x="187" y="161" width="70" height="60" as="geometry" />
26+
</mxCell>
27+
<mxCell id="z8LfdM-xd5_OOajsD7mN-4" value="ROM" style="rounded=0;whiteSpace=wrap;html=1;" parent="1" vertex="1">
28+
<mxGeometry x="86" y="311" width="70" height="60" as="geometry" />
29+
</mxCell>
30+
<mxCell id="z8LfdM-xd5_OOajsD7mN-5" value="UART" style="rounded=0;whiteSpace=wrap;html=1;" parent="1" vertex="1">
31+
<mxGeometry x="197" y="311" width="70" height="60" as="geometry" />
32+
</mxCell>
33+
<mxCell id="z8LfdM-xd5_OOajsD7mN-6" value="" style="shape=flexArrow;endArrow=classic;startArrow=classic;html=1;rounded=0;endWidth=4.11764705882353;endSize=2.6323529411764706;startWidth=4.11764705882353;startSize=2.6323529411764706;width=5.7560975609756095;" parent="1" edge="1">
34+
<mxGeometry width="100" height="100" relative="1" as="geometry">
35+
<mxPoint x="224" y="260" as="sourcePoint" />
36+
<mxPoint x="224" y="222" as="targetPoint" />
37+
</mxGeometry>
38+
</mxCell>
39+
<mxCell id="z8LfdM-xd5_OOajsD7mN-7" value="" style="shape=flexArrow;endArrow=classic;startArrow=classic;html=1;rounded=0;endWidth=4.11764705882353;endSize=2.6323529411764706;startWidth=4.11764705882353;startSize=2.6323529411764706;width=5.7560975609756095;" parent="1" edge="1">
40+
<mxGeometry width="100" height="100" relative="1" as="geometry">
41+
<mxPoint x="233" y="310" as="sourcePoint" />
42+
<mxPoint x="233" y="272" as="targetPoint" />
43+
</mxGeometry>
44+
</mxCell>
45+
<mxCell id="z8LfdM-xd5_OOajsD7mN-8" value="" style="shape=flexArrow;endArrow=classic;startArrow=classic;html=1;rounded=0;endWidth=4.11764705882353;endSize=2.6323529411764706;startWidth=4.11764705882353;startSize=2.6323529411764706;width=5.7560975609756095;" parent="1" edge="1">
46+
<mxGeometry width="100" height="100" relative="1" as="geometry">
47+
<mxPoint x="121" y="310" as="sourcePoint" />
48+
<mxPoint x="121" y="272" as="targetPoint" />
49+
</mxGeometry>
50+
</mxCell>
51+
<mxCell id="z8LfdM-xd5_OOajsD7mN-9" value="" style="shape=flexArrow;endArrow=classic;startArrow=classic;html=1;rounded=0;endWidth=4.11764705882353;endSize=2.6323529411764706;startWidth=4.11764705882353;startSize=2.6323529411764706;width=5.7560975609756095;" parent="1" edge="1">
52+
<mxGeometry width="100" height="100" relative="1" as="geometry">
53+
<mxPoint x="110" y="260" as="sourcePoint" />
54+
<mxPoint x="110" y="222" as="targetPoint" />
55+
</mxGeometry>
56+
</mxCell>
57+
</root>
58+
</mxGraphModel>
59+
</diagram>
60+
</mxfile>

‎src/images/simple-soc.png‎

22.5 KB
Loading

‎src/intro.md‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,11 @@
55
The Platform System Interface Specification, or _psi-spec_, is
66
a collection of documents for [hardware and software co-design](
77
#) from a general perspective.
8-
It describes how microprocessors can provide an [environment for booting](
9-
boot-environments.md) an operating system or otherwise bare-metal applications,
10-
typically starting from intermediate, rewritable code that initializes clocks,
11-
DRAM and peripherals, commonly referred to as boot firmware or [platform
12-
initialization firmware](platform-initialization.md).
8+
It describes how [microprocessors](./application-processors) provide an
9+
[environment for booting](boot-environments.md) operating systems or otherwise
10+
bare-metal applications, typically starting from intermediate, rewritable code
11+
that initializes clocks, DRAM and peripherals, commonly referred to as boot
12+
firmware or [platform initialization firmware](platform-initialization.md).
1313

1414
In the following sections, _psi-spec_ describes principles and
1515
abstractions that apply agnostic of vendors and products.

‎src/peripherals.md‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
## Peripherals
2+
3+
Systems connect with external hardware components, also known as _peripherals_,
4+
using buses and controllers. A controller is a unit driving a bus, such as the
5+
high-speed USB and PCIe buses or the slower SPI and I2C. Hardware platforms may
6+
integrate controllers directly or chain them through adapters and expansions.

0 commit comments

Comments
 (0)