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1 change: 1 addition & 0 deletions include/sta/Sdc.hh
Original file line number Diff line number Diff line change
Expand Up @@ -1115,6 +1115,7 @@ protected:
void recordMergeHash(ExceptionPath *exception, ExceptionPt *missing_pt);
void recordMergeHashes(ExceptionPath *exception);
void unrecordExceptionFirstPts(ExceptionPath *exception);
void unrecordExceptionPins(ExceptionPath *exception);
void unrecordExceptionClks(ExceptionPath *exception,
ClockSet *clks,
ClockExceptionsMap &exception_map);
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17 changes: 17 additions & 0 deletions sdc/Sdc.cc
Original file line number Diff line number Diff line change
Expand Up @@ -4964,6 +4964,7 @@ Sdc::unrecordException(ExceptionPath *exception)
{
unrecordMergeHashes(exception);
unrecordExceptionFirstPts(exception);
unrecordExceptionPins(exception);
exceptions_.erase(exception);
}

Expand Down Expand Up @@ -5022,6 +5023,22 @@ Sdc::unrecordExceptionFirstPts(ExceptionPath *exception)
}
}

void
Sdc::unrecordExceptionPins(ExceptionPath *exception)
{
ExceptionFrom *from = exception->from();
if (from)
unrecordExceptionPins(exception, from->pins(), pin_exceptions_);
ExceptionThruSeq *thrus = exception->thrus();
if (thrus) {
for (ExceptionThru *thru : *thrus)
unrecordExceptionPins(exception, thru->pins(), pin_exceptions_);
}
ExceptionTo *to = exception->to();
if (to)
unrecordExceptionPins(exception, to->pins(), pin_exceptions_);
}

void
Sdc::unrecordExceptionClks(ExceptionPath *exception,
ClockSet *clks,
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17 changes: 17 additions & 0 deletions test/disconnect_pin_with_sdc.ok
Original file line number Diff line number Diff line change
@@ -0,0 +1,17 @@
Warning: asap7_simple.lib.gz line 71029, timing group from output port.
Warning: asap7_simple.lib.gz line 71505, timing group from output port.
Warning: asap7_simple.lib.gz line 71981, timing group from output port.
Warning: asap7_simple.lib.gz line 72457, timing group from output port.
Warning: asap7_simple.lib.gz line 72933, timing group from output port.
Warning: asap7_simple.lib.gz line 73409, timing group from output port.
Warning: asap7_simple.lib.gz line 73885, timing group from output port.
Warning: asap7_simple.lib.gz line 81795, timing group from output port.
Warning: asap7_simple.lib.gz line 82271, timing group from output port.
Warning: asap7_simple.lib.gz line 82747, timing group from output port.
set_multicycle_path on pins
Warning: disconnect_pin_with_sdc.tcl line 17, 'u0/buf0/A' is not a valid endpoint.
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pick a pin that is legal

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This is a key part. I revised the test case to represent anchor buffers on a source-synchronous interface.
In a source-synchronous interface, clock and signals are transferred from asynchronous domain, and the skew b/w clock and data signals should be managed.
To manage this, the problematic design defines the SDC as in this test case.

Warning: disconnect_pin_with_sdc.tcl line 18, 'u0/buf1/A' is not a valid endpoint.
Warning: disconnect_pin_with_sdc.tcl line 19, 'u0/buf2/A' is not a valid endpoint.
Warning: disconnect_pin_with_sdc.tcl line 20, 'u0/buf3/A' is not a valid endpoint.
disconnect the pin w/ SDC
Pass
21 changes: 21 additions & 0 deletions test/disconnect_pin_with_sdc.tcl
Original file line number Diff line number Diff line change
@@ -0,0 +1,21 @@
# disconnect_pin call for a pin where SDC is defined
read_liberty asap7_small.lib.gz
read_verilog disconnect_pin_with_sdc.v
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use reg1_asap7.v and asap7_small.lib.gz instead of expanding the required netlists

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Used asap7_small.lib.gz.
I changed the netlist.

link_design top

create_clock -name clk -period 500 clk

# This SDC defines setup and hold time requirements for data pins
# relative to a clock, typical for a source-synchronous interface.
set_data_check -from clk -to [get_pins u0/A] -setup 10
set_data_check -from clk -to [get_pins u0/A] -hold 10
set_data_check -from clk -to [get_pins u1/A] -setup 10
set_data_check -from clk -to [get_pins u1/A] -hold 10
set_multicycle_path -end -setup 1 -to [get_pins u0/A]
set_multicycle_path -end -setup 1 -to [get_pins u1/A]
set_multicycle_path -start -hold 0 -to [get_pins u0/A]
set_multicycle_path -start -hold 0 -to [get_pins u1/A]

set in_pin [get_pins u1/A]
set in_net [get_net -of $in_pin]
disconnect_pin $in_net $in_pin
11 changes: 11 additions & 0 deletions test/disconnect_pin_with_sdc.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,11 @@
module top (clk, clkout, data_in, data_out);
input clk;
output clkout;
input [1:0] data_in;
output [1:0] data_out;

// Anchor buffers on the source-synchronous interface IOs
BUFx2_ASAP7_75t_R clkbuf0 (.A(clk), .Y(clkout));
BUFx2_ASAP7_75t_R u0 (.A(data_in[0]), .Y(data_out[0]));
BUFx2_ASAP7_75t_R u1 (.A(data_in[1]), .Y(data_out[1]));
endmodule // top
1 change: 1 addition & 0 deletions test/regression_vars.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -138,6 +138,7 @@ record_example_tests {
}

record_sta_tests {
disconnect_pin_with_sdc
get_filter
get_is_memory
get_lib_pins_of_objects
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