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nathanaelhuffmannathanaelhuffman
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pmbus sequencer alerts (#411)
We bring a bunch of alert signals from on-board sm/pmbus regulators into the interrupt block on cosmo so hubris can choose to get real interrupts (or poll the live status) on these. We also turn them to be active high in the IFR register since that matches other interrupt sources.
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7 files changed

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‎hdl/projects/cosmo_seq/cosmo_seq_top.vhd‎

Lines changed: 22 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -391,6 +391,7 @@ architecture rtl of cosmo_seq_top is
391391
signal uart_dbg_if : uart_dbg_t;
392392
signal allow_backplane_pcie_clk : std_logic;
393393
signal nic_dbg_pins : t6_debug_if;
394+
signal reg_alert_l_pins : seq_power_alert_pins_t;
394395

395396
begin
396397

@@ -639,7 +640,8 @@ begin
639640
nic_dbg_pins => nic_dbg_pins,
640641
sp5_t6_perst_l => sp5_t6_perst_l,
641642
ignition_mux_sel => fpga1_to_sp_mux_ign_mux_sel,
642-
ignition_creset => fpga1_to_ign_trgt_fpga_creset
643+
ignition_creset => fpga1_to_ign_trgt_fpga_creset,
644+
reg_alert_l_pins => reg_alert_l_pins
643645
);
644646

645647
-- early power related pins
@@ -729,7 +731,26 @@ begin
729731
dimm_ghijkl_scl_if.i <= i3c_fpga1_to_dimm_ghijkl_scl;
730732
i3c_fpga1_to_dimm_ghijkl_sda <= dimm_ghijkl_sda_if.o when dimm_ghijkl_sda_if.oe else 'Z';
731733
dimm_ghijkl_sda_if.i <= i3c_fpga1_to_dimm_ghijkl_sda;
734+
732735

736+
reg_alert_l_pins.smbus_fan_central_hsc_to_fpga1_alert_l <= smbus_fan_central_hsc_to_fpga1_alert_l;
737+
reg_alert_l_pins.smbus_fan_east_hsc_to_fpga1_alert_l <= smbus_fan_east_hsc_to_fpga1_alert_l;
738+
reg_alert_l_pins.smbus_fan_west_hsc_to_fpga1_alert_l <= smbus_fan_west_hsc_to_fpga1_alert_l;
739+
reg_alert_l_pins.smbus_ibc_to_fpga1_alert_l <= smbus_ibc_to_fpga1_alert_l;
740+
reg_alert_l_pins.smbus_m2_hsc_to_fpga1_alert_l <= smbus_m2_hsc_to_fpga1_alert_l;
741+
reg_alert_l_pins.smbus_nic_hsc_to_fpga1_alert_l <= smbus_nic_hsc_to_fpga1_alert_l;
742+
reg_alert_l_pins.smbus_v12_ddr5_abcdef_hsc_to_fpga1_alert <= smbus_v12_ddr5_abcdef_hsc_to_fpga1_alert;
743+
reg_alert_l_pins.smbus_v12_ddr5_ghijkl_hsc_to_fpga1_alert <= smbus_v12_ddr5_ghijkl_hsc_to_fpga1_alert;
744+
reg_alert_l_pins.smbus_v12_mcio_a0hp_hsc_to_fpga1_alert_l <= smbus_v12_mcio_a0hp_hsc_to_fpga1_alert_l;
745+
reg_alert_l_pins.main_hsc_to_fpga1_alert_l <= main_hsc_to_fpga1_alert_l;
746+
reg_alert_l_pins.vr_v1p8_sys_to_fpga1_alert_l <= vr_v1p8_sys_to_fpga1_alert_l;
747+
reg_alert_l_pins.vr_v3p3_sys_to_fpga1_alert_l <= vr_v3p3_sys_to_fpga1_alert_l;
748+
reg_alert_l_pins.vr_v5p0_sys_to_fpga1_alert_l <= vr_v5p0_sys_to_fpga1_alert_l;
749+
reg_alert_l_pins.pwr_cont1_to_fpga1_alert_l <= pwr_cont1_to_fpga1_alert_l;
750+
reg_alert_l_pins.v0p96_nic_to_fpga1_alert_l <= v0p96_nic_to_fpga1_alert_l;
751+
reg_alert_l_pins.pwr_cont2_to_fpga1_alert_l <= pwr_cont2_to_fpga1_alert_l;
752+
reg_alert_l_pins.pwr_cont3_to_fpga1_alert_l <= pwr_cont3_to_fpga1_alert_l;
753+
733754
dimm_spd_proxy_top_inst: entity work.dimms_subsystem_top
734755
generic map(
735756
CLK_PER_NS => 8,

‎hdl/projects/cosmo_seq/sequencer/seq_sync.vhd‎

Lines changed: 112 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@ entity seq_sync is
2424
sp5_seq_pins : view sp5_seq_at_fpga;
2525
nic_rails_pins : view nic_power_at_fpga;
2626
nic_seq_pins: view nic_seq_at_fpga;
27+
reg_alert_l_pins : view power_alert_at_fpga;
2728
-- internal, synchronized interfaces
2829
early_power : view early_power_on_board;
2930
ddr_bulk: view ddr_bulk_at_reg;
@@ -32,7 +33,8 @@ entity seq_sync is
3233
group_c : view group_c_power_at_reg;
3334
sp5_seq : view sp5_seq_at_sp5;
3435
nic_rails : view nic_power_at_reg;
35-
nic_seq: view nic_seq_at_nic
36+
nic_seq: view nic_seq_at_nic;
37+
reg_alert_l : view power_alert_at_reg;
3638
);
3739
end entity;
3840

@@ -271,4 +273,113 @@ begin
271273
sycnd_output => nic_seq.sp5_mfg_mode_l
272274
);
273275

276+
-- Alert sync stuff
277+
278+
279+
smbus_fan_central_hsc_to_fpga1_alert_l_sync: entity work.meta_sync
280+
port map(
281+
async_input => reg_alert_l_pins.smbus_fan_central_hsc_to_fpga1_alert_l,
282+
clk => clk,
283+
sycnd_output => reg_alert_l.smbus_fan_central_hsc_to_fpga1_alert_l
284+
);
285+
smbus_fan_east_hsc_to_fpga1_alert_l_sync: entity work.meta_sync
286+
port map(
287+
async_input => reg_alert_l_pins.smbus_fan_east_hsc_to_fpga1_alert_l,
288+
clk => clk,
289+
sycnd_output => reg_alert_l.smbus_fan_east_hsc_to_fpga1_alert_l
290+
);
291+
smbus_fan_west_hsc_to_fpga1_alert_l_sync: entity work.meta_sync
292+
port map(
293+
async_input => reg_alert_l_pins.smbus_fan_west_hsc_to_fpga1_alert_l,
294+
clk => clk,
295+
sycnd_output => reg_alert_l.smbus_fan_west_hsc_to_fpga1_alert_l
296+
);
297+
smbus_ibc_to_fpga1_alert_l_sync: entity work.meta_sync
298+
port map(
299+
async_input => reg_alert_l_pins.smbus_ibc_to_fpga1_alert_l,
300+
clk => clk,
301+
sycnd_output => reg_alert_l.smbus_ibc_to_fpga1_alert_l
302+
);
303+
smbus_m2_hsc_to_fpga1_alert_l_sync: entity work.meta_sync
304+
port map(
305+
async_input => reg_alert_l_pins.smbus_m2_hsc_to_fpga1_alert_l,
306+
clk => clk,
307+
sycnd_output => reg_alert_l.smbus_m2_hsc_to_fpga1_alert_l
308+
);
309+
smbus_nic_hsc_to_fpga1_alert_l_sync: entity work.meta_sync
310+
port map(
311+
async_input => reg_alert_l_pins.smbus_nic_hsc_to_fpga1_alert_l,
312+
clk => clk,
313+
sycnd_output => reg_alert_l.smbus_nic_hsc_to_fpga1_alert_l
314+
);
315+
smbus_v12_ddr5_abcdef_hsc_to_fpga1_alert_sync: entity work.meta_sync
316+
port map(
317+
async_input => reg_alert_l_pins.smbus_v12_ddr5_abcdef_hsc_to_fpga1_alert,
318+
clk => clk,
319+
sycnd_output => reg_alert_l.smbus_v12_ddr5_abcdef_hsc_to_fpga1_alert
320+
);
321+
322+
smbus_v12_ddr5_ghijkl_hsc_to_fpga1_alert_sync: entity work.meta_sync
323+
port map(
324+
async_input => reg_alert_l_pins.smbus_v12_ddr5_ghijkl_hsc_to_fpga1_alert,
325+
clk => clk,
326+
sycnd_output => reg_alert_l.smbus_v12_ddr5_ghijkl_hsc_to_fpga1_alert
327+
);
328+
smbus_v12_mcio_a0hp_hsc_to_fpga1_alert_l_sync: entity work.meta_sync
329+
port map(
330+
async_input => reg_alert_l_pins.smbus_v12_mcio_a0hp_hsc_to_fpga1_alert_l,
331+
clk => clk,
332+
sycnd_output => reg_alert_l.smbus_v12_mcio_a0hp_hsc_to_fpga1_alert_l
333+
);
334+
main_hsc_to_fpga1_alert_l_sync: entity work.meta_sync
335+
port map(
336+
async_input => reg_alert_l_pins.main_hsc_to_fpga1_alert_l,
337+
clk => clk,
338+
sycnd_output => reg_alert_l.main_hsc_to_fpga1_alert_l
339+
);
340+
vr_v1p8_sys_to_fpga1_alert_l_sync: entity work.meta_sync
341+
port map(
342+
async_input => reg_alert_l_pins.vr_v1p8_sys_to_fpga1_alert_l,
343+
clk => clk,
344+
sycnd_output => reg_alert_l.vr_v1p8_sys_to_fpga1_alert_l
345+
);
346+
vr_v3p3_sys_to_fpga1_alert_l_sync: entity work.meta_sync
347+
port map(
348+
async_input => reg_alert_l_pins.vr_v3p3_sys_to_fpga1_alert_l,
349+
clk => clk,
350+
sycnd_output => reg_alert_l.vr_v3p3_sys_to_fpga1_alert_l
351+
);
352+
vr_v5p0_sys_to_fpga1_alert_l_sync: entity work.meta_sync
353+
port map(
354+
async_input => reg_alert_l_pins.vr_v5p0_sys_to_fpga1_alert_l,
355+
clk => clk,
356+
sycnd_output => reg_alert_l.vr_v5p0_sys_to_fpga1_alert_l
357+
);
358+
359+
pwr_cont1_to_fpga1_alert_l_sync: entity work.meta_sync
360+
port map(
361+
async_input => reg_alert_l_pins.pwr_cont1_to_fpga1_alert_l,
362+
clk => clk,
363+
sycnd_output => reg_alert_l.pwr_cont1_to_fpga1_alert_l
364+
);
365+
v0p96_nic_to_fpga1_alert_l_sync: entity work.meta_sync
366+
port map(
367+
async_input => reg_alert_l_pins.v0p96_nic_to_fpga1_alert_l,
368+
clk => clk,
369+
sycnd_output => reg_alert_l.v0p96_nic_to_fpga1_alert_l
370+
);
371+
pwr_cont2_to_fpga1_alert_l_sync: entity work.meta_sync
372+
port map(
373+
async_input => reg_alert_l_pins.pwr_cont2_to_fpga1_alert_l,
374+
clk => clk,
375+
sycnd_output => reg_alert_l.pwr_cont2_to_fpga1_alert_l
376+
);
377+
pwr_cont3_to_fpga1_alert_l_sync: entity work.meta_sync
378+
port map(
379+
async_input => reg_alert_l_pins.pwr_cont3_to_fpga1_alert_l,
380+
clk => clk,
381+
sycnd_output => reg_alert_l.pwr_cont3_to_fpga1_alert_l
382+
);
383+
384+
274385
end rtl;

‎hdl/projects/cosmo_seq/sequencer/sequencer_io_pkg.vhd‎

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -65,6 +65,46 @@ package sequencer_io_pkg is
6565
end view;
6666
alias sp5_seq_at_sp5 is sp5_seq_at_fpga'converse;
6767

68+
type seq_power_alert_pins_t is record
69+
smbus_fan_central_hsc_to_fpga1_alert_l : std_logic;
70+
smbus_fan_east_hsc_to_fpga1_alert_l : std_logic;
71+
smbus_fan_west_hsc_to_fpga1_alert_l : std_logic;
72+
smbus_ibc_to_fpga1_alert_l : std_logic;
73+
smbus_m2_hsc_to_fpga1_alert_l : std_logic;
74+
smbus_nic_hsc_to_fpga1_alert_l : std_logic;
75+
smbus_v12_ddr5_abcdef_hsc_to_fpga1_alert : std_logic;
76+
smbus_v12_ddr5_ghijkl_hsc_to_fpga1_alert : std_logic;
77+
smbus_v12_mcio_a0hp_hsc_to_fpga1_alert_l : std_logic;
78+
main_hsc_to_fpga1_alert_l : std_logic;
79+
vr_v1p8_sys_to_fpga1_alert_l : std_logic;
80+
vr_v3p3_sys_to_fpga1_alert_l : std_logic;
81+
vr_v5p0_sys_to_fpga1_alert_l : std_logic;
82+
pwr_cont1_to_fpga1_alert_l : std_logic;
83+
v0p96_nic_to_fpga1_alert_l : std_logic;
84+
pwr_cont2_to_fpga1_alert_l : std_logic;
85+
pwr_cont3_to_fpga1_alert_l : std_logic;
86+
end record;
87+
view power_alert_at_fpga of seq_power_alert_pins_t is
88+
smbus_fan_central_hsc_to_fpga1_alert_l : in;
89+
smbus_fan_east_hsc_to_fpga1_alert_l : in;
90+
smbus_fan_west_hsc_to_fpga1_alert_l : in;
91+
smbus_ibc_to_fpga1_alert_l : in;
92+
smbus_m2_hsc_to_fpga1_alert_l : in;
93+
smbus_nic_hsc_to_fpga1_alert_l : in;
94+
smbus_v12_ddr5_abcdef_hsc_to_fpga1_alert : in;
95+
smbus_v12_ddr5_ghijkl_hsc_to_fpga1_alert : in;
96+
smbus_v12_mcio_a0hp_hsc_to_fpga1_alert_l : in;
97+
main_hsc_to_fpga1_alert_l : in;
98+
vr_v1p8_sys_to_fpga1_alert_l : in;
99+
vr_v3p3_sys_to_fpga1_alert_l : in;
100+
vr_v5p0_sys_to_fpga1_alert_l : in;
101+
pwr_cont1_to_fpga1_alert_l : in;
102+
v0p96_nic_to_fpga1_alert_l : in;
103+
pwr_cont2_to_fpga1_alert_l : in;
104+
pwr_cont3_to_fpga1_alert_l : in;
105+
end view;
106+
alias power_alert_at_reg is power_alert_at_fpga'converse;
107+
68108
-- Nic sequencing-related control/feedback pins
69109
type nic_seq_pins_t is record
70110
cld_rst_l : std_logic;

‎hdl/projects/cosmo_seq/sequencer/sequencer_regs.rdl‎

Lines changed: 76 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -12,27 +12,82 @@ addrmap sequencer_regs {
1212

1313
// IRQ for faults
1414
reg irq {
15-
field {
16-
desc = "Fan Fault";
17-
} fanfault[1];
18-
field {
19-
desc = "Thermtrip- Thermal trip indicated from SP5 (sticky since fpga reset or last clear)";
20-
} thermtrip[1];
21-
field {
22-
desc = "SMERR_L asserted low while CPU was powered up";
23-
} smerr_assert[1];
24-
field {
25-
desc = "A1A0 MAPO- A fault in the A1-A0 domain(s) caused a MAPO (sticky since fpga reset or last clear)";
26-
} a0mapo[1];
27-
field {
28-
desc = "Nic MAPO- A fault in the A0 domain caused a MAPO (sticky since fpga reset or last clear)";
29-
} nicmapo[1];
30-
field {
31-
desc = "AMD PWROK falling edge while in >=A0 (sticky since fpga reset or last clear)";
32-
} amd_pwrok_fedge[1];
33-
field {
34-
desc = "AMD RESET falling edge while in >=A0 (sticky since fpga reset or last clear)";
35-
} amd_rstn_fedge[1];
15+
field {
16+
desc = "Fan Fault";
17+
} fanfault[1];
18+
field {
19+
desc = "Thermtrip- Thermal trip indicated from SP5 (sticky since fpga reset or last clear)";
20+
} thermtrip[1];
21+
field {
22+
desc = "SMERR_L asserted low while CPU was powered up";
23+
} smerr_assert[1];
24+
field {
25+
desc = "A1A0 MAPO- A fault in the A1-A0 domain(s) caused a MAPO (sticky since fpga reset or last clear)";
26+
} a0mapo[1];
27+
field {
28+
desc = "Nic MAPO- A fault in the A0 domain caused a MAPO (sticky since fpga reset or last clear)";
29+
} nicmapo[1];
30+
field {
31+
desc = "AMD PWROK falling edge while in >=A0 (sticky since fpga reset or last clear)";
32+
} amd_pwrok_fedge[1];
33+
field {
34+
desc = "AMD RESET falling edge while in >=A0 (sticky since fpga reset or last clear)";
35+
} amd_rstn_fedge[1];
36+
37+
field {
38+
desc = "Live. Set '1' when smbus_fan_central_hsc_to_fpga1_alert_l is active (low on board)";
39+
} fan_central_hsc_alert[1];
40+
field {
41+
desc = "Live. Set '1' when smbus_fan_east_hsc_to_fpga1_alert_l is active (low on board)";
42+
} fan_east_hsc_alert[1];
43+
field {
44+
desc = "Live. Set '1' when smbus_fan_west_hsc_to_fpga1_alert_l is active (low on board)";
45+
} fan_west_hsc_alert[1];
46+
field {
47+
desc = "Live. Set '1' when smbus_ibc_to_fpga1_alert_l is active (low on board)";
48+
} ibc_alert[1];
49+
field {
50+
desc = "Live. Set '1' when smbus_m2_hsc_to_fpga1_alert_l is active (low on board)";
51+
} m2_hsc_alert[1];
52+
field {
53+
desc = "Live. Set '1' when smbus_nic_hsc_to_fpga1_alert_l is active (low on board)";
54+
} nic_hsc_alert[1];
55+
field {
56+
desc = "Live. Set '1' when smbus_v12_ddr5_abcdef_hsc_to_fpga1_alert_l is active (low on board)";
57+
} v12_ddr5_abcdef_hsc_alert[1];
58+
field {
59+
desc = "Live. Set '1' when smbus_v12_ddr5_ghijkl_hsc_to_fpga1_alert_l is active (low on board)";
60+
} v12_ddr5_ghijkl_hsc_alert[1];
61+
field {
62+
desc = "Live. Set '1' when smbus_v12_mcio_a0hp_hsc_to_fpga1_alert_l is active (low on board)";
63+
} v12_mcio_a0hp_hsc_alert[1];
64+
field {
65+
desc = "Live. Set '1' when main_hsc_to_fpga1_alert_l is active (low on board)";
66+
} main_hsc_alert[1];
67+
field {
68+
desc = "Live. Set '1' when vr_v1p8_sys_to_fpga1_alert_l is active (low on board)";
69+
} vr_v1p8_sys_to_fpga1_alert[1];
70+
field {
71+
desc = "Live. Set '1' when vr_v3p3_sys_to_fpga1_alert_l is active (low on board)";
72+
} vr_v3p3_sys_to_fpga1_alert[1];
73+
field {
74+
desc = "Live. Set '1' when vr_v5p0_sys_to_fpga1_alert_l is active (low on board)";
75+
} vr_v5p0_sys_to_fpga1_alert[1];
76+
field {
77+
desc = "Live. Set '1' when v0p96_nic_to_fpga1_alert_l is active (low on board)";
78+
} v0p96_nic_to_fpga1_alert[1];
79+
field {
80+
desc = "Live. Set '1' when pwr_cont1_to_fpga1_alert_l is active (low on board).
81+
This regulator controls VDDCR_CPU0_EN and VDDCR_SOC rails.";
82+
} pwr_cont1_to_fpga1_alert[1];
83+
field {
84+
desc = "Live. Set '1' when pwr_cont2_to_fpga1_alert_l is active (low on board)
85+
This regulator controls VDDCR_CPU1_EN and VDDIO_SP5 rails.";
86+
} pwr_cont2_to_fpga1_alert[1];
87+
field {
88+
desc = "Live. Set '1' when pwr_cont3_to_fpga1_alert_l is active (low on board).
89+
This regulator controls V1P1_SP5_A0, V1P8_SP5_A0 and V3P3_SP5_A0 rails.";
90+
} pwr_cont3_to_fpga1_alert[1];
3691
};
3792
// Set up interrupt registers using a common irq_type
3893
irq IFR;

‎hdl/projects/cosmo_seq/sequencer/sequencer_regs.vhd‎

Lines changed: 23 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@ use ieee.numeric_std_unsigned.all;
1212
use work.axil_common_pkg.all;
1313
use work.axil8x32_pkg;
1414

15+
use work.sequencer_io_pkg.all;
1516
use work.sequencer_regs_pkg.all;
1617

1718
entity sequencer_regs is
@@ -44,7 +45,9 @@ entity sequencer_regs is
4445
nic_readbacks : in nic_readbacks_type;
4546
-- Ignition mux and reconfig control
4647
ignition_mux_sel : out std_logic;
47-
ignition_creset : out std_logic
48+
ignition_creset : out std_logic;
49+
-- regulator alerts
50+
reg_alert_l : in seq_power_alert_pins_t
4851

4952

5053
);
@@ -237,6 +240,25 @@ begin
237240
when others => null;
238241
end case;
239242
end if;
243+
-- These are done after the write action since they are "live" and not sticky
244+
-- so we don't allow writing to actually clear them so these will take precedence.
245+
ifr.pwr_cont3_to_fpga1_alert <= not reg_alert_l.pwr_cont3_to_fpga1_alert_l;
246+
ifr.pwr_cont2_to_fpga1_alert <= not reg_alert_l.pwr_cont2_to_fpga1_alert_l;
247+
ifr.pwr_cont1_to_fpga1_alert <= not reg_alert_l.pwr_cont1_to_fpga1_alert_l;
248+
ifr.v0p96_nic_to_fpga1_alert <= not reg_alert_l.v0p96_nic_to_fpga1_alert_l;
249+
ifr.vr_v5p0_sys_to_fpga1_alert <= not reg_alert_l.vr_v5p0_sys_to_fpga1_alert_l;
250+
ifr.vr_v3p3_sys_to_fpga1_alert <= not reg_alert_l.vr_v3p3_sys_to_fpga1_alert_l;
251+
ifr.vr_v1p8_sys_to_fpga1_alert <= not reg_alert_l.vr_v1p8_sys_to_fpga1_alert_l;
252+
ifr.main_hsc_alert <= not reg_alert_l.main_hsc_to_fpga1_alert_l;
253+
ifr.v12_mcio_a0hp_hsc_alert <= not reg_alert_l.smbus_v12_mcio_a0hp_hsc_to_fpga1_alert_l;
254+
ifr.v12_ddr5_ghijkl_hsc_alert <= not reg_alert_l.smbus_v12_ddr5_ghijkl_hsc_to_fpga1_alert;
255+
ifr.v12_ddr5_abcdef_hsc_alert <= not reg_alert_l.smbus_v12_ddr5_abcdef_hsc_to_fpga1_alert;
256+
ifr.nic_hsc_alert <= not reg_alert_l.smbus_nic_hsc_to_fpga1_alert_l;
257+
ifr.m2_hsc_alert <= not reg_alert_l.smbus_m2_hsc_to_fpga1_alert_l;
258+
ifr.ibc_alert <= not reg_alert_l.smbus_ibc_to_fpga1_alert_l;
259+
ifr.fan_west_hsc_alert <= not reg_alert_l.smbus_fan_west_hsc_to_fpga1_alert_l;
260+
ifr.fan_east_hsc_alert <= not reg_alert_l.smbus_fan_east_hsc_to_fpga1_alert_l;
261+
ifr.fan_central_hsc_alert <= not reg_alert_l.smbus_fan_central_hsc_to_fpga1_alert_l;
240262

241263
end if;
242264
end process;

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