Merge pull request #823 from os-fpga/task/EDA-3346/handle_dangling_wires

Author: ravikiranchollangi

CMakeLists.txt

@@ -17,7 +17,7 @@ set(VERSION_MINOR 0)
 
 
 
-set(VERSION_PATCH 382)
+set(VERSION_PATCH 383)
 
 
 

design_edit/src/rs_design_edit.cc

@@ -746,6 +746,7 @@ struct DesignEditRapidSilicon : public ScriptPass {
 
   void handle_dangling_outs(Module *module)
   {
+    std::unordered_set<Wire *> dangling_ins;
     for(auto cell : module->cells())
     {
       for (auto &conn : cell->connections())
@@ -831,12 +832,9 @@ struct DesignEditRapidSilicon : public ScriptPass {
           for (SigBit bit : port.second){
             if(!used_bits.count(bit) && cell->output(portName)
               && !bit.wire->port_output){
-              RTLIL::SigSig new_conn;
-              RTLIL::Wire *new_wire = module->addWire(NEW_ID, 1);
-              new_wire->port_output = true;
-              new_conn.first = new_wire;
-              new_conn.second = bit;
-              module->connect(new_conn);
+              new_ins.erase(bit.wire->name.str());
+              bit.wire->port_input = false;
+              dangling_ins.insert(bit.wire);
             }
           }
         }