From f9b2c40b742cb9b26875407628bbe87cf5d5afc9 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Sun, 20 Nov 2022 16:21:08 +0800 Subject: [PATCH 01/39] dt-bindings: serial: add bindings doc for Bouffalolab uart driver Add bindings doc for Bouffalolab UART Driver Signed-off-by: Jisheng Zhang --- .../bindings/serial/bouffalolab,uart.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml diff --git a/Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml b/Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml new file mode 100644 index 00000000000000..6cef956d33d25e --- /dev/null +++ b/Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Jisheng Zhang +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/serial/bouffalolab,uart.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Bouffalolab UART Controller + +maintainers: + - Jisheng Zhang + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + const: bouffalolab,uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + aliases { + serial0 = &uart0; + }; + + uart0: serial@30002000 { + compatible = "bouffalolab,uart"; + reg = <0x30002000 0x1000>; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&xtal>; + }; +... From 2c19a5bf97717be85036e886250502c2e35364ec Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Sun, 20 Nov 2022 16:21:11 +0800 Subject: [PATCH 02/39] riscv: add the Bouffalolab SoC family Kconfig option The Bouffalolab bl808 SoC contains three riscv CPUs, namely M0, D0 and LP. The D0 is 64bit RISC-V GC compatible, so can run linux. Signed-off-by: Jisheng Zhang --- arch/riscv/Kconfig.socs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 4b6deb2715f1c4..a68ab2172230e5 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,5 +1,11 @@ menu "SoC selection" +config SOC_BOUFFALOLAB + bool "Bouffalolab SoCs" + select SIFIVE_PLIC + help + This enables support for Bouffalolab SoC platforms. + config SOC_MICROCHIP_POLARFIRE bool "Microchip PolarFire SoCs" select MCHP_CLK_MPFS From 77c6c7a056e0e02ccd5b182bf263ea27a71cc959 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Sun, 20 Nov 2022 16:21:12 +0800 Subject: [PATCH 03/39] riscv: dts: bouffalolab: add the bl808 SoC base device tree Add a baisc dtsi for the bouffalolab bl808 SoC. Signed-off-by: Jisheng Zhang --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++++++++++++++++++++++ 2 files changed, 75 insertions(+) create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index b0ff5fbabb0c9a..2d4376810bcc75 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +subdir-y += bouffalolab subdir-y += sifive subdir-y += starfive subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi new file mode 100644 index 00000000000000..c98ebb14ee10a6 --- /dev/null +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2022 Jisheng Zhang + */ + +#include + +/ { + compatible = "bouffalolab,bl808"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + timebase-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "thead,c906", "riscv"; + device_type = "cpu"; + reg = <0>; + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <32768>; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + ranges; + interrupt-parent = <&plic>; + dma-noncoherent; + #address-cells = <1>; + #size-cells = <1>; + + uart0: serial@30002000 { + compatible = "bouffalolab,uart"; + reg = <0x30002000 0x1000>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&xtal>; + status = "disabled"; + }; + + plic: interrupt-controller@e0000000 { + compatible = "thead,c900-plic"; + reg = <0xe0000000 0x4000000>; + interrupts-extended = <&cpu0_intc 0xffffffff>, + <&cpu0_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <64>; + }; + }; +}; From cddacea7c8a17fdefacde5abd9974678e6f51058 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Sun, 20 Nov 2022 16:21:13 +0800 Subject: [PATCH 04/39] riscv: dts: bouffalolab: add Sipeed M1S dock devicetree Sipeed manufactures a M1S system-on-module and dock board, add basic support for them. Signed-off-by: Jisheng Zhang --- arch/riscv/boot/dts/bouffalolab/Makefile | 2 ++ .../boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 30 +++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 arch/riscv/boot/dts/bouffalolab/Makefile create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts diff --git a/arch/riscv/boot/dts/bouffalolab/Makefile b/arch/riscv/boot/dts/bouffalolab/Makefile new file mode 100644 index 00000000000000..42e17e1a97bd17 --- /dev/null +++ b/arch/riscv/boot/dts/bouffalolab/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_BOUFFALOLAB) += bl808-sipeed-m1s.dtb diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts new file mode 100644 index 00000000000000..64421fb2ad67d9 --- /dev/null +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2022 Jisheng Zhang + */ + +/dts-v1/; + +#include "bl808.dtsi" + +/ { + model = "Sipeed M1S"; + compatible = "sipeed,m1s", "bouffalolab,bl808"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:2000000n8"; + }; + + memory@50000000 { + device_type = "memory"; + reg = <0x50000000 0x04000000>; + }; +}; + +&uart0 { + status = "okay"; +}; From 69f07729f4f5bd7aa4a9095976a45e5dd8c9b335 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Sun, 20 Nov 2022 16:21:14 +0800 Subject: [PATCH 05/39] MAINTAINERS: add myself as Bouffalolab SoC entry maintainer I want to maintain this Bouffalolab riscv SoC entry from now on. Signed-off-by: Jisheng Zhang --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 135d93368d36ed..a8ee2a529ecb54 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17975,6 +17975,12 @@ F: arch/riscv/ N: riscv K: riscv +RISC-V BOUFFALOLAB SOC SUPPORT +M: Jisheng Zhang +L: linux-riscv at lists.infradead.org +S: Maintained +F: arch/riscv/boot/dts/bouffalolab/ + RISC-V MICROCHIP FPGA SUPPORT M: Conor Dooley M: Daire McNamara From 398fa5f8dd0b26e2ef59c38db908ce4bae033017 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Sun, 8 Jan 2023 01:35:45 -0800 Subject: [PATCH 06/39] riscv: bl808: Add defconfig --- arch/riscv/configs/bl808_defconfig | 143 +++++++++++++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 arch/riscv/configs/bl808_defconfig diff --git a/arch/riscv/configs/bl808_defconfig b/arch/riscv/configs/bl808_defconfig new file mode 100644 index 00000000000000..8a441a64be1a85 --- /dev/null +++ b/arch/riscv/configs/bl808_defconfig @@ -0,0 +1,143 @@ +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_USER_NS=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_PERF_EVENTS=y +CONFIG_SOC_BOUFFALOLAB=y +CONFIG_SOC_VIRT=y +CONFIG_ERRATA_THEAD=y +CONFIG_SMP=y +CONFIG_NR_CPUS=8 +CONFIG_RISCV_SBI_V01=y +# CONFIG_COMPAT is not set +CONFIG_KPROBES=y +CONFIG_JUMP_LABEL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_CMDLINE_PARTITION=y +CONFIG_PAGE_REPORTING=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_DNS_RESOLVER=y +CONFIG_NETLINK_DIAG=y +# CONFIG_WIRELESS is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK_RO=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_ROM=y +CONFIG_MTD_ABSENT=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_PHYSMAP_VERSATILE=y +CONFIG_MTD_PHYSMAP_GEMINI=y +CONFIG_MTD_PLATRAM=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_VIRTIO_BLK=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_VIRTIO=y +CONFIG_NETDEVICES=y +CONFIG_VIRTIO_NET=y +# CONFIG_ETHERNET is not set +CONFIG_MDIO_DEVICE=y +# CONFIG_WLAN is not set +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=y +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y +CONFIG_SERIAL_BFLB=y +CONFIG_SERIAL_BFLB_CONSOLE=y +CONFIG_SERIAL_SIFIVE=y +CONFIG_SERIAL_SIFIVE_CONSOLE=y +CONFIG_HVC_RISCV_SBI=y +CONFIG_VIRTIO_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_VIRTIO=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_XILINX=y +CONFIG_I2C_SLAVE=y +CONFIG_I2C_SLAVE_EEPROM=y +CONFIG_I2C_DEBUG_CORE=y +CONFIG_I2C_DEBUG_ALGO=y +CONFIG_I2C_DEBUG_BUS=y +CONFIG_FB=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_VGA_CONSOLE is not set +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +CONFIG_SYNC_FILE=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_RPMSG_CHAR=y +CONFIG_RPMSG_VIRTIO=y +CONFIG_GENERIC_PHY=y +CONFIG_AUTOFS4_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CONFIGFS_FS=y +# CONFIG_EFIVAR_FS is not set +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_UTF8=y +CONFIG_KEYS=y +CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity" +CONFIG_CRYPTO=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_DEV_VIRTIO=y +CONFIG_CRC16=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC7=y +CONFIG_XZ_DEC=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_VM_PGTABLE=y +CONFIG_DEBUG_TIMEKEEPING=y +CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_MEMTEST=y From 87c20a57492ca7eeff77278c74385a9ba6d39f2a Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Sun, 8 Jan 2023 02:25:29 -0800 Subject: [PATCH 07/39] riscv: dts: bouffalolab: add bootargs/initrd --- arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts index 64421fb2ad67d9..84e5aac6cbf851 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts @@ -17,6 +17,9 @@ chosen { stdout-path = "serial0:2000000n8"; + bootargs = "console=ttyS0,2000000 loglevel=8 earlycon=sbi root=/dev/mtdblock0 ro rootfstype=squashfs"; + linux,initrd-start = <0x0 0x52000000>; + linux,initrd-end = <0x0 0x52941784>; }; memory@50000000 { From c463c23723ed8823f03a7d0417136b800154af9b Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Sun, 8 Jan 2023 02:26:04 -0800 Subject: [PATCH 08/39] riscv: dts: bouffalolab: add xip_flash --- .../boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts index 84e5aac6cbf851..bdb502ea5a5489 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts @@ -26,6 +26,20 @@ device_type = "memory"; reg = <0x50000000 0x04000000>; }; + + xip_flash@58500000 { + compatible = "mtd-rom"; + reg = <0x58500000 0x400000>; + linux,mtd-name = "xip-flash.0"; + erase-size = <0x10000>; + bank-width = <4>; + + rootfs@0 { + label = "rootfs"; + reg = <0x00000 0x280000>; + read-only; + }; + }; }; &uart0 { From 950fd2ac1cd7529abee5852773db654e617173d1 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Wed, 11 Jan 2023 18:14:53 -0800 Subject: [PATCH 09/39] WIP: add BFLB MBOX interrupt controller driver --- .../boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 4 ++++ arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 14 ++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts index bdb502ea5a5489..70259bad7dfd31 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts @@ -45,3 +45,7 @@ &uart0 { status = "okay"; }; + +&ipclic { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi index c98ebb14ee10a6..c5cda8d74ccd9d 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -4,6 +4,7 @@ */ #include +#include / { compatible = "bouffalolab,bl808"; @@ -60,6 +61,19 @@ status = "disabled"; }; + ipclic: mailbox@30005000 { + compatible = "bouffalolab,bflb-ipc"; + reg = <0x30005000 0x20>, + <0x30005020 0x20>, + <0x2000a800 0x20>, + <0x2000a820 0x20>; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + status = "disabled"; + }; + plic: interrupt-controller@e0000000 { compatible = "thead,c900-plic"; reg = <0xe0000000 0x4000000>; From 661769605519fdb71bd4600663f8e0d5c810af7b Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Wed, 11 Jan 2023 18:16:51 -0800 Subject: [PATCH 10/39] WIP: sdhci: add BFLB sdhci driver --- arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 4 ++++ arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 11 +++++++++++ 2 files changed, 15 insertions(+) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts index 70259bad7dfd31..effaeda67c3fb7 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts @@ -46,6 +46,10 @@ status = "okay"; }; +&sdhci0 { + status = "okay"; +}; + &ipclic { status = "okay"; }; diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi index c5cda8d74ccd9d..6f859194f82c36 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -61,6 +61,17 @@ status = "disabled"; }; + sdhci0: sdhci@20060000 { + compatible = "bouffalolab,bflb-sdhci"; + reg = <0x20060000 0x100>; + interrupts-extended = <&ipclic BFLB_IPC_SOURCE_M0 + BFLB_IPC_DEVICE_SDHCI + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipclic BFLB_IPC_SOURCE_M0 BFLB_IPC_DEVICE_SDHCI>; + clocks = <&xtal>; + status = "disabled"; + }; + ipclic: mailbox@30005000 { compatible = "bouffalolab,bflb-ipc"; reg = <0x30005000 0x20>, From 4b74d104b878abe090836f86e42475a0b80235c9 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Wed, 11 Jan 2023 15:22:09 -0800 Subject: [PATCH 11/39] bl808_defconfig: enable sdhci driver --- arch/riscv/configs/bl808_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/configs/bl808_defconfig b/arch/riscv/configs/bl808_defconfig index 8a441a64be1a85..049fe1c25d74ec 100644 --- a/arch/riscv/configs/bl808_defconfig +++ b/arch/riscv/configs/bl808_defconfig @@ -103,6 +103,10 @@ CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y # CONFIG_HID_MICROSOFT is not set # CONFIG_HID_MONTEREY is not set # CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_BFLB=y CONFIG_RTC_CLASS=y CONFIG_SYNC_FILE=y # CONFIG_VIRTIO_MENU is not set From 69e4d28bdf14e9a6c764f14ec7466c603d976094 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Wed, 11 Jan 2023 15:22:29 -0800 Subject: [PATCH 12/39] bl808_defconfig: enable mailbox irqchip driver --- arch/riscv/configs/bl808_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/configs/bl808_defconfig b/arch/riscv/configs/bl808_defconfig index 049fe1c25d74ec..d2786235830294 100644 --- a/arch/riscv/configs/bl808_defconfig +++ b/arch/riscv/configs/bl808_defconfig @@ -111,6 +111,8 @@ CONFIG_RTC_CLASS=y CONFIG_SYNC_FILE=y # CONFIG_VIRTIO_MENU is not set # CONFIG_VHOST_MENU is not set +CONFIG_MAILBOX=y +CONFIG_BFLB_IPC=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_RPMSG_CHAR=y CONFIG_RPMSG_VIRTIO=y From 3b946f78adcf9cd06ab60e444ce696aa3bab66d8 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Wed, 11 Jan 2023 15:23:03 -0800 Subject: [PATCH 13/39] bl808_defconfig: enable irq debugfs --- arch/riscv/configs/bl808_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/bl808_defconfig b/arch/riscv/configs/bl808_defconfig index d2786235830294..0cc8c786a522b2 100644 --- a/arch/riscv/configs/bl808_defconfig +++ b/arch/riscv/configs/bl808_defconfig @@ -1,5 +1,6 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y +CONFIG_GENERIC_IRQ_DEBUGFS=y CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y CONFIG_BPF_SYSCALL=y From e4017e32952a79b01a829092298e558bee92681e Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Wed, 11 Jan 2023 18:14:53 -0800 Subject: [PATCH 14/39] WIP: add BFLB MBOX interrupt controller driver --- include/dt-bindings/mailbox/bflb-ipc.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 include/dt-bindings/mailbox/bflb-ipc.h diff --git a/include/dt-bindings/mailbox/bflb-ipc.h b/include/dt-bindings/mailbox/bflb-ipc.h new file mode 100644 index 00000000000000..1d4c4be6292e97 --- /dev/null +++ b/include/dt-bindings/mailbox/bflb-ipc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (C) 2023 Allen Martin + */ + +#ifndef __DT_BINDINGS_MAILBOX_BFLB_IPC_H +#define __DT_BINDINGS_MAILBOX_BFLB_IPC_H + +/* Source processor */ +#define BFLB_IPC_SOURCE_M0 0 +#define BFLB_IPC_SOURCE_LP 1 + +/* Peripheral device ID */ +#define BFLB_IPC_DEVICE_SDHCI 0 + +#endif From 885fc70c6a228c9285c23ec4d7f07a98964f643f Mon Sep 17 00:00:00 2001 From: Alexander Horner <33007665+alexhorner@users.noreply.github.com> Date: Sat, 14 Jan 2023 00:05:40 +0000 Subject: [PATCH 15/39] UART2 working under Linux! --- arch/riscv/boot/dts/bouffalolab/Makefile | 1 + .../dts/bouffalolab/bl808-pine64-ox64.dts | 60 +++++++++++++++++++ arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 13 +++- include/dt-bindings/mailbox/bflb-ipc.h | 1 + 4 files changed, 74 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts diff --git a/arch/riscv/boot/dts/bouffalolab/Makefile b/arch/riscv/boot/dts/bouffalolab/Makefile index 42e17e1a97bd17..bc7aad3d560406 100644 --- a/arch/riscv/boot/dts/bouffalolab/Makefile +++ b/arch/riscv/boot/dts/bouffalolab/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_SOC_BOUFFALOLAB) += bl808-sipeed-m1s.dtb +dtb-$(CONFIG_SOC_BOUFFALOLAB) += bl808-pine64-ox64.dtb diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts new file mode 100644 index 00000000000000..a3b1ae9f04780d --- /dev/null +++ b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2022 Jisheng Zhang + */ + +/dts-v1/; + +#include "bl808.dtsi" + +/ { + model = "Pine64 Ox64"; + compatible = "sipeed,m1s", "bouffalolab,bl808"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:2000000n8"; + bootargs = "console=ttyS0,2000000 loglevel=8 earlycon=sbi root=/dev/mtdblock0 ro rootfstype=squashfs"; + linux,initrd-start = <0x0 0x52000000>; + linux,initrd-end = <0x0 0x52941784>; + }; + + memory@50000000 { + device_type = "memory"; + reg = <0x50000000 0x04000000>; + }; + + xip_flash@58500000 { + compatible = "mtd-rom"; + reg = <0x58500000 0x400000>; + linux,mtd-name = "xip-flash.0"; + erase-size = <0x10000>; + bank-width = <4>; + + rootfs@0 { + label = "rootfs"; + reg = <0x00000 0x280000>; + read-only; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&sdhci0 { + status = "okay"; +}; + +&ipclic { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi index 6f859194f82c36..755071f80b5904 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -60,7 +60,18 @@ clocks = <&xtal>; status = "disabled"; }; - + + uart1: serial@0x2000AA00 { + compatible = "bouffalolab,uart"; + reg = <0x2000AA00 0x0100>; + interrupts-extended = <&ipclic BFLB_IPC_SOURCE_M0 + BFLB_IPC_DEVICE_UART2 + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipclic BFLB_IPC_SOURCE_M0 BFLB_IPC_DEVICE_UART2>; + clocks = <&xtal>; + status = "disabled"; + }; + sdhci0: sdhci@20060000 { compatible = "bouffalolab,bflb-sdhci"; reg = <0x20060000 0x100>; diff --git a/include/dt-bindings/mailbox/bflb-ipc.h b/include/dt-bindings/mailbox/bflb-ipc.h index 1d4c4be6292e97..e96fe62cbeb9a2 100644 --- a/include/dt-bindings/mailbox/bflb-ipc.h +++ b/include/dt-bindings/mailbox/bflb-ipc.h @@ -12,5 +12,6 @@ /* Peripheral device ID */ #define BFLB_IPC_DEVICE_SDHCI 0 +#define BFLB_IPC_DEVICE_UART2 1 #endif From 9a54e5b68abb12792cda5342b581a46356e57825 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Sat, 14 Jan 2023 17:59:13 -0800 Subject: [PATCH 16/39] dts: bl808: add fake sdh clock at 96MHz --- arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi index 755071f80b5904..ecb285cd7763ed 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -45,6 +45,13 @@ #clock-cells = <0>; }; + sdh: sdh-clk { + compatible = "fixed-clock"; + clock-frequency = <96000000>; + clock-output-names = "sdh"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; ranges; @@ -79,7 +86,7 @@ BFLB_IPC_DEVICE_SDHCI IRQ_TYPE_EDGE_RISING>; mboxes = <&ipclic BFLB_IPC_SOURCE_M0 BFLB_IPC_DEVICE_SDHCI>; - clocks = <&xtal>; + clocks = <&sdh>; status = "disabled"; }; From ad398a49333c425e52f8f46840d4276bdcbdc457 Mon Sep 17 00:00:00 2001 From: Alexander Horner <33007665+alexhorner@users.noreply.github.com> Date: Sun, 15 Jan 2023 13:38:26 +0000 Subject: [PATCH 17/39] Disable flash rootfs for now, edit bootargs to use SDHCI ext4 partition 1 rootfs --- arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts index a3b1ae9f04780d..d3d228c3d8c0ea 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts @@ -18,7 +18,7 @@ chosen { stdout-path = "serial0:2000000n8"; - bootargs = "console=ttyS0,2000000 loglevel=8 earlycon=sbi root=/dev/mtdblock0 ro rootfstype=squashfs"; + bootargs = "console=ttyS0,2000000 loglevel=8 earlycon=sbi root=/dev/mmcblk0p1 rootwait rootfstype=ext4"; linux,initrd-start = <0x0 0x52000000>; linux,initrd-end = <0x0 0x52941784>; }; @@ -35,11 +35,11 @@ erase-size = <0x10000>; bank-width = <4>; - rootfs@0 { + /*rootfs@0 { label = "rootfs"; - reg = <0x00000 0x280000>; + reg = <0x00000 0x400000>; read-only; - }; + };*/ }; }; From b2fe2832f829538921d9c8ac3bbcbd053b776c6b Mon Sep 17 00:00:00 2001 From: Alexander Horner <33007665+alexhorner@users.noreply.github.com> Date: Sun, 15 Jan 2023 14:24:55 +0000 Subject: [PATCH 18/39] Update defconfig with EXT4 support for SD rootfs --- arch/riscv/configs/bl808_defconfig | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/riscv/configs/bl808_defconfig b/arch/riscv/configs/bl808_defconfig index 0cc8c786a522b2..2acab58e801b67 100644 --- a/arch/riscv/configs/bl808_defconfig +++ b/arch/riscv/configs/bl808_defconfig @@ -118,6 +118,7 @@ CONFIG_BFLB_IPC=y CONFIG_RPMSG_CHAR=y CONFIG_RPMSG_VIRTIO=y CONFIG_GENERIC_PHY=y +CONFIG_EXT4_FS=y CONFIG_AUTOFS4_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y @@ -133,11 +134,8 @@ CONFIG_NLS_ISO8859_1=y CONFIG_NLS_UTF8=y CONFIG_KEYS=y CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity" -CONFIG_CRYPTO=y -CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_USER_API_HASH=y CONFIG_CRYPTO_DEV_VIRTIO=y -CONFIG_CRC16=y CONFIG_CRC_ITU_T=y CONFIG_CRC7=y CONFIG_XZ_DEC=y From 4c45c424d0d3e02b1d47b275d37d477f944d6914 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Fri, 13 Jan 2023 02:38:06 -0800 Subject: [PATCH 19/39] usb: add bflb ehci controller --- arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts | 4 ++++ arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 4 ++++ arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 10 ++++++++++ include/dt-bindings/mailbox/bflb-ipc.h | 1 + 4 files changed, 19 insertions(+) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts index d3d228c3d8c0ea..66a892f880c71a 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts @@ -58,3 +58,7 @@ &ipclic { status = "okay"; }; + +&ehci0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts index effaeda67c3fb7..19155bcc269373 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts @@ -53,3 +53,7 @@ &ipclic { status = "okay"; }; + +&ehci0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi index ecb285cd7763ed..f3e4f17e69c033 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -90,6 +90,16 @@ status = "disabled"; }; + ehci0: usb@20072000 { + compatible = "generic-ehci"; + reg = <0x20072010 0x1000>; + interrupts-extended = <&ipclic BFLB_IPC_SOURCE_M0 + BFLB_IPC_DEVICE_USB + IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>; + status = "disabled"; + }; + ipclic: mailbox@30005000 { compatible = "bouffalolab,bflb-ipc"; reg = <0x30005000 0x20>, diff --git a/include/dt-bindings/mailbox/bflb-ipc.h b/include/dt-bindings/mailbox/bflb-ipc.h index e96fe62cbeb9a2..327e150384b95f 100644 --- a/include/dt-bindings/mailbox/bflb-ipc.h +++ b/include/dt-bindings/mailbox/bflb-ipc.h @@ -13,5 +13,6 @@ /* Peripheral device ID */ #define BFLB_IPC_DEVICE_SDHCI 0 #define BFLB_IPC_DEVICE_UART2 1 +#define BFLB_IPC_DEVICE_USB 2 #endif From 0a7184765d42e951d892e1c7b70c6eb08eb67ec9 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Fri, 13 Jan 2023 02:38:58 -0800 Subject: [PATCH 20/39] bl808_defconfig: enable USB and EHCI --- arch/riscv/configs/bl808_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/configs/bl808_defconfig b/arch/riscv/configs/bl808_defconfig index 2acab58e801b67..c43e21711750c7 100644 --- a/arch/riscv/configs/bl808_defconfig +++ b/arch/riscv/configs/bl808_defconfig @@ -103,7 +103,9 @@ CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y # CONFIG_HID_REDRAGON is not set # CONFIG_HID_MICROSOFT is not set # CONFIG_HID_MONTEREY is not set -# CONFIG_USB_SUPPORT is not set +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y From aa9ca42882bd51620df7d5b591bb0c368ea830e4 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Sun, 15 Jan 2023 21:06:40 -0800 Subject: [PATCH 21/39] dts: bl808: fix offset of ehci controller ehci controller registers are at address 0x20072000 not 0x20072010 --- arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi index f3e4f17e69c033..5e90f3ee04d716 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -92,7 +92,7 @@ ehci0: usb@20072000 { compatible = "generic-ehci"; - reg = <0x20072010 0x1000>; + reg = <0x20072000 0x1000>; interrupts-extended = <&ipclic BFLB_IPC_SOURCE_M0 BFLB_IPC_DEVICE_USB IRQ_TYPE_EDGE_RISING>; From 3258905a37d4e65b045453a0955a87a03469a6d2 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Sun, 15 Jan 2023 21:11:40 -0800 Subject: [PATCH 22/39] bl808_defconfig: enable USB serial and network devices --- arch/riscv/configs/bl808_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/configs/bl808_defconfig b/arch/riscv/configs/bl808_defconfig index c43e21711750c7..39ad1cb2b4bc55 100644 --- a/arch/riscv/configs/bl808_defconfig +++ b/arch/riscv/configs/bl808_defconfig @@ -106,6 +106,8 @@ CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SERIAL=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y From dcecd699e76f054916fde5f661fecc410938c5f9 Mon Sep 17 00:00:00 2001 From: Justin Hammond Date: Fri, 20 Jan 2023 13:45:52 +0800 Subject: [PATCH 23/39] Rename DTS Files --- arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts | 8 +------- arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 2 +- arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 10 +++++----- 3 files changed, 7 insertions(+), 13 deletions(-) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts index 66a892f880c71a..eede26e4f043c0 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts @@ -9,7 +9,7 @@ / { model = "Pine64 Ox64"; - compatible = "sipeed,m1s", "bouffalolab,bl808"; + compatible = "sipeed,m1s", "bflb,bl808"; aliases { serial0 = &uart0; @@ -34,12 +34,6 @@ linux,mtd-name = "xip-flash.0"; erase-size = <0x10000>; bank-width = <4>; - - /*rootfs@0 { - label = "rootfs"; - reg = <0x00000 0x400000>; - read-only; - };*/ }; }; diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts index 19155bcc269373..ed2d18482920c6 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts @@ -9,7 +9,7 @@ / { model = "Sipeed M1S"; - compatible = "sipeed,m1s", "bouffalolab,bl808"; + compatible = "sipeed,m1s", "bflb,bl808"; aliases { serial0 = &uart0; diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi index 5e90f3ee04d716..bdfed1bde043ff 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -7,7 +7,7 @@ #include / { - compatible = "bouffalolab,bl808"; + compatible = "bflb,bl808"; #address-cells = <1>; #size-cells = <1>; @@ -61,7 +61,7 @@ #size-cells = <1>; uart0: serial@30002000 { - compatible = "bouffalolab,uart"; + compatible = "bflb,bl808-uart"; reg = <0x30002000 0x1000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&xtal>; @@ -69,7 +69,7 @@ }; uart1: serial@0x2000AA00 { - compatible = "bouffalolab,uart"; + compatible = "bflb,bl808-uart"; reg = <0x2000AA00 0x0100>; interrupts-extended = <&ipclic BFLB_IPC_SOURCE_M0 BFLB_IPC_DEVICE_UART2 @@ -80,7 +80,7 @@ }; sdhci0: sdhci@20060000 { - compatible = "bouffalolab,bflb-sdhci"; + compatible = "bflb,bl808-sdhci"; reg = <0x20060000 0x100>; interrupts-extended = <&ipclic BFLB_IPC_SOURCE_M0 BFLB_IPC_DEVICE_SDHCI @@ -101,7 +101,7 @@ }; ipclic: mailbox@30005000 { - compatible = "bouffalolab,bflb-ipc"; + compatible = "bflb,bl808-ipc"; reg = <0x30005000 0x20>, <0x30005020 0x20>, <0x2000a800 0x20>, From 5de10314906445dd50565284c6fb822e86e3490c Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Fri, 20 Jan 2023 19:01:49 -0800 Subject: [PATCH 24/39] dts: bl808-pine64-ox64: change rootfs to /dev/mmcblk0p2 --- arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts index eede26e4f043c0..4e183098f171ec 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts @@ -18,7 +18,7 @@ chosen { stdout-path = "serial0:2000000n8"; - bootargs = "console=ttyS0,2000000 loglevel=8 earlycon=sbi root=/dev/mmcblk0p1 rootwait rootfstype=ext4"; + bootargs = "console=ttyS0,2000000 loglevel=8 earlycon=sbi root=/dev/mmcblk0p2 rootwait rootfstype=ext4"; linux,initrd-start = <0x0 0x52000000>; linux,initrd-end = <0x0 0x52941784>; }; From 37884166bce69b4289af44e9e1422b7b1078c463 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Tue, 24 Jan 2023 17:00:32 -0800 Subject: [PATCH 25/39] dts: bl808-pine64-ox64: disable secondary UART Pinmux for this device conflicts with EMAC, so disable it until pinmux is changed to some other pins. --- arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts index 4e183098f171ec..96cc039133cc04 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts @@ -41,10 +41,6 @@ status = "okay"; }; -&uart1 { - status = "okay"; -}; - &sdhci0 { status = "okay"; }; From 92d66e03a0a0f921142c67472eec01cbbfde13b9 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Tue, 24 Jan 2023 17:02:40 -0800 Subject: [PATCH 26/39] dts: bl808: add entry for EMAC device Add device-tree node for EMAC ethernet device and fake clock node to represent 50MHz clock to the device. Add a virtualized interrupt bit for forwareded EMAC interrupts. --- arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 17 +++++++++++++++++ include/dt-bindings/mailbox/bflb-ipc.h | 1 + 2 files changed, 18 insertions(+) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi index bdfed1bde043ff..dd795667dea68f 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -52,6 +52,13 @@ #clock-cells = <0>; }; + enet: enet-clk { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + clock-output-names = "enet"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; ranges; @@ -100,6 +107,16 @@ status = "disabled"; }; + enet0: emac@20070000 { + compatible = "opencores,ethoc"; + reg = <0x20070000 0x1000>; + interrupts-extended = <&ipclic BFLB_IPC_SOURCE_M0 + BFLB_IPC_DEVICE_EMAC + IRQ_TYPE_EDGE_RISING>; + clocks = <&enet>; + status = "disabled"; + }; + ipclic: mailbox@30005000 { compatible = "bflb,bl808-ipc"; reg = <0x30005000 0x20>, diff --git a/include/dt-bindings/mailbox/bflb-ipc.h b/include/dt-bindings/mailbox/bflb-ipc.h index 327e150384b95f..0a3c6745a673c1 100644 --- a/include/dt-bindings/mailbox/bflb-ipc.h +++ b/include/dt-bindings/mailbox/bflb-ipc.h @@ -14,5 +14,6 @@ #define BFLB_IPC_DEVICE_SDHCI 0 #define BFLB_IPC_DEVICE_UART2 1 #define BFLB_IPC_DEVICE_USB 2 +#define BFLB_IPC_DEVICE_EMAC 3 #endif From 2ad217b4095e489b76e3d8f1d9c42a668c5e013b Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Tue, 24 Jan 2023 17:13:31 -0800 Subject: [PATCH 27/39] riscv: bl808_defconfig: enable ETHOC driver --- arch/riscv/configs/bl808_defconfig | 45 ++++++++++++++++++++++++++++-- 1 file changed, 43 insertions(+), 2 deletions(-) diff --git a/arch/riscv/configs/bl808_defconfig b/arch/riscv/configs/bl808_defconfig index 39ad1cb2b4bc55..d51f2d78c139d6 100644 --- a/arch/riscv/configs/bl808_defconfig +++ b/arch/riscv/configs/bl808_defconfig @@ -63,8 +63,48 @@ CONFIG_BLK_DEV_SD=y CONFIG_SCSI_VIRTIO=y CONFIG_NETDEVICES=y CONFIG_VIRTIO_NET=y -# CONFIG_ETHERNET is not set -CONFIG_MDIO_DEVICE=y +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ASIX is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_DAVICOM is not set +# CONFIG_NET_VENDOR_ENGLEDER is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FUNGIBLE is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_WANGXUN is not set +# CONFIG_NET_VENDOR_LITEX is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_MICROSOFT is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +CONFIG_ETHOC=y +# CONFIG_NET_VENDOR_PENSANDO is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VERTEXCOM is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set # CONFIG_WLAN is not set CONFIG_INPUT_MOUSEDEV=y CONFIG_INPUT_EVDEV=y @@ -88,6 +128,7 @@ CONFIG_I2C_SLAVE_EEPROM=y CONFIG_I2C_DEBUG_CORE=y CONFIG_I2C_DEBUG_ALGO=y CONFIG_I2C_DEBUG_BUS=y +# CONFIG_PTP_1588_CLOCK is not set CONFIG_FB=y CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_VGA_CONSOLE is not set From a7bbe72dd574b66708c0cc060898551f3917b74a Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Tue, 24 Jan 2023 17:14:05 -0800 Subject: [PATCH 28/39] dts: bl808: enable enet nodes --- arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts | 4 ++++ arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts index 96cc039133cc04..f9ed636291f614 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts @@ -52,3 +52,7 @@ &ehci0 { status = "okay"; }; + +&enet0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts index ed2d18482920c6..031c824f2061ae 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts @@ -57,3 +57,7 @@ &ehci0 { status = "okay"; }; + +&enet0 { + status = "okay"; +}; From ee0931def8e7ff676e11ebe147c1128862e2c8f6 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 5 Feb 2023 16:13:42 -0600 Subject: [PATCH 29/39] riscv: dts: bflb: m1s: Fix address/size-cells The number of address cells needed here (one) does not match the implicitly-defined default number of cells. Signed-off-by: Samuel Holland --- arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts index 031c824f2061ae..5307508e7a9462 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts @@ -33,6 +33,8 @@ linux,mtd-name = "xip-flash.0"; erase-size = <0x10000>; bank-width = <4>; + #address-cells = <1>; + #size-cells = <1>; rootfs@0 { label = "rootfs"; From be296b48621098e41309ac433fc3ebdd3d64c4bd Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Sun, 5 Feb 2023 20:18:50 -0800 Subject: [PATCH 30/39] riscv: dts: bflb: ox64: Fix address/size-cells The number of address cells needed here (one) does not match the implicitly-defined default number of cells. Signed-off-by: Allen Martin --- arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts index f9ed636291f614..f1db126d88e76f 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts @@ -34,6 +34,8 @@ linux,mtd-name = "xip-flash.0"; erase-size = <0x10000>; bank-width = <4>; + #address-cells = <1>; + #size-cells = <1>; }; }; From d48d4b1210f8a99578a429fecc282e83d7f8bc92 Mon Sep 17 00:00:00 2001 From: Justin Hammond Date: Mon, 6 Feb 2023 13:38:55 +0800 Subject: [PATCH 31/39] Add timer node for OpenSBI 1.2 compatibility --- arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi index dd795667dea68f..34652e17aece8f 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -140,5 +140,12 @@ #interrupt-cells = <2>; riscv,ndev = <64>; }; + + clint: timer@e4000000 { + compatible = "thead,c900-clint"; + reg = <0xe4000000 0xc000>; + interrupts-extended = <&cpu0_intc 3>, + <&cpu0_intc 7>; + }; }; }; From b79eef5b82707b2fe5823dc6e5e30f3fd94561ff Mon Sep 17 00:00:00 2001 From: Justin Hammond Date: Mon, 6 Feb 2023 13:41:53 +0800 Subject: [PATCH 32/39] Tabstops are 8 chars, not 4 --- arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi index 34652e17aece8f..7cd033b6a1cf36 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -145,7 +145,7 @@ compatible = "thead,c900-clint"; reg = <0xe4000000 0xc000>; interrupts-extended = <&cpu0_intc 3>, - <&cpu0_intc 7>; + <&cpu0_intc 7>; }; }; }; From 4fb02196485265eeb2c13868932219d3de09a809 Mon Sep 17 00:00:00 2001 From: Alexander Horner <33007665+alexhorner@users.noreply.github.com> Date: Thu, 16 Feb 2023 19:42:01 +0000 Subject: [PATCH 33/39] Update device trees for new GPIO and HWRNG drivers --- .../dts/bouffalolab/bl808-pine64-ox64.dts | 8 +++++ arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 30 +++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts index f1db126d88e76f..5050c80b6f1150 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts @@ -39,6 +39,14 @@ }; }; +&pinctrl { + status = "okay"; +}; + +&seceng { + status = "okay"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi index 7cd033b6a1cf36..73a4e055c7a9e6 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -67,6 +67,36 @@ #address-cells = <1>; #size-cells = <1>; + pinctrl: pinctrl@0x200008C4 { + compatible = "bflb,pinctrl"; + //Last register is for gpio_cfg141 at 0x20000af8 + reg = <0x200008C4 0x1000>; + //clocks = <&gpio_clk>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 46>; + bflb,npins = <46>; + + status = "disabled"; + + interrupt-controller; + #interrupt-cells = <2>; + interrupts-extended = <&ipclic BFLB_IPC_SOURCE_M0 + BFLB_IPC_DEVICE_GPIO IRQ_TYPE_EDGE_RISING>; + + sdh_pins: sdh-pins { + pins = "GPIO0", "GPIO1", "GPIO2", "GPIO3", "GPIO4", "GPIO5"; + function = "sdh"; + }; + }; + + seceng: seceng@0x20004000 { + compatible = "bflb,seceng"; + reg = <0x20004000 0x1000>; + status = "disabled"; + }; + uart0: serial@30002000 { compatible = "bflb,bl808-uart"; reg = <0x30002000 0x1000>; From 56820fe33133f4d37dc277a344c5a54bfeb502c3 Mon Sep 17 00:00:00 2001 From: Alexander Horner <33007665+alexhorner@users.noreply.github.com> Date: Tue, 14 Feb 2023 23:12:03 +0000 Subject: [PATCH 34/39] Update bl808_defconfig for new drivers --- arch/riscv/configs/bl808_defconfig | 40 ++++++++++++++++++++++-------- 1 file changed, 30 insertions(+), 10 deletions(-) diff --git a/arch/riscv/configs/bl808_defconfig b/arch/riscv/configs/bl808_defconfig index d51f2d78c139d6..9e234dcb5ec0d7 100644 --- a/arch/riscv/configs/bl808_defconfig +++ b/arch/riscv/configs/bl808_defconfig @@ -11,8 +11,10 @@ CONFIG_CGROUP_SCHED=y CONFIG_CFS_BANDWIDTH=y CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y +CONFIG_NAMESPACES=y CONFIG_USER_NS=y CONFIG_CHECKPOINT_RESTORE=y +CONFIG_EXPERT=y CONFIG_PERF_EVENTS=y CONFIG_SOC_BOUFFALOLAB=y CONFIG_SOC_VIRT=y @@ -129,21 +131,15 @@ CONFIG_I2C_DEBUG_CORE=y CONFIG_I2C_DEBUG_ALGO=y CONFIG_I2C_DEBUG_BUS=y # CONFIG_PTP_1588_CLOCK is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_BFLB_GPIO=y +CONFIG_GPIO_SYSFS=y CONFIG_FB=y CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -# CONFIG_HID_A4TECH is not set -# CONFIG_HID_BELKIN is not set -# CONFIG_HID_CHERRY is not set -# CONFIG_HID_CYPRESS is not set -# CONFIG_HID_EZKEY is not set -# CONFIG_HID_ITE is not set -# CONFIG_HID_KENSINGTON is not set -# CONFIG_HID_REDRAGON is not set -# CONFIG_HID_MICROSOFT is not set -# CONFIG_HID_MONTEREY is not set +CONFIG_HID_CHICONY=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_HCD_PLATFORM=y @@ -153,6 +149,27 @@ CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_BFLB=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_USER=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_MTD=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_ACTIVITY=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_TRANSIENT=y +CONFIG_LEDS_TRIGGER_CAMERA=y +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_NETDEV=y +CONFIG_LEDS_TRIGGER_PATTERN=y +CONFIG_LEDS_TRIGGER_AUDIO=y +CONFIG_LEDS_TRIGGER_TTY=y CONFIG_RTC_CLASS=y CONFIG_SYNC_FILE=y # CONFIG_VIRTIO_MENU is not set @@ -180,6 +197,7 @@ CONFIG_NLS_UTF8=y CONFIG_KEYS=y CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity" CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_DEV_BFLB_SECENG=y CONFIG_CRYPTO_DEV_VIRTIO=y CONFIG_CRC_ITU_T=y CONFIG_CRC7=y @@ -187,7 +205,9 @@ CONFIG_XZ_DEC=y CONFIG_PRINTK_TIME=y CONFIG_DEBUG_FS=y CONFIG_DEBUG_VM_PGTABLE=y +CONFIG_DEBUG_MEMORY_INIT=y CONFIG_DEBUG_TIMEKEEPING=y +# CONFIG_FTRACE is not set CONFIG_FUNCTION_ERROR_INJECTION=y # CONFIG_RUNTIME_TESTING_MENU is not set CONFIG_MEMTEST=y From 5bc30359db03519fe18fafbbf0b1f4c38dbebdf7 Mon Sep 17 00:00:00 2001 From: Alexander Horner <33007665+alexhorner@users.noreply.github.com> Date: Thu, 16 Feb 2023 19:43:15 +0000 Subject: [PATCH 35/39] Bring M1s device tree up to date with Ox64's changes, fix compatible string on the Ox64 device tree --- .../dts/bouffalolab/bl808-pine64-ox64.dts | 2 +- .../boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 31 ++++++++++++++----- 2 files changed, 25 insertions(+), 8 deletions(-) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts index 5050c80b6f1150..c5b1e86310d983 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts @@ -9,7 +9,7 @@ / { model = "Pine64 Ox64"; - compatible = "sipeed,m1s", "bflb,bl808"; + compatible = "pine64,ox64", "bflb,bl808"; aliases { serial0 = &uart0; diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts index 5307508e7a9462..ecdce792132336 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts @@ -6,9 +6,11 @@ /dts-v1/; #include "bl808.dtsi" +#include +#include / { - model = "Sipeed M1S"; + model = "Sipeed M1s"; compatible = "sipeed,m1s", "bflb,bl808"; aliases { @@ -17,7 +19,7 @@ chosen { stdout-path = "serial0:2000000n8"; - bootargs = "console=ttyS0,2000000 loglevel=8 earlycon=sbi root=/dev/mtdblock0 ro rootfstype=squashfs"; + bootargs = "console=ttyS0,2000000 loglevel=8 earlycon=sbi root=/dev/mmcblk0p2 rootwait rootfstype=ext4"; linux,initrd-start = <0x0 0x52000000>; linux,initrd-end = <0x0 0x52941784>; }; @@ -35,15 +37,30 @@ bank-width = <4>; #address-cells = <1>; #size-cells = <1>; + }; + + leds { + compatible = "gpio-leds"; + + led { + gpios = <&pinctrl 8 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&pinctrl { + status = "okay"; - rootfs@0 { - label = "rootfs"; - reg = <0x00000 0x280000>; - read-only; - }; + led { + pins = "GPIO8"; + function = "gpio"; }; }; +&seceng { + status = "okay"; +}; + &uart0 { status = "okay"; }; From b9595ae86079168be9389006f090fd046f91111a Mon Sep 17 00:00:00 2001 From: Alexander Horner <33007665+alexhorner@users.noreply.github.com> Date: Tue, 14 Feb 2023 22:44:18 +0000 Subject: [PATCH 36/39] Add GPIO/PINCTRL and HWRNG/Crypto drivers --- include/dt-bindings/mailbox/bflb-ipc.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/mailbox/bflb-ipc.h b/include/dt-bindings/mailbox/bflb-ipc.h index 0a3c6745a673c1..9763460edbcc75 100644 --- a/include/dt-bindings/mailbox/bflb-ipc.h +++ b/include/dt-bindings/mailbox/bflb-ipc.h @@ -13,7 +13,8 @@ /* Peripheral device ID */ #define BFLB_IPC_DEVICE_SDHCI 0 #define BFLB_IPC_DEVICE_UART2 1 -#define BFLB_IPC_DEVICE_USB 2 +#define BFLB_IPC_DEVICE_USB 2 #define BFLB_IPC_DEVICE_EMAC 3 +#define BFLB_IPC_DEVICE_GPIO 4 #endif From 3532068965415161d1e3e90f4c952feb82547bba Mon Sep 17 00:00:00 2001 From: "Grant T. Olson" Date: Fri, 10 Mar 2023 10:36:18 -0500 Subject: [PATCH 37/39] BL808 Watchdog Support #2/3: device-tree updates --- arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts | 4 ++++ arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 4 ++++ arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 6 ++++++ 3 files changed, 14 insertions(+) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts index c5b1e86310d983..50ca13e8e68e67 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts @@ -66,3 +66,7 @@ &enet0 { status = "okay"; }; + +&wdt { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts index ecdce792132336..e22a162932424f 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts @@ -80,3 +80,7 @@ &enet0 { status = "okay"; }; + +&wdt { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi index 73a4e055c7a9e6..c3617b61e0adaf 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -147,6 +147,12 @@ status = "disabled"; }; + wdt: wdt@2000a500 { + compatible = "bflb,bl808-wdt"; + reg = <0x2000a500 0x100>; + status = "disabled"; + }; + ipclic: mailbox@30005000 { compatible = "bflb,bl808-ipc"; reg = <0x30005000 0x20>, From a4c7de0f326b7b453cded8e7cffed70c0cf8f0c5 Mon Sep 17 00:00:00 2001 From: "Grant T. Olson" Date: Mon, 6 Feb 2023 15:18:43 -0500 Subject: [PATCH 38/39] BL808 Watchdog Support #2/3: Watchdog device driver --- drivers/watchdog/Kconfig | 11 ++ drivers/watchdog/Makefile | 3 + drivers/watchdog/bflb_wdt.c | 291 ++++++++++++++++++++++++++++++++++++ 3 files changed, 305 insertions(+) create mode 100644 drivers/watchdog/bflb_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 0bc40b763b0652..8df5e1d38752a3 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -181,6 +181,17 @@ config BD957XMUF_WATCHDOG watchdog. Alternatively say M to compile the driver as a module, which will be called bd9576_wdt. +config BFLB_WATCHDOG + tristate "BFLB BL808 Watchdog" + depends on SOC_BOUFFALOLAB + select WATCHDOG_CORE + help + Support for the watchdog on BL808. + + Say Y here to include support for the BL808 watchdog. + Alternately say M to compile the driver as a module, + which will be called bflb_wdt. + config DA9052_WATCHDOG tristate "Dialog DA9052 Watchdog" depends on PMIC_DA9052 || COMPILE_TEST diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 9cbf6580f16c9f..736e7224fe4a6e 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -192,6 +192,9 @@ obj-$(CONFIG_MEN_A21_WDT) += mena21_wdt.o obj-$(CONFIG_PSERIES_WDT) += pseries-wdt.o obj-$(CONFIG_WATCHDOG_RTAS) += wdrtas.o +# RISC-V Architecture +obj-$(CONFIG_BFLB_WATCHDOG) += bflb_wdt.o + # S390 Architecture obj-$(CONFIG_DIAG288_WATCHDOG) += diag288_wdt.o diff --git a/drivers/watchdog/bflb_wdt.c b/drivers/watchdog/bflb_wdt.c new file mode 100644 index 00000000000000..27fbb877ad76fd --- /dev/null +++ b/drivers/watchdog/bflb_wdt.c @@ -0,0 +1,291 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// Settings here get us the slowest possible clock speed on the hardware +// which is the closest we can get to the linux watchdog's resolution of +// 1 second. +#define BFLB_INT_TICKS_PER_SEC 1024 +#define BFLB_TICK_CLKDIV 256 +#define BFLB_TICKS_PER_SEC ( BFLB_INT_TICKS_PER_SEC / BFLB_TICK_CLKDIV ) +#define BFLB_MAX_SECS ( 65535 / BFLB_TICKS_PER_SEC ) + +#define BFLB_DEFAULT_TIMEOUT 60 + +#define BFLB_REG_BASE 0x2000A500 + +#define BFLB_REG_WFAR 0x9C +#define BFLB_WFAR_MAGIC 0xBABA + +#define BFLB_REG_WSAR 0xA0 +#define BFLB_WSAR_MAGIC 0xEB10 + +#define BFLB_REG_WVR 0x6C +#define BFLB_REG_WCR 0x98 +#define BFLB_WCR_RESET_COUNTER BIT(0) + +#define BFLB_REG_WMER 0x64 +#define BFLB_WMER_WATCHDOG_ENABLE BIT(0) +#define BFLB_WMER_RESET_SOURCE BIT(1) + +#define BFLB_REG_TCCR 0x00 +#define BFLB_SHIFT_CS_WDT 8 +#define BFLB_MASK_CS_WDT GENMASK(BFLB_SHIFT_CS_WDT+3,BFLB_SHIFT_CS_WDT) +#define BFLB_TCCR_CS_FCLK (0x0 << BFLB_SHIFT_CS_WDT) +#define BFLB_TCCR_CS_32K (0x1 << BFLB_SHIFT_CS_WDT) +#define BFLB_TCCR_CS_1K (0x2 << BFLB_SHIFT_CS_WDT) +#define BFLB_TCCR_CS_32M (0x3 << BFLB_SHIFT_CS_WDT) +#define BFLB_TCCR_CS_GPIO (0x4 << BFLB_SHIFT_CS_WDT) + +#define BFLB_REG_TCDR 0xbc +#define BFLB_SHIFT_WDT_CLKDIV 24 +#define BFLB_MASK_TCDR GENMASK(BFLB_SHIFT_WDT_CLKDIV+7,BFLB_SHIFT_WDT_CLKDIV) + +// CLKDIV is an eight bit counter, but the counter is +// zero indexed, so subtract 1 before setting +#define BFLB_TCDR_CLKDIV ((BFLB_TICK_CLKDIV - 1) << BFLB_SHIFT_WDT_CLKDIV) + +#define BFLB_REG_WMR 0x68 +#define BFLB_MASK_WMR GENMASK(15,0) + +struct bflb_watchdog_device { + struct watchdog_device wdd; + struct device *dev; + void __iomem *regs; +}; + +static inline +struct bflb_watchdog_device *to_bflb_wdd(struct watchdog_device *wdd) +{ + return container_of(wdd, struct bflb_watchdog_device, wdd); +} + +// Access key registers must be written before write +// operations presumably to prevent accidentally enabling +// the watchdog and killing the machine. +static inline int bflb_unlock_watchdog(struct bflb_watchdog_device *bflb_wdd) +{ + writew(BFLB_WFAR_MAGIC, bflb_wdd->regs + BFLB_REG_WFAR); + writew(BFLB_WSAR_MAGIC, bflb_wdd->regs + BFLB_REG_WSAR); + + return 0; +} + +static int bflb_wdt_ping(struct watchdog_device *wdd) +{ + uint32_t reg_val; + struct bflb_watchdog_device *bflb_wdd = to_bflb_wdd(wdd); + + dev_dbg(wdd->parent, "bflb_wdt_ping"); + bflb_unlock_watchdog(bflb_wdd); + reg_val = readl(bflb_wdd->regs + BFLB_REG_WCR); + reg_val |= BFLB_WCR_RESET_COUNTER; + writel(reg_val, bflb_wdd->regs + BFLB_REG_WCR); + + return 0; +}; + +static inline void bflb_wdt_update_timeout_reg(struct watchdog_device *wdd) +{ + unsigned int timeout_ticks; + struct bflb_watchdog_device *bflb_wdd = to_bflb_wdd(wdd); + + bflb_unlock_watchdog(bflb_wdd); + timeout_ticks = wdd->timeout * BFLB_TICKS_PER_SEC; + writew(timeout_ticks, bflb_wdd->regs + BFLB_REG_WMR); +} + +static int bflb_wdt_set_timeout(struct watchdog_device *wdd, + unsigned int timeout) +{ + if (timeout >= wdd->max_timeout) { + dev_warn(wdd->parent, + "timeout %i > max_timeout %i, using max_timeout...", + timeout, wdd->max_timeout); + timeout = wdd->max_timeout; + } + + wdd->timeout = timeout; + + bflb_wdt_update_timeout_reg(wdd); + + dev_dbg(wdd->parent, "bflb_wdt_set_timeout (s=%i tps=%i)", + timeout, BFLB_TICKS_PER_SEC); + + return 0; +} + +static int bflb_wdt_start(struct watchdog_device *wdd) +{ + uint32_t reg_val; + struct bflb_watchdog_device *bflb_wdd = to_bflb_wdd(wdd); + + + // And enable the watchdog + bflb_unlock_watchdog(bflb_wdd); + reg_val = readl(bflb_wdd->regs + BFLB_REG_WMER); + reg_val |= BFLB_WMER_WATCHDOG_ENABLE; + writel(reg_val, bflb_wdd->regs + BFLB_REG_WMER); + + dev_info(wdd->parent, "bflb_wdt_start started..."); + + return 0; +} + +static int bflb_wdt_stop(struct watchdog_device *wdd) +{ + uint32_t reg_val; + struct bflb_watchdog_device *bflb_wdd = to_bflb_wdd(wdd); + + // disable + bflb_unlock_watchdog(bflb_wdd); + reg_val = readl(bflb_wdd->regs + BFLB_REG_WMER); + reg_val &= ~BFLB_WMER_WATCHDOG_ENABLE; + writel(reg_val, bflb_wdd->regs + BFLB_REG_WMER); + + dev_info(wdd->parent, "bflb_wdt_stopped..."); + + return 0; +}; + + +static unsigned int bflb_wdt_timeleft(struct watchdog_device *wdd) +{ + unsigned int used_seconds; + unsigned int remaining_seconds; + unsigned int ticks; + struct bflb_watchdog_device *bflb_wdd = to_bflb_wdd(wdd); + + ticks = readw(bflb_wdd->regs + BFLB_REG_WVR); + + used_seconds = ticks / BFLB_TICKS_PER_SEC; + remaining_seconds = wdd->max_timeout - used_seconds; + dev_dbg(wdd->parent, "bflb_wdt_time left %i (elapsed tick %i, sec %i)", + remaining_seconds, ticks, used_seconds); + + return remaining_seconds; +}; + +static const struct watchdog_info bflb_wdt_info = { + .identity = "bflb_wdt", + .options = WDIOF_SETTIMEOUT | + WDIOF_KEEPALIVEPING | + WDIOF_MAGICCLOSE, +}; + +static const struct watchdog_ops bflb_wdt_ops = { + .start = bflb_wdt_start, + .stop = bflb_wdt_stop, + .ping = bflb_wdt_ping, + .set_timeout = bflb_wdt_set_timeout, + .get_timeleft = bflb_wdt_timeleft, +}; + + +static int __init bflb_wdt_probe(struct platform_device *pdev) +{ + struct bflb_watchdog_device *bflb_wdd; + struct watchdog_device *wdd; + int err; + uint32_t reg_val; + + dev_dbg(&pdev->dev, "bflb_wdt_probe started"); + + bflb_wdd = devm_kzalloc(&pdev->dev, sizeof(*bflb_wdd), GFP_KERNEL); + if (!bflb_wdd) return -ENOMEM; + + bflb_wdd->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(bflb_wdd->regs)) + return PTR_ERR(bflb_wdd->regs); + + wdd = &bflb_wdd->wdd; + + wdd->info = &bflb_wdt_info; + wdd->ops = &bflb_wdt_ops; + + wdd->timeout = BFLB_DEFAULT_TIMEOUT; + wdd->max_timeout = BFLB_MAX_SECS; + wdd->min_timeout = 1; + wdd->parent = &pdev->dev; + + watchdog_stop_on_reboot(wdd); + watchdog_stop_on_unregister(wdd); + watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT); + watchdog_init_timeout(wdd, BFLB_DEFAULT_TIMEOUT, &pdev->dev); + + // Setup registers + + // Set to reboot on watchdog, disable until we start + bflb_unlock_watchdog(bflb_wdd); + reg_val = readl(bflb_wdd->regs + BFLB_REG_WMER); + reg_val &= ~BFLB_WMER_WATCHDOG_ENABLE; + reg_val |= BFLB_WMER_RESET_SOURCE; + writel(reg_val, bflb_wdd->regs + BFLB_REG_WMER); + + // Set to 1K per second clock + reg_val = readl(bflb_wdd->regs + BFLB_REG_TCCR); + reg_val &= ~BFLB_MASK_CS_WDT; + reg_val |= BFLB_TCCR_CS_1K; + writel(reg_val, bflb_wdd->regs + BFLB_REG_TCCR); + + reg_val = readl(bflb_wdd->regs + BFLB_REG_TCDR); + reg_val &= ~BFLB_MASK_TCDR; + reg_val |= BFLB_TCDR_CLKDIV; + writel(reg_val, bflb_wdd->regs + BFLB_REG_TCDR); + + // Set last valid timeout value + bflb_wdt_update_timeout_reg(wdd); + + err = devm_watchdog_register_device(&pdev->dev, wdd); + if (err) return err; + + platform_set_drvdata(pdev, bflb_wdd); + + dev_info(&pdev->dev, "bflb_wdt_probe completed..."); + + return 0; +} + +static int __exit bflb_wdt_remove(struct platform_device *pdev) +{ + dev_info(&pdev->dev, "bflb_wdt_remove removed..."); + + return 0; +} + +static const struct of_device_id bflb_wdt_match[] = { + { + .compatible = "bflb,bl808-wdt", + }, + {}, +}; + +MODULE_DEVICE_TABLE(of, bflb_wdt_match); + +static struct platform_driver bflb_wdt_driver = { + .probe = bflb_wdt_probe, + .remove = bflb_wdt_remove, + .driver = { + .name = "bflb_wdt", + .owner = THIS_MODULE, + .of_match_table = bflb_wdt_match, + .suppress_bind_attrs = true, + }, +}; + + +module_platform_driver(bflb_wdt_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("BL808 Watchdog support"); +MODULE_AUTHOR("Grant Olson Date: Mon, 6 Feb 2023 15:40:33 -0500 Subject: [PATCH 39/39] BL808 Watchdog Support #3/3: Enable Watchdog in bl808_defconfig --- arch/riscv/configs/bl808_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/configs/bl808_defconfig b/arch/riscv/configs/bl808_defconfig index 9e234dcb5ec0d7..f19f0e2e37d994 100644 --- a/arch/riscv/configs/bl808_defconfig +++ b/arch/riscv/configs/bl808_defconfig @@ -211,3 +211,6 @@ CONFIG_DEBUG_TIMEKEEPING=y CONFIG_FUNCTION_ERROR_INJECTION=y # CONFIG_RUNTIME_TESTING_MENU is not set CONFIG_MEMTEST=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +CONFIG_BFLB_WATCHDOG=y