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82 | 82 |
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83 | 83 | interrupt-controller; |
84 | 84 | #interrupt-cells = <2>; |
85 | | - interrupts-extended = <&ipclic BFLB_IPC_SOURCE_M0 |
86 | | - BFLB_IPC_DEVICE_GPIO IRQ_TYPE_EDGE_RISING>; |
| 85 | + interrupts-extended = <&m0ic 44>; |
87 | 86 |
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88 | 87 | sdh_pins: sdh-pins { |
89 | 88 | pins = "GPIO0", "GPIO1", "GPIO2", "GPIO3", "GPIO4", "GPIO5"; |
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98 | 97 | }; |
99 | 98 |
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100 | 99 | uart0: serial@30002000 { |
| 100 | + /*Maps to hardware UART 3*/ |
101 | 101 | compatible = "bflb,bl808-uart"; |
102 | 102 | reg = <0x30002000 0x1000>; |
103 | 103 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; |
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106 | 106 | }; |
107 | 107 |
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108 | 108 | uart1: serial@0x2000AA00 { |
| 109 | + /*Maps to hardware UART 2*/ |
109 | 110 | compatible = "bflb,bl808-uart"; |
110 | 111 | reg = <0x2000AA00 0x0100>; |
111 | | - interrupts-extended = <&ipclic BFLB_IPC_SOURCE_M0 |
112 | | - BFLB_IPC_DEVICE_UART2 |
113 | | - IRQ_TYPE_EDGE_RISING>; |
114 | | - mboxes = <&ipclic BFLB_IPC_SOURCE_M0 BFLB_IPC_DEVICE_UART2>; |
| 112 | + interrupts-extended = <&m0ic 30>; |
115 | 113 | clocks = <&xtal>; |
116 | 114 | status = "disabled"; |
117 | 115 | }; |
118 | 116 |
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119 | 117 | sdhci0: sdhci@20060000 { |
120 | 118 | compatible = "bflb,bl808-sdhci"; |
121 | 119 | reg = <0x20060000 0x100>; |
122 | | - interrupts-extended = <&ipclic BFLB_IPC_SOURCE_M0 |
123 | | - BFLB_IPC_DEVICE_SDHCI |
124 | | - IRQ_TYPE_EDGE_RISING>; |
125 | | - mboxes = <&ipclic BFLB_IPC_SOURCE_M0 BFLB_IPC_DEVICE_SDHCI>; |
| 120 | + interrupts-extended = <&m0ic 17>; |
126 | 121 | clocks = <&sdh>; |
127 | 122 | status = "disabled"; |
128 | 123 | }; |
129 | 124 |
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130 | 125 | ehci0: usb@20072000 { |
131 | 126 | compatible = "generic-ehci"; |
132 | 127 | reg = <0x20072000 0x1000>; |
133 | | - interrupts-extended = <&ipclic BFLB_IPC_SOURCE_M0 |
134 | | - BFLB_IPC_DEVICE_USB |
135 | | - IRQ_TYPE_EDGE_RISING>; |
| 128 | + interrupts-extended = <&m0ic 21>; |
136 | 129 | clocks = <&xtal>; |
137 | 130 | status = "disabled"; |
138 | 131 | }; |
139 | 132 |
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140 | 133 | enet0: emac@20070000 { |
141 | 134 | compatible = "opencores,ethoc"; |
142 | 135 | reg = <0x20070000 0x1000>; |
143 | | - interrupts-extended = <&ipclic BFLB_IPC_SOURCE_M0 |
144 | | - BFLB_IPC_DEVICE_EMAC |
145 | | - IRQ_TYPE_EDGE_RISING>; |
| 136 | + interrupts-extended = <&m0ic 24>; |
146 | 137 | clocks = <&enet>; |
147 | 138 | status = "disabled"; |
148 | 139 | }; |
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160 | 151 | status = "disabled"; |
161 | 152 | }; |
162 | 153 |
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| 154 | + m0ic: mcu-interrupt-controller@20000050 { |
| 155 | + compatible = "bflb,bl808-mcu-irq"; |
| 156 | + reg = <0x20000050 0x18>; |
| 157 | + interrupts = <81 IRQ_TYPE_LEVEL_HIGH>; |
| 158 | + interrupt-controller; |
| 159 | + #address-cells = <0>; |
| 160 | + #interrupt-cells = <1>; |
| 161 | + }; |
| 162 | + |
163 | 163 | plic: interrupt-controller@e0000000 { |
164 | 164 | compatible = "thead,c900-plic"; |
165 | 165 | reg = <0xe0000000 0x4000000>; |
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168 | 168 | interrupt-controller; |
169 | 169 | #address-cells = <0>; |
170 | 170 | #interrupt-cells = <2>; |
171 | | - riscv,ndev = <64>; |
| 171 | + riscv,ndev = <82>; |
172 | 172 | }; |
173 | 173 |
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174 | 174 | clint: timer@e4000000 { |
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