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wip: opcode lookup table
1 parent 2a9dff6 commit e8e8fb0

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3 files changed

+97
-36
lines changed

3 files changed

+97
-36
lines changed

src/core.rs

Lines changed: 51 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,8 @@
1-
use crate::{bus::Bus, rom::Rom};
1+
use crate::{
2+
bus::Bus,
3+
ops::{parse_opcode, OpName},
4+
rom::Rom,
5+
};
26

37
/// CPU (Central Processing Unit)
48
/// The NES uses 2A03, which is a modified version of the 6502 chip.
@@ -223,42 +227,53 @@ impl Cpu {
223227
loop {
224228
callback(self);
225229

226-
let op = self.mem_read(self.pc);
230+
let opcode = self.mem_read(self.pc);
227231
self.pc += 1;
228-
match op {
229-
// LDA
230-
0xA9 => {
231-
self.lda(&AddressingMode::Immediate);
232-
self.pc += 1;
233-
}
234-
0xA5 => {
235-
self.lda(&AddressingMode::ZeroPage);
236-
self.pc += 1;
237-
}
238-
0xB5 => {
239-
self.lda(&AddressingMode::ZeroPageX);
240-
self.pc += 1;
241-
}
242-
0xAD => {
243-
self.lda(&AddressingMode::Absolute);
244-
self.pc += 2;
245-
}
246-
0xBD => {
247-
self.lda(&AddressingMode::AbsoluteX);
248-
self.pc += 2;
249-
}
250-
0xB9 => {
251-
self.lda(&AddressingMode::AbsoluteY);
252-
self.pc += 2;
253-
}
254-
0xA1 => {
255-
self.lda(&AddressingMode::IndirectX);
256-
self.pc += 1;
257-
}
258-
0xB1 => {
259-
self.lda(&AddressingMode::IndirectY);
260-
self.pc += 1;
232+
233+
if let Some(op) = parse_opcode(opcode) {
234+
match op.0 {
235+
OpName::LDA => self.lda(&op.2),
236+
_ => todo!(),
261237
}
238+
self.pc += op.1;
239+
240+
continue;
241+
}
242+
243+
match opcode {
244+
// // LDA
245+
// 0xA9 => {
246+
// self.lda(&AddressingMode::Immediate);
247+
// self.pc += 1;
248+
// }
249+
// 0xA5 => {
250+
// self.lda(&AddressingMode::ZeroPage);
251+
// self.pc += 1;
252+
// }
253+
// 0xB5 => {
254+
// self.lda(&AddressingMode::ZeroPageX);
255+
// self.pc += 1;
256+
// }
257+
// 0xAD => {
258+
// self.lda(&AddressingMode::Absolute);
259+
// self.pc += 2;
260+
// }
261+
// 0xBD => {
262+
// self.lda(&AddressingMode::AbsoluteX);
263+
// self.pc += 2;
264+
// }
265+
// 0xB9 => {
266+
// self.lda(&AddressingMode::AbsoluteY);
267+
// self.pc += 2;
268+
// }
269+
// 0xA1 => {
270+
// self.lda(&AddressingMode::IndirectX);
271+
// self.pc += 1;
272+
// }
273+
// 0xB1 => {
274+
// self.lda(&AddressingMode::IndirectY);
275+
// self.pc += 1;
276+
// }
262277

263278
// LDX
264279
0xA2 => {
@@ -806,7 +821,7 @@ impl Cpu {
806821
0xF8 => self.set_flag(Flag::Decimal, true),
807822

808823
_ => {
809-
println!("Op {:#04x} not yet implemented", op);
824+
println!("Op {:#04x} not yet implemented", opcode);
810825
todo!();
811826
}
812827
}

src/main.rs

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@ use std::time::Duration;
77

88
mod bus;
99
mod core;
10+
mod ops;
1011
mod rom;
1112

1213
use rand::random;

src/ops.rs

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,45 @@
1+
use core::fmt;
2+
3+
use crate::core::AddressingMode;
4+
5+
// TODO: Stringify these
6+
#[derive(Debug, PartialEq, Eq)]
7+
pub enum OpName {
8+
LDA,
9+
10+
TODO, // TODO
11+
}
12+
13+
impl fmt::Display for OpName {
14+
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
15+
write!(f, "{:?}", self)
16+
}
17+
}
18+
19+
pub struct Op(pub OpName, pub u16, pub AddressingMode);
20+
21+
pub fn parse_opcode(code: u8) -> Option<Op> {
22+
let op = match code {
23+
0xA9 => Op(OpName::LDA, 2, AddressingMode::Immediate),
24+
0xA5 => Op(OpName::LDA, 2, AddressingMode::ZeroPage),
25+
0xB5 => Op(OpName::LDA, 2, AddressingMode::ZeroPageX),
26+
0xAD => Op(OpName::LDA, 3, AddressingMode::Absolute),
27+
0xBD => Op(OpName::LDA, 3, AddressingMode::AbsoluteX),
28+
0xB9 => Op(OpName::LDA, 3, AddressingMode::AbsoluteY),
29+
0xA1 => Op(OpName::LDA, 2, AddressingMode::IndirectX),
30+
0xB1 => Op(OpName::LDA, 2, AddressingMode::IndirectY),
31+
// 0xA1 => Op(OpName::LDA, 3, AddressingMode::AbsoluteY),
32+
// 0xB1 => Op(OpName::LDA, 3, AddressingMode::AbsoluteY),
33+
// 0xA2 => {
34+
// self.ldx(&AddressingMode::Immediate);
35+
// self.pc += 1;
36+
// }
37+
_ => Op(OpName::TODO, 0, AddressingMode::None),
38+
};
39+
40+
if op.0 == OpName::TODO {
41+
None
42+
} else {
43+
Some(op)
44+
}
45+
}

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