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get tests passing given new Rom setup
1 parent c07d780 commit 578e689

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3 files changed

+73
-50
lines changed

3 files changed

+73
-50
lines changed

src/core.rs

+71-47
Original file line numberDiff line numberDiff line change
@@ -192,18 +192,16 @@ impl Cpu {
192192
// for (i, val) in program.iter().enumerate() {
193193
// self.mem_write((CPU_START + i) as u16, *val);
194194
// }
195-
let rom = Rom::new(&program);
195+
let rom = Rom::new_test_rom(program);
196196
self.set_bus(Bus::new(rom));
197-
198-
// TODO: update this to get unit tests working
199197
// self.mem_write_u16(0xFFFC, CPU_START as u16);
200198
}
201199

202-
// pub fn load_rom(&mut self, rom: Rom) {
203-
// // Load turns program into ROM, then sets the bus
204-
// self.set_bus(Bus::new(rom));
205-
// // self.mem_write_u16(0xFFFC, CPU_START as u16);
206-
// }
200+
pub fn load_rom(&mut self, rom: Rom) {
201+
// Load turns program into ROM, then sets the bus
202+
self.set_bus(Bus::new(rom));
203+
// self.mem_write_u16(0xFFFC, CPU_START as u16);
204+
}
207205

208206
fn load_and_run(&mut self, program: Vec<u8>) {
209207
self.load(program);
@@ -1314,20 +1312,23 @@ mod tests {
13141312
}
13151313

13161314
#[test]
1317-
fn test_lda_from_memory() {
1315+
fn test_0xa5_lda_from_memory() {
13181316
let mut cpu = Cpu::new();
1317+
cpu.load(vec![0xa5, 0x10, 0x00]);
1318+
cpu.reset();
13191319
cpu.mem_write(0x10, 0x55);
1320-
assert_eq!(cpu.mem_read(0x10), 0x55);
1321-
cpu.load_and_run(vec![0xa5, 0x10, 0x00]);
1320+
cpu.run();
13221321

13231322
assert_eq!(cpu.a, 0x55);
13241323
}
13251324

13261325
#[test]
1327-
fn test_lda_absolute() {
1326+
fn test_0xad_lda_absolute() {
13281327
let mut cpu = Cpu::new();
1328+
cpu.load(vec![0xad, 0x03, 0x10, 0x00]);
1329+
cpu.reset();
13291330
cpu.mem_write(0x1003, 0x99);
1330-
cpu.load_and_run(vec![0xad, 0x03, 0x10, 0x00]);
1331+
cpu.run();
13311332

13321333
assert_eq!(cpu.a, 0x99);
13331334
}
@@ -1460,9 +1461,10 @@ mod tests {
14601461
#[test]
14611462
fn test_jmp() {
14621463
let mut cpu = Cpu::new();
1463-
let jump_dest: u16 = (CPU_START as u16) + 333;
1464-
cpu.mem_write_u16((CPU_START as u16) + 1, jump_dest);
1465-
cpu.load_and_run(vec![0x20]);
1464+
let jump_dest: u16 = (PRG_ROM_START + CPU_START as u16) + 333;
1465+
let lo = (jump_dest & 0xff) as u8;
1466+
let hi = (jump_dest >> 8) as u8;
1467+
cpu.load_and_run(vec![0x20, lo, hi]);
14661468

14671469
// expect that you jump to jump_dest, then pc steps forward one more time while reading a BRK
14681470
// (since everything is 0x00 BRK by default)
@@ -1475,19 +1477,19 @@ mod tests {
14751477

14761478
let jmp_opcode = 0x20;
14771479
let rts_opcode = 0x60;
1478-
cpu.load(vec![jmp_opcode]);
1479-
cpu.reset();
14801480

14811481
let jump_dest: u16 = (CPU_START as u16) + 123;
1482-
cpu.mem_write_u16((CPU_START as u16) + 1, jump_dest);
1483-
1482+
let lo = (jump_dest & 0xff) as u8;
1483+
let hi = (jump_dest >> 8) as u8;
1484+
cpu.load(vec![jmp_opcode, lo, hi]);
1485+
cpu.reset();
14841486
cpu.mem_write(jump_dest, rts_opcode);
14851487

14861488
cpu.run();
14871489
// +4 =
14881490
// [0 1 2 3 ]
14891491
// [jmp, addr, addr+1, brk] .. and +1 as last pc+1 after brek
1490-
assert_eq!(cpu.pc, (CPU_START as u16) + 4);
1492+
assert_eq!(cpu.pc, (PRG_ROM_START + CPU_START as u16) + 4);
14911493
}
14921494

14931495
#[test]
@@ -1532,14 +1534,19 @@ mod tests {
15321534
#[test]
15331535
fn test_0xee_inc_absolute() {
15341536
let mut cpu = Cpu::new();
1535-
let to_inc = 0x01;
1536-
let to_inc_addr = CPU_START as u16 + 4;
1537-
let inc_param_addr = CPU_START as u16 + 1;
1538-
cpu.load(vec![0xee, 0x00, 0x00, 0x00, to_inc]);
1537+
1538+
let inst = 0xee;
1539+
1540+
let target_val = 3;
1541+
let target_address = 0x12; // needs to be in CPU
1542+
1543+
let hi = (target_address >> 8) as u8;
1544+
let lo = (target_address & 0x00ff) as u8;
1545+
cpu.load(vec![inst, lo, hi, 0x00]);
1546+
cpu.mem_write(target_address, target_val);
15391547
cpu.reset();
1540-
cpu.mem_write_u16(inc_param_addr, to_inc_addr);
15411548
cpu.run();
1542-
assert_eq!(cpu.mem_read(to_inc_addr), 0x02);
1549+
assert_eq!(cpu.mem_read(target_address), 4);
15431550
}
15441551

15451552
#[test]
@@ -1586,15 +1593,22 @@ mod tests {
15861593
let consumed_brk_op = 1;
15871594
assert_eq!(
15881595
cpu.pc,
1589-
CPU_START as u16 + consumed_bpl_op + displacement as u16 + consumed_brk_op
1596+
PRG_ROM_START
1597+
+ CPU_START as u16
1598+
+ consumed_bpl_op
1599+
+ displacement as u16
1600+
+ consumed_brk_op
15901601
);
15911602

15921603
let mut cpu = Cpu::new();
15931604
cpu.load(program);
15941605
cpu.reset();
15951606
cpu.set_flag(flag, !branch_if);
15961607
cpu.run();
1597-
assert_eq!(cpu.pc, CPU_START as u16 + consumed_bpl_op + consumed_brk_op);
1608+
assert_eq!(
1609+
cpu.pc,
1610+
PRG_ROM_START + CPU_START as u16 + consumed_bpl_op + consumed_brk_op
1611+
);
15981612
}
15991613
}
16001614

@@ -1626,14 +1640,17 @@ mod tests {
16261640
#[test]
16271641
fn test_0x4e_lsr_shifts_absolute() {
16281642
let mut cpu = Cpu::new();
1629-
let to_lsr = 0b1000_1001;
1630-
let to_lsr_addr = CPU_START as u16 + 4;
1631-
let lsr_param_addr = CPU_START as u16 + 1;
1632-
cpu.load(vec![0x4e, 0x00, 0x00, 0x00, to_lsr]);
1643+
1644+
let target_val = 0b1000_1001;
1645+
let target_address = 0x12; // needs to be in CPU
1646+
1647+
let hi = (target_address >> 8) as u8;
1648+
let lo = (target_address & 0x00ff) as u8;
1649+
cpu.load(vec![0x4e, lo, hi, 0x00]);
1650+
cpu.mem_write(target_address, target_val);
16331651
cpu.reset();
1634-
cpu.mem_write_u16(lsr_param_addr, to_lsr_addr);
16351652
cpu.run();
1636-
assert_eq!(cpu.mem_read(to_lsr_addr), 0b0100_0100);
1653+
assert_eq!(cpu.mem_read(target_address), 0b0100_0100);
16371654
assert!(cpu.get_flag(Flag::Carry));
16381655
}
16391656

@@ -1642,7 +1659,7 @@ mod tests {
16421659
let mut cpu = Cpu::new();
16431660
let program = vec![0xea, 0xea, 0xea, 0xea, 0x00];
16441661
cpu.load_and_run(program.clone());
1645-
let end = (CPU_START + program.len()) as u16;
1662+
let end = PRG_ROM_START + (CPU_START + program.len()) as u16;
16461663
assert_eq!(cpu.pc, end);
16471664
}
16481665

@@ -1723,15 +1740,19 @@ mod tests {
17231740
#[test]
17241741
fn test_0xce_dec_absolute() {
17251742
let mut cpu = Cpu::new();
1726-
let dec = 0xce;
1727-
let to_dec = 3;
1728-
let to_dec_addr = CPU_START as u16 + 4;
1729-
let dec_param_addr = CPU_START as u16 + 1;
1730-
cpu.load(vec![dec, 0x00, 0x00, 0x00, to_dec]);
1743+
1744+
let inst = 0xce;
1745+
1746+
let target_val = 3;
1747+
let target_address = 0x12; // needs to be in CPU
1748+
1749+
let hi = (target_address >> 8) as u8;
1750+
let lo = (target_address & 0x00ff) as u8;
1751+
cpu.load(vec![inst, lo, hi, 0x00]);
1752+
cpu.mem_write(target_address, target_val);
17311753
cpu.reset();
1732-
cpu.mem_write_u16(dec_param_addr, to_dec_addr);
17331754
cpu.run();
1734-
assert_eq!(cpu.mem_read(to_dec_addr), 2);
1755+
assert_eq!(cpu.mem_read(target_address), 2);
17351756
}
17361757

17371758
#[test]
@@ -1760,12 +1781,15 @@ mod tests {
17601781
#[test]
17611782
fn test_0x0e_asl_shifts_absolute() {
17621783
let mut cpu = Cpu::new();
1784+
17631785
let to_lsr = 0b1000_1001;
1764-
let to_lsr_addr = CPU_START as u16 + 4;
1765-
let lsr_param_addr = CPU_START as u16 + 1;
1766-
cpu.load(vec![0x0e, 0x00, 0x00, 0x00, to_lsr]);
1786+
let to_lsr_addr = 0x12; // needs to be in CPU
1787+
1788+
let hi = (to_lsr_addr >> 8) as u8;
1789+
let lo = (to_lsr_addr & 0x00ff) as u8;
1790+
cpu.load(vec![0x0e, lo, hi, 0x00]);
1791+
cpu.mem_write(to_lsr_addr, to_lsr);
17671792
cpu.reset();
1768-
cpu.mem_write_u16(lsr_param_addr, to_lsr_addr);
17691793
cpu.run();
17701794
assert_eq!(cpu.mem_read(to_lsr_addr), 0b0001_0010);
17711795
assert!(cpu.get_flag(Flag::Carry));

src/main.rs

+1-2
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,6 @@ mod bus;
99
mod core;
1010
mod rom;
1111

12-
use bus::Bus;
1312
use rand::random;
1413
use rom::Rom;
1514
use sdl2::event::Event;
@@ -39,7 +38,7 @@ fn main() -> Result<(), Box<dyn Error>> {
3938
let program = fs::read("roms/snake.nes").unwrap();
4039

4140
let mut cpu = Cpu::new();
42-
cpu.load(program);
41+
cpu.load_rom(Rom::new(&program));
4342
cpu.reset();
4443
cpu.run_with_callback(move |cpu| {
4544
// read user input and write it to mem[0xFF]

src/rom.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@ impl Rom {
7878
}
7979

8080
pub fn new_test() -> Self {
81-
let mut prg_rom = [0; 0x8000].to_vec();
81+
let prg_rom = [0; 0x8000].to_vec();
8282
// prg_rom[0xFFFC - 0x8000] = CPU_START
8383
// prg_rom[0xFFFC - 0x8000] = CPU_START
8484
Self {

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