diff --git a/litespi/clkgen.py b/litespi/clkgen.py
index c1ab65d..12d0ea9 100644
--- a/litespi/clkgen.py
+++ b/litespi/clkgen.py
@@ -30,7 +30,7 @@ class DDRLiteSPIClkGen(Module, AutoDoc, ModuleDoc):
     def __init__(self, pads):
         self.en         = en         = Signal()
 
-        self.specials += DDROutput(i1=en, i2=0, o=pads.clk)
+        self.specials += DDROutput(i1=0, i2=en, o=pads.clk)
 
 
 class LiteSPIClkGen(Module, AutoDoc, ModuleDoc):
diff --git a/litespi/phy/generic_ddr.py b/litespi/phy/generic_ddr.py
index ee847b2..d29aa45 100644
--- a/litespi/phy/generic_ddr.py
+++ b/litespi/phy/generic_ddr.py
@@ -86,18 +86,16 @@ def __init__(self, pads, flash, cs_delay, extra_latency=0):
         self.comb += pads.cs_n.eq(~cs_enable)
 
         # I/Os.
-        data_bits = 32
-
-        dq_o  = Array([Signal(len(pads.dq)) for _ in range(2)])
-        dq_i  = Array([Signal(len(pads.dq)) for _ in range(2)])
-        dq_oe = Array([Signal(len(pads.dq)) for _ in range(2)])
+        dq_o  = Signal(len(pads.dq))
+        dq_i  = Signal(len(pads.dq))
+        dq_oe = Signal(len(pads.dq))
 
         for i in range(len(pads.dq)):
             self.specials += DDRTristate(
                 io  = pads.dq[i],
-                o1  =  dq_o[0][i],  o2 =  dq_o[1][i],
-                oe1 = dq_oe[0][i], oe2 = dq_oe[1][i],
-                i1  =  dq_i[0][i],  i2 =  dq_i[1][i]
+                o1  =  dq_o[i],  o2 =  dq_o[i], # Output on rising edge: Same data.
+                oe1 = dq_oe[i], oe2 = dq_oe[i], # Output on rising edge: Same data.
+                i1  = Signal(),  i2 =  dq_i[i]  # Sampling on falling edge.
             )
 
         # Data Shift Registers.
@@ -110,20 +108,18 @@ def __init__(self, pads, flash, cs_delay, extra_latency=0):
 
         # Data Out Shift.
         self.comb += [
-            dq_oe[1].eq(sink.mask),
+            dq_oe.eq(sink.mask),
             Case(sink.width, {
-                1:  dq_o[1].eq(sr_out[-1:]),
-                2:  dq_o[1].eq(sr_out[-2:]),
-                4:  dq_o[1].eq(sr_out[-4:]),
-                8:  dq_o[1].eq(sr_out[-8:]),
+                1:  dq_o.eq(sr_out[-1:]),
+                2:  dq_o.eq(sr_out[-2:]),
+                4:  dq_o.eq(sr_out[-4:]),
+                8:  dq_o.eq(sr_out[-8:]),
             })
         ]
         self.sync += If(sr_out_load,
             sr_out.eq(sink.data << (len(sink.data) - sink.len))
         )
         self.sync += If(sr_out_shift,
-            dq_oe[0].eq(dq_oe[1]),
-            dq_o[0].eq(dq_o[1]),
             Case(sink.width, {
                 1 : sr_out.eq(Cat(Signal(1), sr_out)),
                 2 : sr_out.eq(Cat(Signal(2), sr_out)),
@@ -135,18 +131,16 @@ def __init__(self, pads, flash, cs_delay, extra_latency=0):
         # Data In Shift.
         self.sync += If(sr_in_shift,
             Case(sink.width, {
-                1 : sr_in.eq(Cat(dq_i[0][1],  sr_in)), # 1: pads.miso
-                2 : sr_in.eq(Cat(dq_i[0][:2], sr_in)),
-                4 : sr_in.eq(Cat(dq_i[0][:4], sr_in)),
-                8 : sr_in.eq(Cat(dq_i[0][:8], sr_in)),
+                1 : sr_in.eq(Cat(dq_i[1],  sr_in)), # 1: pads.miso
+                2 : sr_in.eq(Cat(dq_i[:2], sr_in)),
+                4 : sr_in.eq(Cat(dq_i[:4], sr_in)),
+                8 : sr_in.eq(Cat(dq_i[:8], sr_in)),
             })
         )
 
         # FSM.
         self.submodules.fsm = fsm = FSM(reset_state="WAIT-CMD-DATA")
         fsm.act("WAIT-CMD-DATA",
-            # Stop Clk.
-            NextValue(clkgen.en, 0),
             # Wait for CS and a CMD from the Core.
             If(cs_enable & sink.valid,
                 # Load Shift Register Count/Data Out.
@@ -159,7 +153,7 @@ def __init__(self, pads, flash, cs_delay, extra_latency=0):
 
         fsm.act("XFER",
             # Generate Clk.
-            NextValue(clkgen.en, 1),
+            clkgen.en.eq(1),
 
             # Data In Shift.
             sr_in_shift.eq(1),
@@ -176,9 +170,6 @@ def __init__(self, pads, flash, cs_delay, extra_latency=0):
             ),
         )
         fsm.act("XFER-END",
-            # Stop Clk.
-            NextValue(clkgen.en, 0),
-
             # Data In Shift.
             sr_in_shift.eq(1),
 
diff --git a/litespi/phy/generic_sdr.py b/litespi/phy/generic_sdr.py
index a28d26f..f16edc6 100644
--- a/litespi/phy/generic_sdr.py
+++ b/litespi/phy/generic_sdr.py
@@ -110,9 +110,6 @@ def __init__(self, pads, flash, device, clock_domain, default_divisor, cs_delay)
         self.comb += pads.cs_n.eq(~cs_enable)
 
         # I/Os.
-        data_bits = 32
-        cmd_bits  = 8
-
         dq_o  = Signal(len(pads.dq))
         dq_i  = Signal(len(pads.dq))
         dq_oe = Signal(len(pads.dq))