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| 1 | +/* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | +/* |
| 3 | + * Copyright (c) 2021 - 2022, Shanghai Yunsilicon Technology Co., Ltd. |
| 4 | + * All rights reserved. |
| 5 | + */ |
| 6 | + |
| 7 | +#ifndef XSC_ABI_USER_H |
| 8 | +#define XSC_ABI_USER_H |
| 9 | + |
| 10 | +#include <linux/types.h> |
| 11 | +#include <linux/if_ether.h> /* For ETH_ALEN. */ |
| 12 | +#include <rdma/ib_user_ioctl_verbs.h> |
| 13 | + |
| 14 | +enum { |
| 15 | + XSC_WQ_FLAG_SIGNATURE = 1 << 0, |
| 16 | +}; |
| 17 | + |
| 18 | +/* Make sure that all structs defined in this file remain laid out so |
| 19 | + * that they pack the same way on 32-bit and 64-bit architectures (to |
| 20 | + * avoid incompatibility between 32-bit userspace and 64-bit kernels). |
| 21 | + * In particular do not use pointer types -- pass pointers in __u64 |
| 22 | + * instead. |
| 23 | + */ |
| 24 | + |
| 25 | +struct xsc_ib_alloc_ucontext_req { |
| 26 | + __u32 rsvd0; |
| 27 | + __u32 rsvd1; |
| 28 | +}; |
| 29 | + |
| 30 | +enum xsc_user_cmds_supp_uhw { |
| 31 | + XSC_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0, |
| 32 | + XSC_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1, |
| 33 | +}; |
| 34 | + |
| 35 | +struct xsc_ib_alloc_ucontext_resp { |
| 36 | + __u32 qp_tab_size; |
| 37 | + __u32 cache_line_size; |
| 38 | + __u16 max_sq_desc_sz; |
| 39 | + __u16 max_rq_desc_sz; |
| 40 | + __u32 max_send_wr; |
| 41 | + __u32 max_recv_wr; |
| 42 | + __u16 num_ports; |
| 43 | + __u16 device_id; |
| 44 | + __aligned_u64 qpm_tx_db; |
| 45 | + __aligned_u64 qpm_rx_db; |
| 46 | + __aligned_u64 cqm_next_cid_reg; |
| 47 | + __aligned_u64 cqm_armdb; |
| 48 | + __u32 send_ds_num; |
| 49 | + __u32 recv_ds_num; |
| 50 | + __u32 cmds_supp_uhw; |
| 51 | +}; |
| 52 | + |
| 53 | +struct xsc_ib_create_qp { |
| 54 | + __aligned_u64 buf_addr; |
| 55 | + __aligned_u64 db_addr; |
| 56 | + __u32 sq_wqe_count; |
| 57 | + __u32 rq_wqe_count; |
| 58 | + __u32 rq_wqe_shift; |
| 59 | + __u32 flags; |
| 60 | +}; |
| 61 | + |
| 62 | +struct xsc_ib_create_qp_resp { |
| 63 | + __u32 bfreg_index; |
| 64 | + __u32 resv; |
| 65 | +}; |
| 66 | + |
| 67 | +struct xsc_ib_create_cq { |
| 68 | + __aligned_u64 buf_addr; |
| 69 | + __u32 cqe_size; |
| 70 | +}; |
| 71 | + |
| 72 | +struct xsc_ib_create_cq_resp { |
| 73 | + __u32 cqn; |
| 74 | + __u32 reserved; |
| 75 | +}; |
| 76 | + |
| 77 | +struct xsc_ib_create_ah_resp { |
| 78 | + __u32 response_length; |
| 79 | + __u8 dmac[ETH_ALEN]; |
| 80 | + __u8 reserved[6]; |
| 81 | +}; |
| 82 | + |
| 83 | +struct xsc_ib_alloc_pd_resp { |
| 84 | + __u32 pdn; |
| 85 | +}; |
| 86 | + |
| 87 | +struct xsc_ib_tso_caps { |
| 88 | + __u32 max_tso; /* Maximum tso payload size in bytes */ |
| 89 | + |
| 90 | + /* Corresponding bit will be set if qp type from |
| 91 | + * 'enum ib_qp_type' is supported, e.g. |
| 92 | + * supported_qpts |= 1 << IB_QPT_UD |
| 93 | + */ |
| 94 | + __u32 supported_qpts; |
| 95 | +}; |
| 96 | + |
| 97 | +/* RX Hash function flags */ |
| 98 | +enum xsc_rx_hash_function_flags { |
| 99 | + XSC_RX_HASH_FUNC_TOEPLITZ = 1 << 0, |
| 100 | +}; |
| 101 | + |
| 102 | +/* |
| 103 | + * RX Hash flags, these flags allows to set which incoming packet's field should |
| 104 | + * participates in RX Hash. Each flag represent certain packet's field, |
| 105 | + * when the flag is set the field that is represented by the flag will |
| 106 | + * participate in RX Hash calculation. |
| 107 | + * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP |
| 108 | + * and *TCP and *UDP flags can't be enabled together on the same QP. |
| 109 | + */ |
| 110 | +enum xsc_rx_hash_fields { |
| 111 | + XSC_RX_HASH_SRC_IPV4 = 1 << 0, |
| 112 | + XSC_RX_HASH_DST_IPV4 = 1 << 1, |
| 113 | + XSC_RX_HASH_SRC_IPV6 = 1 << 2, |
| 114 | + XSC_RX_HASH_DST_IPV6 = 1 << 3, |
| 115 | + XSC_RX_HASH_SRC_PORT_TCP = 1 << 4, |
| 116 | + XSC_RX_HASH_DST_PORT_TCP = 1 << 5, |
| 117 | + XSC_RX_HASH_SRC_PORT_UDP = 1 << 6, |
| 118 | + XSC_RX_HASH_DST_PORT_UDP = 1 << 7, |
| 119 | + XSC_RX_HASH_IPSEC_SPI = 1 << 8, |
| 120 | + /* Save bits for future fields */ |
| 121 | + XSC_RX_HASH_INNER = (1UL << 31), |
| 122 | +}; |
| 123 | + |
| 124 | +struct xsc_ib_rss_caps { |
| 125 | + __aligned_u64 rx_hash_fields_mask; /* enum xsc_rx_hash_fields */ |
| 126 | + __u8 rx_hash_function; /* enum xsc_rx_hash_function_flags */ |
| 127 | + __u8 reserved[7]; |
| 128 | +}; |
| 129 | + |
| 130 | +enum xsc_ib_cqe_comp_res_format { |
| 131 | + XSC_IB_CQE_RES_FORMAT_HASH = 1 << 0, |
| 132 | + XSC_IB_CQE_RES_FORMAT_CSUM = 1 << 1, |
| 133 | + XSC_IB_CQE_RES_FORMAT_CSUM_STRIDX = 1 << 2, |
| 134 | +}; |
| 135 | + |
| 136 | +struct xsc_ib_cqe_comp_caps { |
| 137 | + __u32 max_num; |
| 138 | + __u32 supported_format; /* enum xsc_ib_cqe_comp_res_format */ |
| 139 | +}; |
| 140 | + |
| 141 | +enum xsc_ib_packet_pacing_cap_flags { |
| 142 | + XSC_IB_PP_SUPPORT_BURST = 1 << 0, |
| 143 | +}; |
| 144 | + |
| 145 | +struct xsc_packet_pacing_caps { |
| 146 | + __u32 qp_rate_limit_min; |
| 147 | + __u32 qp_rate_limit_max; /* In kpbs */ |
| 148 | + |
| 149 | + /* Corresponding bit will be set if qp type from |
| 150 | + * 'enum ib_qp_type' is supported, e.g. |
| 151 | + * supported_qpts |= 1 << IB_QPT_RAW_PACKET |
| 152 | + */ |
| 153 | + __u32 supported_qpts; |
| 154 | + __u8 cap_flags; /* enum xsc_ib_packet_pacing_cap_flags */ |
| 155 | + __u8 reserved[3]; |
| 156 | +}; |
| 157 | + |
| 158 | +struct xsc_ib_sw_parsing_caps { |
| 159 | + __u32 sw_parsing_offloads; /* enum xsc_ib_sw_parsing_offloads */ |
| 160 | + |
| 161 | + /* Corresponding bit will be set if qp type from |
| 162 | + * 'enum ib_qp_type' is supported, e.g. |
| 163 | + * supported_qpts |= 1 << IB_QPT_RAW_PACKET |
| 164 | + */ |
| 165 | + __u32 supported_qpts; |
| 166 | +}; |
| 167 | + |
| 168 | +struct xsc_ib_striding_rq_caps { |
| 169 | + __u32 min_single_stride_log_num_of_bytes; |
| 170 | + __u32 max_single_stride_log_num_of_bytes; |
| 171 | + __u32 min_single_wqe_log_num_of_strides; |
| 172 | + __u32 max_single_wqe_log_num_of_strides; |
| 173 | + |
| 174 | + /* Corresponding bit will be set if qp type from |
| 175 | + * 'enum ib_qp_type' is supported, e.g. |
| 176 | + * supported_qpts |= 1 << IB_QPT_RAW_PACKET |
| 177 | + */ |
| 178 | + __u32 supported_qpts; |
| 179 | + __u32 reserved; |
| 180 | +}; |
| 181 | + |
| 182 | +enum xsc_ib_query_dev_resp_flags { |
| 183 | + /* Support 128B CQE compression */ |
| 184 | + XSC_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0, |
| 185 | + XSC_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1, |
| 186 | +}; |
| 187 | + |
| 188 | +struct xsc_ib_query_device_resp { |
| 189 | + __u32 comp_mask; |
| 190 | + __u32 response_length; |
| 191 | + struct xsc_ib_tso_caps tso_caps; |
| 192 | + struct xsc_ib_rss_caps rss_caps; |
| 193 | + struct xsc_ib_cqe_comp_caps cqe_comp_caps; |
| 194 | + struct xsc_packet_pacing_caps packet_pacing_caps; |
| 195 | + __u32 xsc_ib_support_multi_pkt_send_wqes; |
| 196 | + __u32 flags; /* Use enum xsc_ib_query_dev_resp_flags */ |
| 197 | + struct xsc_ib_sw_parsing_caps sw_parsing_caps; |
| 198 | + struct xsc_ib_striding_rq_caps striding_rq_caps; |
| 199 | + __u32 tunnel_offloads_caps; /* enum xsc_ib_tunnel_offloads */ |
| 200 | + __u32 reserved; |
| 201 | +}; |
| 202 | + |
| 203 | +struct xsc_ib_modify_qp_resp { |
| 204 | + __u32 response_length; |
| 205 | + __u32 dctn; |
| 206 | +}; |
| 207 | + |
| 208 | +#endif /* XSC_ABI_USER_H */ |
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