Prepare for publishing

Author: jurihock

.gitignore

@@ -1,5 +1,10 @@
 .*/
+
 *.py[cod]
+__pycache__/
+
+*.egg-info/
+dist/
 
 .DS_Store
 Thumbs.db

README.md

@@ -2,7 +2,7 @@
 
 The [Basler AG](https://www.baslerweb.com) company provides a [TCL](https://docs.baslerweb.com/visualapplets/files/documents/TCL/Content/4_VisualApplets/TCL/Intro.htm) scripting engine to automatize the creation of [VisualApplets](https://www.baslerweb.com/en/products/frame-grabber-portfolio/visualapplets) designs (a former Silicon Software GmbH technology), which is a nice and useful feature but not nice enough, in my opinion.
 
-The main idea of the **[visualapplets.py](visualapplets.py)** project is to introduce an additional scripting abstraction and to script the creation of TCL scripts via Python.
+The main idea of the **[visualapplets.py](https://github.com/jurihock/visualapplets.py/blob/main/visualapplets.py)** project is to introduce an additional scripting abstraction and to script the creation of TCL scripts via Python.
 
 Huh, to script a script? Too much meta? Let's study an example...
 
@@ -12,7 +12,7 @@ In this example we will implement the [ReLU](https://en.wikipedia.org/wiki/Recti
 
 Just for practical reasons, we encapsulate the operator logic in a `HierarchicalBox`. So it can be reused many times in a VisualApplets design. Consequently we also create a class in our Python script, for the same purpose of course.
 
-We begin with the first part of the Python script [example.py](example.py):
+We begin with the first part of the Python script [example.py](https://github.com/jurihock/visualapplets.py/blob/main/example.py):
 
 ```python
 import visualapplets as VA
@@ -59,7 +59,7 @@ design = VA.Design('mE5-MA-VCLx', 'Example')
 example = Example(design, 'Example', x=1, y=2)
 ```
 
-Finally import the generated [example.tcl](example.tcl) file in the VisualApplets IDE or execute something like this in the TCL console:
+Finally import the generated [example.tcl](https://github.com/jurihock/visualapplets.py/raw/main/example.tcl) file in the VisualApplets IDE or execute something like this in the TCL console:
 
 ```
 CloseDesign Discard
@@ -68,7 +68,7 @@ source "C:/foo/bar/example.tcl"
 
 The resulting design should look similar to this one:
 
-![](example.png)
+![](https://github.com/jurihock/visualapplets.py/raw/main/example.png)
 
 Obviously there are more possibilities to implement the ReLU function. You can replace the fallback value by the `XOR` result or also only check the sign bit of the input value. But the preferred way is probably to utilize the built-in `ClipLow` operator instead... ;-)
 
@@ -93,7 +93,7 @@ Furthermore each module instance provides an access to
 * module port descriptor via `()` accessor and
 * module parameter descriptor via `[]` accessor.
 
-Modules with unambiguous assignable output-input port combination can be directly connected without specifying the source and destination port, like `CONST - BRANCH`. Reciprocal connection `BRANCH - CONST` is not necessarily unambiguous, since the branch can have multiple outputs, so you have to specify which one.
+Modules with unambiguous assignable output-input port combination can be directly connected without specifying the source and destination port, like `CONST - BRANCH`. Reciprocal connection `BRANCH - CONST` is not necessarily unambiguous, since the branch may have multiple outputs, so you have to specify which one.
 
 ## Port
 

pyproject.toml

@@ -0,0 +1,3 @@
+[build-system]
+requires = ["setuptools>=42", "wheel"]
+build-backend = "setuptools.build_meta"

setup.cfg

@@ -0,0 +1,51 @@
+[metadata]
+name = visualapplets
+version = attr: visualapplets.__version__
+author = Juergen Hock
+author_email = [email protected]
+url = https://github.com/jurihock/visualapplets.py
+description = Python bindings for Basler's VisualApplets TCL script generation.
+long_description = file: README.md
+long_description_content_type = text/markdown
+license = MPL-2.0
+license_file = LICENSE
+keywords =
+    automation
+    basler
+    camera
+    cameralink
+    dsp
+    fpga
+    framegrabber
+    gigevision
+    high-performance
+    image-processing
+    kintex7
+    machine-vision
+    microenable
+    prototyping
+    python
+    real-time
+    siso
+    tcl
+    visualapplets
+    xilinx
+classifiers =
+    Development Status :: 4 - Beta
+    Intended Audience :: Developers
+    Intended Audience :: Manufacturing
+    Intended Audience :: Science/Research
+    License :: OSI Approved :: Mozilla Public License 2.0 (MPL 2.0)
+    Programming Language :: Python :: 3
+    Programming Language :: Tcl
+    Topic :: Scientific/Engineering
+    Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
+    Topic :: Scientific/Engineering :: Image Processing
+    Topic :: Scientific/Engineering :: Visualization
+    Topic :: Software Development
+    Topic :: Software Development :: Code Generators
+    Topic :: System :: Hardware
+    Topic :: Utilities
+
+[options]
+py_modules = visualapplets

visualapplets.py

@@ -17,6 +17,9 @@
 """
 
 
+__version__ = '1.0'
+
+
 operators = {
     'ADD': {
         'I': lambda n: f'I{n:03d}',
@@ -117,9 +120,6 @@ def print(self, what):
             self.file.write('\n')
 
 
-printer = StdoutPrinter()
-
-
 class Grid:
 
     def x(self, index):
@@ -131,9 +131,6 @@ def y(self, index):
         return ((index or 0) * 40 + 3) * 2 - (1 * 40 + 3)
 
 
-grid = Grid()
-
-
 class Design:
 
     def __init__(self, platform, name=None, version=None, description=None):
@@ -426,6 +423,5 @@ def stringify(value):
         assert False
 
 
-if __name__ == '__main__':
-
-    pass
+grid = Grid()
+printer = StdoutPrinter()