diff --git a/synthesis/build_defs.bzl b/synthesis/build_defs.bzl
index fbdbb062..e3471d0e 100644
--- a/synthesis/build_defs.bzl
+++ b/synthesis/build_defs.bzl
@@ -363,6 +363,11 @@ synthesize_rtl = rule(
         "deps": attr.label_list(
             providers = [[VerilogInfo], [UhdmInfo]],
         ),
+        "early_techmap": attr.label(
+            allow_single_file = True,
+            mandatory = False,
+            doc = "verilog/system verilog file for early techmap process",
+        ),
         "extra_tcl_command": attr.string(
             default = "",
         ),
@@ -399,11 +404,6 @@ synthesize_rtl = rule(
             executable = True,
             cfg = "exec",
         ),
-        "early_techmap": attr.label(
-            allow_single_file = True,
-            mandatory = False,
-            doc = "verilog/system verilog file for early techmap process"
-        ),
     },
 )