WIP: Add icc_igrpen1_el3 too.

Author: qwandor

src/sysreg.rs

@@ -22,6 +22,7 @@ write_sysreg32!(icc_ctlr_el1, 0, c12, c12, 4, write_icc_ctlr_el1);
 write_sysreg32!(icc_eoir1_el1, 0, c12, c12, 1, write_icc_eoir1_el1);
 write_sysreg32!(icc_igrpen0_el1, 0, c12, c12, 6, write_icc_igrpen0_el1);
 write_sysreg32!(icc_igrpen1_el1, 0, c12, c12, 7, write_icc_igrpen1_el1);
+write_sysreg32!(icc_igrpen1_el3, 6, c12, c12, 7, write_icc_igrpen1_el3);
 write_sysreg32!(icc_pmr_el1, 0, c4, c6, 0, write_icc_pmr_el1);
 write_sysreg64!(icc_sgi1r_el1, 0, c12, write_icc_sgi1r_el1);
 write_sysreg32!(icc_sre_el1, 0, c12, c12, 5, write_icc_sre_el1, IccSre);
@@ -38,5 +39,8 @@ bitflags! {
         const DFB = 1 << 1;
         /// Disable IRQ bypass.
         const DIB = 1 << 2;
+        // TODO: Should this be on a different type? Not all registers have it.
+        /// Enables lower EL access to ICC_SRE_ELn.
+        const ENABLE = 1 << 3;
     }
 }