Generic IP Core Synthesis?

[FallenXV]

I am an undergraduate researching on integrating my LSTM Autoencoder model into low power FPGAs (particularly Intel Cyclone 10LP series). There are a few implementation of similar approaches in multiple papers, but I can't seem to find a way to automatically synthesize ANN models using publicly available resources.

My question: Is there a way to synthesize my model into generic IP cores instead of a .qsys file with Intel HLS Compiler or Vivado/Vitis's approach?

Problem with Intel HLS Compiler:

• Intel Quartus Prime Pro/Standard HLS Compiler does not support Cyclone 10LP

Problem with Vitis HLS:

• I have trouble understanding how to transfer the results into Intel Quartus (or if even possible)

[calad0i]

Not sure with Intel, in viavdo you can fetch the generated hdl source files under the syn/ or impl/ directory.

[jmitrevs]

I think with oneAPI you can get the sytem verilog output, but I am not positive if it can be used directly. In build/myproject.report.prj/kernel_hdl/Myproject I see, for example, Myproject_function.sv. I have only used the IP using qsys, though.